BaseCPU.py revision 9544
18839Sandreas.hansson@arm.com# Copyright (c) 2012 ARM Limited 28839Sandreas.hansson@arm.com# All rights reserved. 38839Sandreas.hansson@arm.com# 48839Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 58839Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 68839Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 78839Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 88839Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 98839Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 108839Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 118839Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 128839Sandreas.hansson@arm.com# 135335Shines@cs.fsu.edu# Copyright (c) 2005-2008 The Regents of The University of Michigan 147897Shestness@cs.utexas.edu# Copyright (c) 2011 Regents of the University of California 154486Sbinkertn@umich.edu# All rights reserved. 164486Sbinkertn@umich.edu# 174486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 184486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 194486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 204486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 214486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 224486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 234486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 244486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 254486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 264486Sbinkertn@umich.edu# this software without specific prior written permission. 274486Sbinkertn@umich.edu# 284486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 324486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 364486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 384486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394486Sbinkertn@umich.edu# 404486Sbinkertn@umich.edu# Authors: Nathan Binkert 417897Shestness@cs.utexas.edu# Rick Strong 428839Sandreas.hansson@arm.com# Andreas Hansson 434486Sbinkertn@umich.edu 446654Snate@binkert.orgimport sys 456654Snate@binkert.org 466654Snate@binkert.orgfrom m5.defines import buildEnv 473102SN/Afrom m5.params import * 483102SN/Afrom m5.proxy import * 496654Snate@binkert.org 509036Sandreas.hansson@arm.comfrom Bus import CoherentBus 514776Sgblack@eecs.umich.edufrom InstTracer import InstTracer 524776Sgblack@eecs.umich.edufrom ExeTracer import ExeTracer 536654Snate@binkert.orgfrom MemObject import MemObject 549480Snilay@cs.wisc.edufrom BranchPredictor import BranchPredictor 552667SN/A 564776Sgblack@eecs.umich.edudefault_tracer = ExeTracer() 574776Sgblack@eecs.umich.edu 586654Snate@binkert.orgif buildEnv['TARGET_ISA'] == 'alpha': 596023Snate@binkert.org from AlphaTLB import AlphaDTB, AlphaITB 608745Sgblack@eecs.umich.edu from AlphaInterrupts import AlphaInterrupts 619384SAndreas.Sandberg@arm.com from AlphaISA import AlphaISA 629384SAndreas.Sandberg@arm.com isa_class = AlphaISA 636654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'sparc': 646022Sgblack@eecs.umich.edu from SparcTLB import SparcTLB 658745Sgblack@eecs.umich.edu from SparcInterrupts import SparcInterrupts 669384SAndreas.Sandberg@arm.com from SparcISA import SparcISA 679384SAndreas.Sandberg@arm.com isa_class = SparcISA 686654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'x86': 696022Sgblack@eecs.umich.edu from X86TLB import X86TLB 708745Sgblack@eecs.umich.edu from X86LocalApic import X86LocalApic 719384SAndreas.Sandberg@arm.com from X86ISA import X86ISA 729384SAndreas.Sandberg@arm.com isa_class = X86ISA 736654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'mips': 746022Sgblack@eecs.umich.edu from MipsTLB import MipsTLB 758745Sgblack@eecs.umich.edu from MipsInterrupts import MipsInterrupts 769384SAndreas.Sandberg@arm.com from MipsISA import MipsISA 779384SAndreas.Sandberg@arm.com isa_class = MipsISA 786654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'arm': 796116Snate@binkert.org from ArmTLB import ArmTLB 808745Sgblack@eecs.umich.edu from ArmInterrupts import ArmInterrupts 819384SAndreas.Sandberg@arm.com from ArmISA import ArmISA 829384SAndreas.Sandberg@arm.com isa_class = ArmISA 836691Stjones1@inf.ed.ac.ukelif buildEnv['TARGET_ISA'] == 'power': 846691Stjones1@inf.ed.ac.uk from PowerTLB import PowerTLB 858745Sgblack@eecs.umich.edu from PowerInterrupts import PowerInterrupts 869384SAndreas.Sandberg@arm.com from PowerISA import PowerISA 879384SAndreas.Sandberg@arm.com isa_class = PowerISA 884486Sbinkertn@umich.edu 895529Snate@binkert.orgclass BaseCPU(MemObject): 901366SN/A type = 'BaseCPU' 911310SN/A abstract = True 929338SAndreas.Sandberg@arm.com cxx_header = "cpu/base.hh" 939254SAndreas.Sandberg@arm.com 949254SAndreas.Sandberg@arm.com @classmethod 959254SAndreas.Sandberg@arm.com def export_methods(cls, code): 969254SAndreas.Sandberg@arm.com code(''' 979254SAndreas.Sandberg@arm.com void switchOut(); 989254SAndreas.Sandberg@arm.com void takeOverFrom(BaseCPU *cpu); 999430SAndreas.Sandberg@ARM.com bool switchedOut(); 1009446SAndreas.Sandberg@ARM.com void flushTLBs(); 1019254SAndreas.Sandberg@arm.com''') 1029254SAndreas.Sandberg@arm.com 1039518SAndreas.Sandberg@ARM.com @classmethod 1049518SAndreas.Sandberg@ARM.com def memory_mode(cls): 1059518SAndreas.Sandberg@ARM.com """Which memory mode does this CPU require?""" 1069518SAndreas.Sandberg@ARM.com return 'invalid' 1079518SAndreas.Sandberg@ARM.com 1089518SAndreas.Sandberg@ARM.com @classmethod 1099518SAndreas.Sandberg@ARM.com def require_caches(cls): 1109518SAndreas.Sandberg@ARM.com """Does the CPU model require caches? 1119518SAndreas.Sandberg@ARM.com 1129518SAndreas.Sandberg@ARM.com Some CPU models might make assumptions that require them to 1139518SAndreas.Sandberg@ARM.com have caches. 1149518SAndreas.Sandberg@ARM.com """ 1159518SAndreas.Sandberg@ARM.com return False 1169518SAndreas.Sandberg@ARM.com 1179518SAndreas.Sandberg@ARM.com @classmethod 1189518SAndreas.Sandberg@ARM.com def support_take_over(cls): 1199518SAndreas.Sandberg@ARM.com """Does the CPU model support CPU takeOverFrom?""" 1209518SAndreas.Sandberg@ARM.com return False 1219518SAndreas.Sandberg@ARM.com 1229254SAndreas.Sandberg@arm.com def takeOverFrom(self, old_cpu): 1239254SAndreas.Sandberg@arm.com self._ccObject.takeOverFrom(old_cpu._ccObject) 1249254SAndreas.Sandberg@arm.com 1259254SAndreas.Sandberg@arm.com 1262901SN/A system = Param.System(Parent.any, "system object") 1275712Shsul@eecs.umich.edu cpu_id = Param.Int(-1, "CPU identifier") 1285529Snate@binkert.org numThreads = Param.Unsigned(1, "number of HW thread contexts") 1295529Snate@binkert.org 1305529Snate@binkert.org function_trace = Param.Bool(False, "Enable function trace") 1319161Sandreas.hansson@arm.com function_trace_start = Param.Tick(0, "Tick to start function trace") 1325529Snate@binkert.org 1335821Ssaidi@eecs.umich.edu checker = Param.BaseCPU(NULL, "checker CPU") 1343170SN/A 1355780Ssteve.reinhardt@amd.com do_checkpoint_insts = Param.Bool(True, 1365780Ssteve.reinhardt@amd.com "enable checkpoint pseudo instructions") 1375780Ssteve.reinhardt@amd.com do_statistics_insts = Param.Bool(True, 1385780Ssteve.reinhardt@amd.com "enable statistics pseudo instructions") 1395780Ssteve.reinhardt@amd.com 1408784Sgblack@eecs.umich.edu profile = Param.Latency('0ns', "trace the kernel stack") 1418784Sgblack@eecs.umich.edu do_quiesce = Param.Bool(True, "enable quiesce instructions") 1428784Sgblack@eecs.umich.edu 1438793Sgblack@eecs.umich.edu workload = VectorParam.Process([], "processes to run") 1441310SN/A 1456654Snate@binkert.org if buildEnv['TARGET_ISA'] == 'sparc': 1466022Sgblack@eecs.umich.edu dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 1476022Sgblack@eecs.umich.edu itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") 1488745Sgblack@eecs.umich.edu interrupts = Param.SparcInterrupts( 1498863Snilay@cs.wisc.edu NULL, "Interrupt Controller") 1509384SAndreas.Sandberg@arm.com isa = VectorParam.SparcISA([ isa_class() ], "ISA instance") 1516654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'alpha': 1526023Snate@binkert.org dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 1536023Snate@binkert.org itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") 1548745Sgblack@eecs.umich.edu interrupts = Param.AlphaInterrupts( 1558863Snilay@cs.wisc.edu NULL, "Interrupt Controller") 1569384SAndreas.Sandberg@arm.com isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance") 1576654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'x86': 1586022Sgblack@eecs.umich.edu dtb = Param.X86TLB(X86TLB(), "Data TLB") 1596022Sgblack@eecs.umich.edu itb = Param.X86TLB(X86TLB(), "Instruction TLB") 1608863Snilay@cs.wisc.edu interrupts = Param.X86LocalApic(NULL, "Interrupt Controller") 1619384SAndreas.Sandberg@arm.com isa = VectorParam.X86ISA([ isa_class() ], "ISA instance") 1626654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'mips': 1636022Sgblack@eecs.umich.edu dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 1646022Sgblack@eecs.umich.edu itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") 1658745Sgblack@eecs.umich.edu interrupts = Param.MipsInterrupts( 1668863Snilay@cs.wisc.edu NULL, "Interrupt Controller") 1679384SAndreas.Sandberg@arm.com isa = VectorParam.MipsISA([ isa_class() ], "ISA instance") 1686654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'arm': 1696116Snate@binkert.org dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 1706116Snate@binkert.org itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") 1718745Sgblack@eecs.umich.edu interrupts = Param.ArmInterrupts( 1728863Snilay@cs.wisc.edu NULL, "Interrupt Controller") 1739384SAndreas.Sandberg@arm.com isa = VectorParam.ArmISA([ isa_class() ], "ISA instance") 1746691Stjones1@inf.ed.ac.uk elif buildEnv['TARGET_ISA'] == 'power': 1756691Stjones1@inf.ed.ac.uk UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 1766691Stjones1@inf.ed.ac.uk dtb = Param.PowerTLB(PowerTLB(), "Data TLB") 1776691Stjones1@inf.ed.ac.uk itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") 1788745Sgblack@eecs.umich.edu interrupts = Param.PowerInterrupts( 1798863Snilay@cs.wisc.edu NULL, "Interrupt Controller") 1809384SAndreas.Sandberg@arm.com isa = VectorParam.PowerISA([ isa_class() ], "ISA instance") 1814997Sgblack@eecs.umich.edu else: 1824997Sgblack@eecs.umich.edu print "Don't know what TLB to use for ISA %s" % \ 1836654Snate@binkert.org buildEnv['TARGET_ISA'] 1844997Sgblack@eecs.umich.edu sys.exit(1) 1854997Sgblack@eecs.umich.edu 1861310SN/A max_insts_all_threads = Param.Counter(0, 1871310SN/A "terminate when all threads have reached this inst count") 1881310SN/A max_insts_any_thread = Param.Counter(0, 1891310SN/A "terminate when any thread reaches this inst count") 1901310SN/A max_loads_all_threads = Param.Counter(0, 1911310SN/A "terminate when all threads have reached this load count") 1921310SN/A max_loads_any_thread = Param.Counter(0, 1931310SN/A "terminate when any thread reaches this load count") 1949180Sandreas.hansson@arm.com progress_interval = Param.Frequency('0Hz', 1959180Sandreas.hansson@arm.com "frequency to print out the progress message") 1961310SN/A 1979433SAndreas.Sandberg@ARM.com switched_out = Param.Bool(False, 1989433SAndreas.Sandberg@ARM.com "Leave the CPU switched out after startup (used when switching " \ 1999433SAndreas.Sandberg@ARM.com "between CPU models)") 2001634SN/A 2014776Sgblack@eecs.umich.edu tracer = Param.InstTracer(default_tracer, "Instruction tracer") 2024776Sgblack@eecs.umich.edu 2038839Sandreas.hansson@arm.com icache_port = MasterPort("Instruction Port") 2048839Sandreas.hansson@arm.com dcache_port = MasterPort("Data Port") 2058707Sandreas.hansson@arm.com _cached_ports = ['icache_port', 'dcache_port'] 2068707Sandreas.hansson@arm.com 2079480Snilay@cs.wisc.edu branchPred = Param.BranchPredictor(NULL, "Branch Predictor") 2089480Snilay@cs.wisc.edu 2098756Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 2108707Sandreas.hansson@arm.com _cached_ports += ["itb.walker.port", "dtb.walker.port"] 2117876Sgblack@eecs.umich.edu 2128839Sandreas.hansson@arm.com _uncached_slave_ports = [] 2138839Sandreas.hansson@arm.com _uncached_master_ports = [] 2148745Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'x86': 2158839Sandreas.hansson@arm.com _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"] 2168839Sandreas.hansson@arm.com _uncached_master_ports += ["interrupts.int_master"] 2172998SN/A 2188863Snilay@cs.wisc.edu def createInterruptController(self): 2198863Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] == 'sparc': 2208863Snilay@cs.wisc.edu self.interrupts = SparcInterrupts() 2218863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'alpha': 2228863Snilay@cs.wisc.edu self.interrupts = AlphaInterrupts() 2238863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'x86': 2249544Sandreas.hansson@arm.com self.interrupts = X86LocalApic(clock = Parent.clock * 16, 2259544Sandreas.hansson@arm.com pio_addr=0x2000000000000000) 2269544Sandreas.hansson@arm.com _localApic = self.interrupts 2278863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'mips': 2288863Snilay@cs.wisc.edu self.interrupts = MipsInterrupts() 2298863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'arm': 2308863Snilay@cs.wisc.edu self.interrupts = ArmInterrupts() 2318863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'power': 2328863Snilay@cs.wisc.edu self.interrupts = PowerInterrupts() 2338863Snilay@cs.wisc.edu else: 2348863Snilay@cs.wisc.edu print "Don't know what Interrupt Controller to use for ISA %s" % \ 2358863Snilay@cs.wisc.edu buildEnv['TARGET_ISA'] 2368863Snilay@cs.wisc.edu sys.exit(1) 2378863Snilay@cs.wisc.edu 2387876Sgblack@eecs.umich.edu def connectCachedPorts(self, bus): 2397876Sgblack@eecs.umich.edu for p in self._cached_ports: 2408839Sandreas.hansson@arm.com exec('self.%s = bus.slave' % p) 2417404SAli.Saidi@ARM.com 2427876Sgblack@eecs.umich.edu def connectUncachedPorts(self, bus): 2438839Sandreas.hansson@arm.com for p in self._uncached_slave_ports: 2448839Sandreas.hansson@arm.com exec('self.%s = bus.master' % p) 2458839Sandreas.hansson@arm.com for p in self._uncached_master_ports: 2468839Sandreas.hansson@arm.com exec('self.%s = bus.slave' % p) 2477876Sgblack@eecs.umich.edu 2487876Sgblack@eecs.umich.edu def connectAllPorts(self, cached_bus, uncached_bus = None): 2497876Sgblack@eecs.umich.edu self.connectCachedPorts(cached_bus) 2507876Sgblack@eecs.umich.edu if not uncached_bus: 2517876Sgblack@eecs.umich.edu uncached_bus = cached_bus 2527876Sgblack@eecs.umich.edu self.connectUncachedPorts(uncached_bus) 2532998SN/A 2547868Sgblack@eecs.umich.edu def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 2552998SN/A self.icache = ic 2562998SN/A self.dcache = dc 2572998SN/A self.icache_port = ic.cpu_side 2582998SN/A self.dcache_port = dc.cpu_side 2597876Sgblack@eecs.umich.edu self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 2608796Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 2618796Sgblack@eecs.umich.edu if iwc and dwc: 2628796Sgblack@eecs.umich.edu self.itb_walker_cache = iwc 2638796Sgblack@eecs.umich.edu self.dtb_walker_cache = dwc 2648796Sgblack@eecs.umich.edu self.itb.walker.port = iwc.cpu_side 2658796Sgblack@eecs.umich.edu self.dtb.walker.port = dwc.cpu_side 2668796Sgblack@eecs.umich.edu self._cached_ports += ["itb_walker_cache.mem_side", \ 2678796Sgblack@eecs.umich.edu "dtb_walker_cache.mem_side"] 2688796Sgblack@eecs.umich.edu else: 2698796Sgblack@eecs.umich.edu self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 2708887Sgeoffrey.blake@arm.com 2718809Sgblack@eecs.umich.edu # Checker doesn't need its own tlb caches because it does 2728809Sgblack@eecs.umich.edu # functional accesses only 2738887Sgeoffrey.blake@arm.com if self.checker != NULL: 2748809Sgblack@eecs.umich.edu self._cached_ports += ["checker.itb.walker.port", \ 2758809Sgblack@eecs.umich.edu "checker.dtb.walker.port"] 2762998SN/A 2777868Sgblack@eecs.umich.edu def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 2787868Sgblack@eecs.umich.edu self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 2799284Sandreas.hansson@arm.com # Override the default bus clock of 1 GHz and uses the CPU 2809284Sandreas.hansson@arm.com # clock for the L1-to-L2 bus, and also set a width of 32 bytes 2819284Sandreas.hansson@arm.com # (256-bits), which is four times that of the default bus. 2829284Sandreas.hansson@arm.com self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32) 2837876Sgblack@eecs.umich.edu self.connectCachedPorts(self.toL2Bus) 2842998SN/A self.l2cache = l2c 2858839Sandreas.hansson@arm.com self.toL2Bus.master = self.l2cache.cpu_side 2867876Sgblack@eecs.umich.edu self._cached_ports = ['l2cache.mem_side'] 2878887Sgeoffrey.blake@arm.com 2889384SAndreas.Sandberg@arm.com def createThreads(self): 2899384SAndreas.Sandberg@arm.com self.isa = [ isa_class() for i in xrange(self.numThreads) ] 2909384SAndreas.Sandberg@arm.com if self.checker != NULL: 2919384SAndreas.Sandberg@arm.com self.checker.createThreads() 2929384SAndreas.Sandberg@arm.com 2938887Sgeoffrey.blake@arm.com def addCheckerCpu(self): 2948887Sgeoffrey.blake@arm.com pass 295