BaseCPU.py revision 9433
11689SN/A# Copyright (c) 2012 ARM Limited 212106SRekai.GonzalezAlberquilla@arm.com# All rights reserved. 39913Ssteve.reinhardt@amd.com# 47854SAli.Saidi@ARM.com# The license below extends only to copyright in the software and shall 57854SAli.Saidi@ARM.com# not be construed as granting a license to any other intellectual 67854SAli.Saidi@ARM.com# property including but not limited to intellectual property relating 77854SAli.Saidi@ARM.com# to a hardware implementation of the functionality of the software 87854SAli.Saidi@ARM.com# licensed hereunder. You may use the software subject to the license 97854SAli.Saidi@ARM.com# terms below provided that you ensure that this notice is replicated 107854SAli.Saidi@ARM.com# unmodified and in its entirety in all distributions of the software, 117854SAli.Saidi@ARM.com# modified or unmodified, in source code or in binary form. 127854SAli.Saidi@ARM.com# 137854SAli.Saidi@ARM.com# Copyright (c) 2005-2008 The Regents of The University of Michigan 147854SAli.Saidi@ARM.com# Copyright (c) 2011 Regents of the University of California 152329SN/A# All rights reserved. 161689SN/A# 171689SN/A# Redistribution and use in source and binary forms, with or without 181689SN/A# modification, are permitted provided that the following conditions are 191689SN/A# met: redistributions of source code must retain the above copyright 201689SN/A# notice, this list of conditions and the following disclaimer; 211689SN/A# redistributions in binary form must reproduce the above copyright 221689SN/A# notice, this list of conditions and the following disclaimer in the 231689SN/A# documentation and/or other materials provided with the distribution; 241689SN/A# neither the name of the copyright holders nor the names of its 251689SN/A# contributors may be used to endorse or promote products derived from 261689SN/A# this software without specific prior written permission. 271689SN/A# 281689SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 391689SN/A# 402665Ssaidi@eecs.umich.edu# Authors: Nathan Binkert 412665Ssaidi@eecs.umich.edu# Rick Strong 422935Sksewell@umich.edu# Andreas Hansson 431689SN/A 441689SN/Aimport sys 459944Smatt.horsnell@ARM.com 469944Smatt.horsnell@ARM.comfrom m5.defines import buildEnv 479944Smatt.horsnell@ARM.comfrom m5.params import * 481060SN/Afrom m5.proxy import * 491060SN/A 503773Sgblack@eecs.umich.edufrom Bus import CoherentBus 516329Sgblack@eecs.umich.edufrom InstTracer import InstTracer 526658Snate@binkert.orgfrom ExeTracer import ExeTracer 531717SN/Afrom MemObject import MemObject 549913Ssteve.reinhardt@amd.com 558232Snate@binkert.orgdefault_tracer = ExeTracer() 568232Snate@binkert.org 579527SMatt.Horsnell@arm.comif buildEnv['TARGET_ISA'] == 'alpha': 585529Snate@binkert.org from AlphaTLB import AlphaDTB, AlphaITB 591060SN/A from AlphaInterrupts import AlphaInterrupts 606221Snate@binkert.org from AlphaISA import AlphaISA 616221Snate@binkert.org isa_class = AlphaISA 621061SN/Aelif buildEnv['TARGET_ISA'] == 'sparc': 635529Snate@binkert.org from SparcTLB import SparcTLB 644329Sktlim@umich.edu from SparcInterrupts import SparcInterrupts 654329Sktlim@umich.edu from SparcISA import SparcISA 662292SN/A isa_class = SparcISA 672292SN/Aelif buildEnv['TARGET_ISA'] == 'x86': 682292SN/A from X86TLB import X86TLB 692292SN/A from X86LocalApic import X86LocalApic 705529Snate@binkert.org from X86ISA import X86ISA 719920Syasuko.eckert@amd.com isa_class = X86ISA 7210935Snilay@cs.wisc.eduelif buildEnv['TARGET_ISA'] == 'mips': 731060SN/A from MipsTLB import MipsTLB 7410172Sdam.sunwoo@arm.com from MipsInterrupts import MipsInterrupts 7510172Sdam.sunwoo@arm.com from MipsISA import MipsISA 7610172Sdam.sunwoo@arm.com isa_class = MipsISA 7710172Sdam.sunwoo@arm.comelif buildEnv['TARGET_ISA'] == 'arm': 7810172Sdam.sunwoo@arm.com from ArmTLB import ArmTLB 792292SN/A from ArmInterrupts import ArmInterrupts 8010328Smitch.hayenga@arm.com from ArmISA import ArmISA 812292SN/A isa_class = ArmISA 822292SN/Aelif buildEnv['TARGET_ISA'] == 'power': 832292SN/A from PowerTLB import PowerTLB 842292SN/A from PowerInterrupts import PowerInterrupts 852292SN/A from PowerISA import PowerISA 862292SN/A isa_class = PowerISA 872292SN/A 881060SN/Aclass BaseCPU(MemObject): 891060SN/A type = 'BaseCPU' 901061SN/A abstract = True 911060SN/A cxx_header = "cpu/base.hh" 922292SN/A 931062SN/A @classmethod 941062SN/A def export_methods(cls, code): 958240Snate@binkert.org code(''' 961062SN/A void switchOut(); 971062SN/A void takeOverFrom(BaseCPU *cpu); 981062SN/A bool switchedOut(); 998240Snate@binkert.org''') 1001062SN/A 1011062SN/A def takeOverFrom(self, old_cpu): 1021062SN/A self._ccObject.takeOverFrom(old_cpu._ccObject) 1038240Snate@binkert.org 1041062SN/A 1051062SN/A system = Param.System(Parent.any, "system object") 1062301SN/A cpu_id = Param.Int(-1, "CPU identifier") 1078240Snate@binkert.org numThreads = Param.Unsigned(1, "number of HW thread contexts") 1082301SN/A 1092301SN/A function_trace = Param.Bool(False, "Enable function trace") 1102292SN/A function_trace_start = Param.Tick(0, "Tick to start function trace") 1118240Snate@binkert.org 1122292SN/A checker = Param.BaseCPU(NULL, "checker CPU") 1132292SN/A 1141062SN/A do_checkpoint_insts = Param.Bool(True, 1158240Snate@binkert.org "enable checkpoint pseudo instructions") 1161062SN/A do_statistics_insts = Param.Bool(True, 1171062SN/A "enable statistics pseudo instructions") 1181062SN/A 1198240Snate@binkert.org profile = Param.Latency('0ns', "trace the kernel stack") 1201062SN/A do_quiesce = Param.Bool(True, "enable quiesce instructions") 1211062SN/A 1221062SN/A workload = VectorParam.Process([], "processes to run") 1238240Snate@binkert.org 1241062SN/A if buildEnv['TARGET_ISA'] == 'sparc': 1251062SN/A dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 1261062SN/A itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") 1278240Snate@binkert.org interrupts = Param.SparcInterrupts( 1282292SN/A NULL, "Interrupt Controller") 1291062SN/A isa = VectorParam.SparcISA([ isa_class() ], "ISA instance") 1301062SN/A elif buildEnv['TARGET_ISA'] == 'alpha': 1318240Snate@binkert.org dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 1322292SN/A itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") 1331062SN/A interrupts = Param.AlphaInterrupts( 13410239Sbinhpham@cs.rutgers.edu NULL, "Interrupt Controller") 13510239Sbinhpham@cs.rutgers.edu isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance") 13610239Sbinhpham@cs.rutgers.edu elif buildEnv['TARGET_ISA'] == 'x86': 13710239Sbinhpham@cs.rutgers.edu dtb = Param.X86TLB(X86TLB(), "Data TLB") 13810239Sbinhpham@cs.rutgers.edu itb = Param.X86TLB(X86TLB(), "Instruction TLB") 13910239Sbinhpham@cs.rutgers.edu interrupts = Param.X86LocalApic(NULL, "Interrupt Controller") 14010239Sbinhpham@cs.rutgers.edu isa = VectorParam.X86ISA([ isa_class() ], "ISA instance") 14110239Sbinhpham@cs.rutgers.edu elif buildEnv['TARGET_ISA'] == 'mips': 1421062SN/A dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 1438240Snate@binkert.org itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") 1441062SN/A interrupts = Param.MipsInterrupts( 1451062SN/A NULL, "Interrupt Controller") 1461062SN/A isa = VectorParam.MipsISA([ isa_class() ], "ISA instance") 1478240Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'arm': 1481062SN/A dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 1491062SN/A itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") 1501062SN/A interrupts = Param.ArmInterrupts( 1518240Snate@binkert.org NULL, "Interrupt Controller") 1521062SN/A isa = VectorParam.ArmISA([ isa_class() ], "ISA instance") 1531062SN/A elif buildEnv['TARGET_ISA'] == 'power': 1541062SN/A UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 1558240Snate@binkert.org dtb = Param.PowerTLB(PowerTLB(), "Data TLB") 1561062SN/A itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") 1571062SN/A interrupts = Param.PowerInterrupts( 1581062SN/A NULL, "Interrupt Controller") 1598240Snate@binkert.org isa = VectorParam.PowerISA([ isa_class() ], "ISA instance") 1601062SN/A else: 1611062SN/A print "Don't know what TLB to use for ISA %s" % \ 1622301SN/A buildEnv['TARGET_ISA'] 1638240Snate@binkert.org sys.exit(1) 1642301SN/A 1652301SN/A max_insts_all_threads = Param.Counter(0, 1662301SN/A "terminate when all threads have reached this inst count") 1672301SN/A max_insts_any_thread = Param.Counter(0, 1688240Snate@binkert.org "terminate when any thread reaches this inst count") 1692301SN/A max_loads_all_threads = Param.Counter(0, 1702301SN/A "terminate when all threads have reached this load count") 1712301SN/A max_loads_any_thread = Param.Counter(0, 1722307SN/A "terminate when any thread reaches this load count") 1738240Snate@binkert.org progress_interval = Param.Frequency('0Hz', 1742307SN/A "frequency to print out the progress message") 1752307SN/A 1762307SN/A switched_out = Param.Bool(False, 1777897Shestness@cs.utexas.edu "Leave the CPU switched out after startup (used when switching " \ 1788240Snate@binkert.org "between CPU models)") 1797897Shestness@cs.utexas.edu 1807897Shestness@cs.utexas.edu tracer = Param.InstTracer(default_tracer, "Instruction tracer") 1817897Shestness@cs.utexas.edu 1828240Snate@binkert.org icache_port = MasterPort("Instruction Port") 1837897Shestness@cs.utexas.edu dcache_port = MasterPort("Data Port") 1847897Shestness@cs.utexas.edu _cached_ports = ['icache_port', 'dcache_port'] 1851062SN/A 1861062SN/A if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 1871062SN/A _cached_ports += ["itb.walker.port", "dtb.walker.port"] 1881062SN/A 18911246Sradhika.jagtap@ARM.com _uncached_slave_ports = [] 19011246Sradhika.jagtap@ARM.com _uncached_master_ports = [] 19111246Sradhika.jagtap@ARM.com if buildEnv['TARGET_ISA'] == 'x86': 19211246Sradhika.jagtap@ARM.com _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"] 19311246Sradhika.jagtap@ARM.com _uncached_master_ports += ["interrupts.int_master"] 19411246Sradhika.jagtap@ARM.com 19511246Sradhika.jagtap@ARM.com def createInterruptController(self): 19611246Sradhika.jagtap@ARM.com if buildEnv['TARGET_ISA'] == 'sparc': 19711246Sradhika.jagtap@ARM.com self.interrupts = SparcInterrupts() 1982292SN/A elif buildEnv['TARGET_ISA'] == 'alpha': 1991060SN/A self.interrupts = AlphaInterrupts() 2001060SN/A elif buildEnv['TARGET_ISA'] == 'x86': 2011060SN/A _localApic = X86LocalApic(pio_addr=0x2000000000000000) 2021060SN/A self.interrupts = _localApic 2031060SN/A elif buildEnv['TARGET_ISA'] == 'mips': 2041060SN/A self.interrupts = MipsInterrupts() 2051060SN/A elif buildEnv['TARGET_ISA'] == 'arm': 2061060SN/A self.interrupts = ArmInterrupts() 2071060SN/A elif buildEnv['TARGET_ISA'] == 'power': 2081060SN/A self.interrupts = PowerInterrupts() 2091060SN/A else: 2101060SN/A print "Don't know what Interrupt Controller to use for ISA %s" % \ 2111060SN/A buildEnv['TARGET_ISA'] 2121061SN/A sys.exit(1) 2131060SN/A 2142292SN/A def connectCachedPorts(self, bus): 2151060SN/A for p in self._cached_ports: 2161060SN/A exec('self.%s = bus.slave' % p) 2171060SN/A 2181060SN/A def connectUncachedPorts(self, bus): 2191060SN/A for p in self._uncached_slave_ports: 2201060SN/A exec('self.%s = bus.master' % p) 2211060SN/A for p in self._uncached_master_ports: 2221061SN/A exec('self.%s = bus.slave' % p) 2231060SN/A 2242292SN/A def connectAllPorts(self, cached_bus, uncached_bus = None): 2251060SN/A self.connectCachedPorts(cached_bus) 2261060SN/A if not uncached_bus: 2271060SN/A uncached_bus = cached_bus 2281060SN/A self.connectUncachedPorts(uncached_bus) 2291060SN/A 2301060SN/A def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 2311060SN/A self.icache = ic 2321061SN/A self.dcache = dc 2331060SN/A self.icache_port = ic.cpu_side 2349427SAndreas.Sandberg@ARM.com self.dcache_port = dc.cpu_side 2351060SN/A self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 2369444SAndreas.Sandberg@ARM.com if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 2379444SAndreas.Sandberg@ARM.com if iwc and dwc: 2389444SAndreas.Sandberg@ARM.com self.itb_walker_cache = iwc 2399444SAndreas.Sandberg@ARM.com self.dtb_walker_cache = dwc 2409444SAndreas.Sandberg@ARM.com self.itb.walker.port = iwc.cpu_side 2419444SAndreas.Sandberg@ARM.com self.dtb.walker.port = dwc.cpu_side 2429444SAndreas.Sandberg@ARM.com self._cached_ports += ["itb_walker_cache.mem_side", \ 2439444SAndreas.Sandberg@ARM.com "dtb_walker_cache.mem_side"] 2449444SAndreas.Sandberg@ARM.com else: 2459444SAndreas.Sandberg@ARM.com self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 2469444SAndreas.Sandberg@ARM.com 2479444SAndreas.Sandberg@ARM.com # Checker doesn't need its own tlb caches because it does 2482329SN/A # functional accesses only 2496221Snate@binkert.org if self.checker != NULL: 2509444SAndreas.Sandberg@ARM.com self._cached_ports += ["checker.itb.walker.port", \ 2519444SAndreas.Sandberg@ARM.com "checker.dtb.walker.port"] 2522292SN/A 25310239Sbinhpham@cs.rutgers.edu def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 25410239Sbinhpham@cs.rutgers.edu self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 2552292SN/A # Override the default bus clock of 1 GHz and uses the CPU 2562292SN/A # clock for the L1-to-L2 bus, and also set a width of 32 bytes 2579444SAndreas.Sandberg@ARM.com # (256-bits), which is four times that of the default bus. 2589444SAndreas.Sandberg@ARM.com self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32) 2599444SAndreas.Sandberg@ARM.com self.connectCachedPorts(self.toL2Bus) 2609444SAndreas.Sandberg@ARM.com self.l2cache = l2c 2619444SAndreas.Sandberg@ARM.com self.toL2Bus.master = self.l2cache.cpu_side 26210239Sbinhpham@cs.rutgers.edu self._cached_ports = ['l2cache.mem_side'] 26310239Sbinhpham@cs.rutgers.edu 2649444SAndreas.Sandberg@ARM.com def createThreads(self): 2659444SAndreas.Sandberg@ARM.com self.isa = [ isa_class() for i in xrange(self.numThreads) ] 2662292SN/A if self.checker != NULL: 2671060SN/A self.checker.createThreads() 2681060SN/A 2692292SN/A def addCheckerCpu(self): 2702292SN/A pass 2716221Snate@binkert.org