BaseCPU.py revision 9430
18839Sandreas.hansson@arm.com# Copyright (c) 2012 ARM Limited 28839Sandreas.hansson@arm.com# All rights reserved. 38839Sandreas.hansson@arm.com# 48839Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 58839Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 68839Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 78839Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 88839Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 98839Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 108839Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 118839Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 128839Sandreas.hansson@arm.com# 135335Shines@cs.fsu.edu# Copyright (c) 2005-2008 The Regents of The University of Michigan 147897Shestness@cs.utexas.edu# Copyright (c) 2011 Regents of the University of California 154486Sbinkertn@umich.edu# All rights reserved. 164486Sbinkertn@umich.edu# 174486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 184486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 194486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 204486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 214486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 224486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 234486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 244486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 254486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 264486Sbinkertn@umich.edu# this software without specific prior written permission. 274486Sbinkertn@umich.edu# 284486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 324486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 364486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 384486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394486Sbinkertn@umich.edu# 404486Sbinkertn@umich.edu# Authors: Nathan Binkert 417897Shestness@cs.utexas.edu# Rick Strong 428839Sandreas.hansson@arm.com# Andreas Hansson 434486Sbinkertn@umich.edu 446654Snate@binkert.orgimport sys 456654Snate@binkert.org 466654Snate@binkert.orgfrom m5.defines import buildEnv 473102SN/Afrom m5.params import * 483102SN/Afrom m5.proxy import * 496654Snate@binkert.org 509036Sandreas.hansson@arm.comfrom Bus import CoherentBus 514776Sgblack@eecs.umich.edufrom InstTracer import InstTracer 524776Sgblack@eecs.umich.edufrom ExeTracer import ExeTracer 536654Snate@binkert.orgfrom MemObject import MemObject 542667SN/A 554776Sgblack@eecs.umich.edudefault_tracer = ExeTracer() 564776Sgblack@eecs.umich.edu 576654Snate@binkert.orgif buildEnv['TARGET_ISA'] == 'alpha': 586023Snate@binkert.org from AlphaTLB import AlphaDTB, AlphaITB 598745Sgblack@eecs.umich.edu from AlphaInterrupts import AlphaInterrupts 609384SAndreas.Sandberg@arm.com from AlphaISA import AlphaISA 619384SAndreas.Sandberg@arm.com isa_class = AlphaISA 626654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'sparc': 636022Sgblack@eecs.umich.edu from SparcTLB import SparcTLB 648745Sgblack@eecs.umich.edu from SparcInterrupts import SparcInterrupts 659384SAndreas.Sandberg@arm.com from SparcISA import SparcISA 669384SAndreas.Sandberg@arm.com isa_class = SparcISA 676654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'x86': 686022Sgblack@eecs.umich.edu from X86TLB import X86TLB 698745Sgblack@eecs.umich.edu from X86LocalApic import X86LocalApic 709384SAndreas.Sandberg@arm.com from X86ISA import X86ISA 719384SAndreas.Sandberg@arm.com isa_class = X86ISA 726654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'mips': 736022Sgblack@eecs.umich.edu from MipsTLB import MipsTLB 748745Sgblack@eecs.umich.edu from MipsInterrupts import MipsInterrupts 759384SAndreas.Sandberg@arm.com from MipsISA import MipsISA 769384SAndreas.Sandberg@arm.com isa_class = MipsISA 776654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'arm': 786116Snate@binkert.org from ArmTLB import ArmTLB 798745Sgblack@eecs.umich.edu from ArmInterrupts import ArmInterrupts 809384SAndreas.Sandberg@arm.com from ArmISA import ArmISA 819384SAndreas.Sandberg@arm.com isa_class = ArmISA 826691Stjones1@inf.ed.ac.ukelif buildEnv['TARGET_ISA'] == 'power': 836691Stjones1@inf.ed.ac.uk from PowerTLB import PowerTLB 848745Sgblack@eecs.umich.edu from PowerInterrupts import PowerInterrupts 859384SAndreas.Sandberg@arm.com from PowerISA import PowerISA 869384SAndreas.Sandberg@arm.com isa_class = PowerISA 874486Sbinkertn@umich.edu 885529Snate@binkert.orgclass BaseCPU(MemObject): 891366SN/A type = 'BaseCPU' 901310SN/A abstract = True 919338SAndreas.Sandberg@arm.com cxx_header = "cpu/base.hh" 929254SAndreas.Sandberg@arm.com 939254SAndreas.Sandberg@arm.com @classmethod 949254SAndreas.Sandberg@arm.com def export_methods(cls, code): 959254SAndreas.Sandberg@arm.com code(''' 969254SAndreas.Sandberg@arm.com void switchOut(); 979254SAndreas.Sandberg@arm.com void takeOverFrom(BaseCPU *cpu); 989430SAndreas.Sandberg@ARM.com bool switchedOut(); 999254SAndreas.Sandberg@arm.com''') 1009254SAndreas.Sandberg@arm.com 1019254SAndreas.Sandberg@arm.com def takeOverFrom(self, old_cpu): 1029254SAndreas.Sandberg@arm.com self._ccObject.takeOverFrom(old_cpu._ccObject) 1039254SAndreas.Sandberg@arm.com 1049254SAndreas.Sandberg@arm.com 1052901SN/A system = Param.System(Parent.any, "system object") 1065712Shsul@eecs.umich.edu cpu_id = Param.Int(-1, "CPU identifier") 1075529Snate@binkert.org numThreads = Param.Unsigned(1, "number of HW thread contexts") 1085529Snate@binkert.org 1095529Snate@binkert.org function_trace = Param.Bool(False, "Enable function trace") 1109161Sandreas.hansson@arm.com function_trace_start = Param.Tick(0, "Tick to start function trace") 1115529Snate@binkert.org 1125821Ssaidi@eecs.umich.edu checker = Param.BaseCPU(NULL, "checker CPU") 1133170SN/A 1145780Ssteve.reinhardt@amd.com do_checkpoint_insts = Param.Bool(True, 1155780Ssteve.reinhardt@amd.com "enable checkpoint pseudo instructions") 1165780Ssteve.reinhardt@amd.com do_statistics_insts = Param.Bool(True, 1175780Ssteve.reinhardt@amd.com "enable statistics pseudo instructions") 1185780Ssteve.reinhardt@amd.com 1198784Sgblack@eecs.umich.edu profile = Param.Latency('0ns', "trace the kernel stack") 1208784Sgblack@eecs.umich.edu do_quiesce = Param.Bool(True, "enable quiesce instructions") 1218784Sgblack@eecs.umich.edu 1228793Sgblack@eecs.umich.edu workload = VectorParam.Process([], "processes to run") 1231310SN/A 1246654Snate@binkert.org if buildEnv['TARGET_ISA'] == 'sparc': 1256022Sgblack@eecs.umich.edu dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 1266022Sgblack@eecs.umich.edu itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") 1278745Sgblack@eecs.umich.edu interrupts = Param.SparcInterrupts( 1288863Snilay@cs.wisc.edu NULL, "Interrupt Controller") 1299384SAndreas.Sandberg@arm.com isa = VectorParam.SparcISA([ isa_class() ], "ISA instance") 1306654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'alpha': 1316023Snate@binkert.org dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 1326023Snate@binkert.org itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") 1338745Sgblack@eecs.umich.edu interrupts = Param.AlphaInterrupts( 1348863Snilay@cs.wisc.edu NULL, "Interrupt Controller") 1359384SAndreas.Sandberg@arm.com isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance") 1366654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'x86': 1376022Sgblack@eecs.umich.edu dtb = Param.X86TLB(X86TLB(), "Data TLB") 1386022Sgblack@eecs.umich.edu itb = Param.X86TLB(X86TLB(), "Instruction TLB") 1398863Snilay@cs.wisc.edu interrupts = Param.X86LocalApic(NULL, "Interrupt Controller") 1409384SAndreas.Sandberg@arm.com isa = VectorParam.X86ISA([ isa_class() ], "ISA instance") 1416654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'mips': 1426022Sgblack@eecs.umich.edu dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 1436022Sgblack@eecs.umich.edu itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") 1448745Sgblack@eecs.umich.edu interrupts = Param.MipsInterrupts( 1458863Snilay@cs.wisc.edu NULL, "Interrupt Controller") 1469384SAndreas.Sandberg@arm.com isa = VectorParam.MipsISA([ isa_class() ], "ISA instance") 1476654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'arm': 1486116Snate@binkert.org dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 1496116Snate@binkert.org itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") 1508745Sgblack@eecs.umich.edu interrupts = Param.ArmInterrupts( 1518863Snilay@cs.wisc.edu NULL, "Interrupt Controller") 1529384SAndreas.Sandberg@arm.com isa = VectorParam.ArmISA([ isa_class() ], "ISA instance") 1536691Stjones1@inf.ed.ac.uk elif buildEnv['TARGET_ISA'] == 'power': 1546691Stjones1@inf.ed.ac.uk UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 1556691Stjones1@inf.ed.ac.uk dtb = Param.PowerTLB(PowerTLB(), "Data TLB") 1566691Stjones1@inf.ed.ac.uk itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") 1578745Sgblack@eecs.umich.edu interrupts = Param.PowerInterrupts( 1588863Snilay@cs.wisc.edu NULL, "Interrupt Controller") 1599384SAndreas.Sandberg@arm.com isa = VectorParam.PowerISA([ isa_class() ], "ISA instance") 1604997Sgblack@eecs.umich.edu else: 1614997Sgblack@eecs.umich.edu print "Don't know what TLB to use for ISA %s" % \ 1626654Snate@binkert.org buildEnv['TARGET_ISA'] 1634997Sgblack@eecs.umich.edu sys.exit(1) 1644997Sgblack@eecs.umich.edu 1651310SN/A max_insts_all_threads = Param.Counter(0, 1661310SN/A "terminate when all threads have reached this inst count") 1671310SN/A max_insts_any_thread = Param.Counter(0, 1681310SN/A "terminate when any thread reaches this inst count") 1691310SN/A max_loads_all_threads = Param.Counter(0, 1701310SN/A "terminate when all threads have reached this load count") 1711310SN/A max_loads_any_thread = Param.Counter(0, 1721310SN/A "terminate when any thread reaches this load count") 1739180Sandreas.hansson@arm.com progress_interval = Param.Frequency('0Hz', 1749180Sandreas.hansson@arm.com "frequency to print out the progress message") 1751310SN/A 1761369SN/A defer_registration = Param.Bool(False, 1771310SN/A "defer registration with system (for sampling)") 1781634SN/A 1794776Sgblack@eecs.umich.edu tracer = Param.InstTracer(default_tracer, "Instruction tracer") 1804776Sgblack@eecs.umich.edu 1818839Sandreas.hansson@arm.com icache_port = MasterPort("Instruction Port") 1828839Sandreas.hansson@arm.com dcache_port = MasterPort("Data Port") 1838707Sandreas.hansson@arm.com _cached_ports = ['icache_port', 'dcache_port'] 1848707Sandreas.hansson@arm.com 1858756Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 1868707Sandreas.hansson@arm.com _cached_ports += ["itb.walker.port", "dtb.walker.port"] 1877876Sgblack@eecs.umich.edu 1888839Sandreas.hansson@arm.com _uncached_slave_ports = [] 1898839Sandreas.hansson@arm.com _uncached_master_ports = [] 1908745Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'x86': 1918839Sandreas.hansson@arm.com _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"] 1928839Sandreas.hansson@arm.com _uncached_master_ports += ["interrupts.int_master"] 1932998SN/A 1948863Snilay@cs.wisc.edu def createInterruptController(self): 1958863Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] == 'sparc': 1968863Snilay@cs.wisc.edu self.interrupts = SparcInterrupts() 1978863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'alpha': 1988863Snilay@cs.wisc.edu self.interrupts = AlphaInterrupts() 1998863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'x86': 2008863Snilay@cs.wisc.edu _localApic = X86LocalApic(pio_addr=0x2000000000000000) 2018863Snilay@cs.wisc.edu self.interrupts = _localApic 2028863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'mips': 2038863Snilay@cs.wisc.edu self.interrupts = MipsInterrupts() 2048863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'arm': 2058863Snilay@cs.wisc.edu self.interrupts = ArmInterrupts() 2068863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'power': 2078863Snilay@cs.wisc.edu self.interrupts = PowerInterrupts() 2088863Snilay@cs.wisc.edu else: 2098863Snilay@cs.wisc.edu print "Don't know what Interrupt Controller to use for ISA %s" % \ 2108863Snilay@cs.wisc.edu buildEnv['TARGET_ISA'] 2118863Snilay@cs.wisc.edu sys.exit(1) 2128863Snilay@cs.wisc.edu 2137876Sgblack@eecs.umich.edu def connectCachedPorts(self, bus): 2147876Sgblack@eecs.umich.edu for p in self._cached_ports: 2158839Sandreas.hansson@arm.com exec('self.%s = bus.slave' % p) 2167404SAli.Saidi@ARM.com 2177876Sgblack@eecs.umich.edu def connectUncachedPorts(self, bus): 2188839Sandreas.hansson@arm.com for p in self._uncached_slave_ports: 2198839Sandreas.hansson@arm.com exec('self.%s = bus.master' % p) 2208839Sandreas.hansson@arm.com for p in self._uncached_master_ports: 2218839Sandreas.hansson@arm.com exec('self.%s = bus.slave' % p) 2227876Sgblack@eecs.umich.edu 2237876Sgblack@eecs.umich.edu def connectAllPorts(self, cached_bus, uncached_bus = None): 2247876Sgblack@eecs.umich.edu self.connectCachedPorts(cached_bus) 2257876Sgblack@eecs.umich.edu if not uncached_bus: 2267876Sgblack@eecs.umich.edu uncached_bus = cached_bus 2277876Sgblack@eecs.umich.edu self.connectUncachedPorts(uncached_bus) 2282998SN/A 2297868Sgblack@eecs.umich.edu def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 2302998SN/A self.icache = ic 2312998SN/A self.dcache = dc 2322998SN/A self.icache_port = ic.cpu_side 2332998SN/A self.dcache_port = dc.cpu_side 2347876Sgblack@eecs.umich.edu self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 2358796Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 2368796Sgblack@eecs.umich.edu if iwc and dwc: 2378796Sgblack@eecs.umich.edu self.itb_walker_cache = iwc 2388796Sgblack@eecs.umich.edu self.dtb_walker_cache = dwc 2398796Sgblack@eecs.umich.edu self.itb.walker.port = iwc.cpu_side 2408796Sgblack@eecs.umich.edu self.dtb.walker.port = dwc.cpu_side 2418796Sgblack@eecs.umich.edu self._cached_ports += ["itb_walker_cache.mem_side", \ 2428796Sgblack@eecs.umich.edu "dtb_walker_cache.mem_side"] 2438796Sgblack@eecs.umich.edu else: 2448796Sgblack@eecs.umich.edu self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 2458887Sgeoffrey.blake@arm.com 2468809Sgblack@eecs.umich.edu # Checker doesn't need its own tlb caches because it does 2478809Sgblack@eecs.umich.edu # functional accesses only 2488887Sgeoffrey.blake@arm.com if self.checker != NULL: 2498809Sgblack@eecs.umich.edu self._cached_ports += ["checker.itb.walker.port", \ 2508809Sgblack@eecs.umich.edu "checker.dtb.walker.port"] 2512998SN/A 2527868Sgblack@eecs.umich.edu def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 2537868Sgblack@eecs.umich.edu self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 2549284Sandreas.hansson@arm.com # Override the default bus clock of 1 GHz and uses the CPU 2559284Sandreas.hansson@arm.com # clock for the L1-to-L2 bus, and also set a width of 32 bytes 2569284Sandreas.hansson@arm.com # (256-bits), which is four times that of the default bus. 2579284Sandreas.hansson@arm.com self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32) 2587876Sgblack@eecs.umich.edu self.connectCachedPorts(self.toL2Bus) 2592998SN/A self.l2cache = l2c 2608839Sandreas.hansson@arm.com self.toL2Bus.master = self.l2cache.cpu_side 2617876Sgblack@eecs.umich.edu self._cached_ports = ['l2cache.mem_side'] 2628887Sgeoffrey.blake@arm.com 2639384SAndreas.Sandberg@arm.com def createThreads(self): 2649384SAndreas.Sandberg@arm.com self.isa = [ isa_class() for i in xrange(self.numThreads) ] 2659384SAndreas.Sandberg@arm.com if self.checker != NULL: 2669384SAndreas.Sandberg@arm.com self.checker.createThreads() 2679384SAndreas.Sandberg@arm.com 2688887Sgeoffrey.blake@arm.com def addCheckerCpu(self): 2698887Sgeoffrey.blake@arm.com pass 270