BaseCPU.py revision 9284
18839Sandreas.hansson@arm.com# Copyright (c) 2012 ARM Limited 28839Sandreas.hansson@arm.com# All rights reserved. 38839Sandreas.hansson@arm.com# 48839Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 58839Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 68839Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 78839Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 88839Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 98839Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 108839Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 118839Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 128839Sandreas.hansson@arm.com# 135335Shines@cs.fsu.edu# Copyright (c) 2005-2008 The Regents of The University of Michigan 147897Shestness@cs.utexas.edu# Copyright (c) 2011 Regents of the University of California 154486Sbinkertn@umich.edu# All rights reserved. 164486Sbinkertn@umich.edu# 174486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 184486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 194486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 204486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 214486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 224486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 234486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 244486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 254486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 264486Sbinkertn@umich.edu# this software without specific prior written permission. 274486Sbinkertn@umich.edu# 284486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 324486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 364486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 384486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394486Sbinkertn@umich.edu# 404486Sbinkertn@umich.edu# Authors: Nathan Binkert 417897Shestness@cs.utexas.edu# Rick Strong 428839Sandreas.hansson@arm.com# Andreas Hansson 434486Sbinkertn@umich.edu 446654Snate@binkert.orgimport sys 456654Snate@binkert.org 466654Snate@binkert.orgfrom m5.defines import buildEnv 473102SN/Afrom m5.params import * 483102SN/Afrom m5.proxy import * 496654Snate@binkert.org 509036Sandreas.hansson@arm.comfrom Bus import CoherentBus 514776Sgblack@eecs.umich.edufrom InstTracer import InstTracer 524776Sgblack@eecs.umich.edufrom ExeTracer import ExeTracer 536654Snate@binkert.orgfrom MemObject import MemObject 542667SN/A 554776Sgblack@eecs.umich.edudefault_tracer = ExeTracer() 564776Sgblack@eecs.umich.edu 576654Snate@binkert.orgif buildEnv['TARGET_ISA'] == 'alpha': 586023Snate@binkert.org from AlphaTLB import AlphaDTB, AlphaITB 598745Sgblack@eecs.umich.edu from AlphaInterrupts import AlphaInterrupts 606654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'sparc': 616022Sgblack@eecs.umich.edu from SparcTLB import SparcTLB 628745Sgblack@eecs.umich.edu from SparcInterrupts import SparcInterrupts 636654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'x86': 646022Sgblack@eecs.umich.edu from X86TLB import X86TLB 658745Sgblack@eecs.umich.edu from X86LocalApic import X86LocalApic 666654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'mips': 676022Sgblack@eecs.umich.edu from MipsTLB import MipsTLB 688745Sgblack@eecs.umich.edu from MipsInterrupts import MipsInterrupts 696654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'arm': 706116Snate@binkert.org from ArmTLB import ArmTLB 718745Sgblack@eecs.umich.edu from ArmInterrupts import ArmInterrupts 726691Stjones1@inf.ed.ac.ukelif buildEnv['TARGET_ISA'] == 'power': 736691Stjones1@inf.ed.ac.uk from PowerTLB import PowerTLB 748745Sgblack@eecs.umich.edu from PowerInterrupts import PowerInterrupts 754486Sbinkertn@umich.edu 765529Snate@binkert.orgclass BaseCPU(MemObject): 771366SN/A type = 'BaseCPU' 781310SN/A abstract = True 791310SN/A 809254SAndreas.Sandberg@arm.com @classmethod 819254SAndreas.Sandberg@arm.com def export_method_cxx_predecls(cls, code): 829254SAndreas.Sandberg@arm.com code('#include "cpu/base.hh"') 839254SAndreas.Sandberg@arm.com 849254SAndreas.Sandberg@arm.com 859254SAndreas.Sandberg@arm.com @classmethod 869254SAndreas.Sandberg@arm.com def export_methods(cls, code): 879254SAndreas.Sandberg@arm.com code(''' 889254SAndreas.Sandberg@arm.com void switchOut(); 899254SAndreas.Sandberg@arm.com void takeOverFrom(BaseCPU *cpu); 909254SAndreas.Sandberg@arm.com''') 919254SAndreas.Sandberg@arm.com 929254SAndreas.Sandberg@arm.com def takeOverFrom(self, old_cpu): 939254SAndreas.Sandberg@arm.com self._ccObject.takeOverFrom(old_cpu._ccObject) 949254SAndreas.Sandberg@arm.com 959254SAndreas.Sandberg@arm.com 962901SN/A system = Param.System(Parent.any, "system object") 975712Shsul@eecs.umich.edu cpu_id = Param.Int(-1, "CPU identifier") 985529Snate@binkert.org numThreads = Param.Unsigned(1, "number of HW thread contexts") 995529Snate@binkert.org 1005529Snate@binkert.org function_trace = Param.Bool(False, "Enable function trace") 1019161Sandreas.hansson@arm.com function_trace_start = Param.Tick(0, "Tick to start function trace") 1025529Snate@binkert.org 1035821Ssaidi@eecs.umich.edu checker = Param.BaseCPU(NULL, "checker CPU") 1043170SN/A 1055780Ssteve.reinhardt@amd.com do_checkpoint_insts = Param.Bool(True, 1065780Ssteve.reinhardt@amd.com "enable checkpoint pseudo instructions") 1075780Ssteve.reinhardt@amd.com do_statistics_insts = Param.Bool(True, 1085780Ssteve.reinhardt@amd.com "enable statistics pseudo instructions") 1095780Ssteve.reinhardt@amd.com 1108784Sgblack@eecs.umich.edu profile = Param.Latency('0ns', "trace the kernel stack") 1118784Sgblack@eecs.umich.edu do_quiesce = Param.Bool(True, "enable quiesce instructions") 1128784Sgblack@eecs.umich.edu 1138793Sgblack@eecs.umich.edu workload = VectorParam.Process([], "processes to run") 1141310SN/A 1156654Snate@binkert.org if buildEnv['TARGET_ISA'] == 'sparc': 1166022Sgblack@eecs.umich.edu dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 1176022Sgblack@eecs.umich.edu itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") 1188745Sgblack@eecs.umich.edu interrupts = Param.SparcInterrupts( 1198863Snilay@cs.wisc.edu NULL, "Interrupt Controller") 1206654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'alpha': 1216023Snate@binkert.org dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 1226023Snate@binkert.org itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") 1238745Sgblack@eecs.umich.edu interrupts = Param.AlphaInterrupts( 1248863Snilay@cs.wisc.edu NULL, "Interrupt Controller") 1256654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'x86': 1266022Sgblack@eecs.umich.edu dtb = Param.X86TLB(X86TLB(), "Data TLB") 1276022Sgblack@eecs.umich.edu itb = Param.X86TLB(X86TLB(), "Instruction TLB") 1288863Snilay@cs.wisc.edu interrupts = Param.X86LocalApic(NULL, "Interrupt Controller") 1296654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'mips': 1306022Sgblack@eecs.umich.edu dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 1316022Sgblack@eecs.umich.edu itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") 1328745Sgblack@eecs.umich.edu interrupts = Param.MipsInterrupts( 1338863Snilay@cs.wisc.edu NULL, "Interrupt Controller") 1346654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'arm': 1356116Snate@binkert.org dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 1366116Snate@binkert.org itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") 1378745Sgblack@eecs.umich.edu interrupts = Param.ArmInterrupts( 1388863Snilay@cs.wisc.edu NULL, "Interrupt Controller") 1396691Stjones1@inf.ed.ac.uk elif buildEnv['TARGET_ISA'] == 'power': 1406691Stjones1@inf.ed.ac.uk UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 1416691Stjones1@inf.ed.ac.uk dtb = Param.PowerTLB(PowerTLB(), "Data TLB") 1426691Stjones1@inf.ed.ac.uk itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") 1438745Sgblack@eecs.umich.edu interrupts = Param.PowerInterrupts( 1448863Snilay@cs.wisc.edu NULL, "Interrupt Controller") 1454997Sgblack@eecs.umich.edu else: 1464997Sgblack@eecs.umich.edu print "Don't know what TLB to use for ISA %s" % \ 1476654Snate@binkert.org buildEnv['TARGET_ISA'] 1484997Sgblack@eecs.umich.edu sys.exit(1) 1494997Sgblack@eecs.umich.edu 1501310SN/A max_insts_all_threads = Param.Counter(0, 1511310SN/A "terminate when all threads have reached this inst count") 1521310SN/A max_insts_any_thread = Param.Counter(0, 1531310SN/A "terminate when any thread reaches this inst count") 1541310SN/A max_loads_all_threads = Param.Counter(0, 1551310SN/A "terminate when all threads have reached this load count") 1561310SN/A max_loads_any_thread = Param.Counter(0, 1571310SN/A "terminate when any thread reaches this load count") 1589180Sandreas.hansson@arm.com progress_interval = Param.Frequency('0Hz', 1599180Sandreas.hansson@arm.com "frequency to print out the progress message") 1601310SN/A 1611369SN/A defer_registration = Param.Bool(False, 1621310SN/A "defer registration with system (for sampling)") 1631634SN/A 1644776Sgblack@eecs.umich.edu tracer = Param.InstTracer(default_tracer, "Instruction tracer") 1654776Sgblack@eecs.umich.edu 1668839Sandreas.hansson@arm.com icache_port = MasterPort("Instruction Port") 1678839Sandreas.hansson@arm.com dcache_port = MasterPort("Data Port") 1688707Sandreas.hansson@arm.com _cached_ports = ['icache_port', 'dcache_port'] 1698707Sandreas.hansson@arm.com 1708756Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 1718707Sandreas.hansson@arm.com _cached_ports += ["itb.walker.port", "dtb.walker.port"] 1727876Sgblack@eecs.umich.edu 1738839Sandreas.hansson@arm.com _uncached_slave_ports = [] 1748839Sandreas.hansson@arm.com _uncached_master_ports = [] 1758745Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'x86': 1768839Sandreas.hansson@arm.com _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"] 1778839Sandreas.hansson@arm.com _uncached_master_ports += ["interrupts.int_master"] 1782998SN/A 1798863Snilay@cs.wisc.edu def createInterruptController(self): 1808863Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] == 'sparc': 1818863Snilay@cs.wisc.edu self.interrupts = SparcInterrupts() 1828863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'alpha': 1838863Snilay@cs.wisc.edu self.interrupts = AlphaInterrupts() 1848863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'x86': 1858863Snilay@cs.wisc.edu _localApic = X86LocalApic(pio_addr=0x2000000000000000) 1868863Snilay@cs.wisc.edu self.interrupts = _localApic 1878863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'mips': 1888863Snilay@cs.wisc.edu self.interrupts = MipsInterrupts() 1898863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'arm': 1908863Snilay@cs.wisc.edu self.interrupts = ArmInterrupts() 1918863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'power': 1928863Snilay@cs.wisc.edu self.interrupts = PowerInterrupts() 1938863Snilay@cs.wisc.edu else: 1948863Snilay@cs.wisc.edu print "Don't know what Interrupt Controller to use for ISA %s" % \ 1958863Snilay@cs.wisc.edu buildEnv['TARGET_ISA'] 1968863Snilay@cs.wisc.edu sys.exit(1) 1978863Snilay@cs.wisc.edu 1987876Sgblack@eecs.umich.edu def connectCachedPorts(self, bus): 1997876Sgblack@eecs.umich.edu for p in self._cached_ports: 2008839Sandreas.hansson@arm.com exec('self.%s = bus.slave' % p) 2017404SAli.Saidi@ARM.com 2027876Sgblack@eecs.umich.edu def connectUncachedPorts(self, bus): 2038839Sandreas.hansson@arm.com for p in self._uncached_slave_ports: 2048839Sandreas.hansson@arm.com exec('self.%s = bus.master' % p) 2058839Sandreas.hansson@arm.com for p in self._uncached_master_ports: 2068839Sandreas.hansson@arm.com exec('self.%s = bus.slave' % p) 2077876Sgblack@eecs.umich.edu 2087876Sgblack@eecs.umich.edu def connectAllPorts(self, cached_bus, uncached_bus = None): 2097876Sgblack@eecs.umich.edu self.connectCachedPorts(cached_bus) 2107876Sgblack@eecs.umich.edu if not uncached_bus: 2117876Sgblack@eecs.umich.edu uncached_bus = cached_bus 2127876Sgblack@eecs.umich.edu self.connectUncachedPorts(uncached_bus) 2132998SN/A 2147868Sgblack@eecs.umich.edu def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 2152998SN/A self.icache = ic 2162998SN/A self.dcache = dc 2172998SN/A self.icache_port = ic.cpu_side 2182998SN/A self.dcache_port = dc.cpu_side 2197876Sgblack@eecs.umich.edu self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 2208796Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 2218796Sgblack@eecs.umich.edu if iwc and dwc: 2228796Sgblack@eecs.umich.edu self.itb_walker_cache = iwc 2238796Sgblack@eecs.umich.edu self.dtb_walker_cache = dwc 2248796Sgblack@eecs.umich.edu self.itb.walker.port = iwc.cpu_side 2258796Sgblack@eecs.umich.edu self.dtb.walker.port = dwc.cpu_side 2268796Sgblack@eecs.umich.edu self._cached_ports += ["itb_walker_cache.mem_side", \ 2278796Sgblack@eecs.umich.edu "dtb_walker_cache.mem_side"] 2288796Sgblack@eecs.umich.edu else: 2298796Sgblack@eecs.umich.edu self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 2308887Sgeoffrey.blake@arm.com 2318809Sgblack@eecs.umich.edu # Checker doesn't need its own tlb caches because it does 2328809Sgblack@eecs.umich.edu # functional accesses only 2338887Sgeoffrey.blake@arm.com if self.checker != NULL: 2348809Sgblack@eecs.umich.edu self._cached_ports += ["checker.itb.walker.port", \ 2358809Sgblack@eecs.umich.edu "checker.dtb.walker.port"] 2362998SN/A 2377868Sgblack@eecs.umich.edu def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 2387868Sgblack@eecs.umich.edu self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 2399284Sandreas.hansson@arm.com # Override the default bus clock of 1 GHz and uses the CPU 2409284Sandreas.hansson@arm.com # clock for the L1-to-L2 bus, and also set a width of 32 bytes 2419284Sandreas.hansson@arm.com # (256-bits), which is four times that of the default bus. 2429284Sandreas.hansson@arm.com self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32) 2437876Sgblack@eecs.umich.edu self.connectCachedPorts(self.toL2Bus) 2442998SN/A self.l2cache = l2c 2458839Sandreas.hansson@arm.com self.toL2Bus.master = self.l2cache.cpu_side 2467876Sgblack@eecs.umich.edu self._cached_ports = ['l2cache.mem_side'] 2478887Sgeoffrey.blake@arm.com 2488887Sgeoffrey.blake@arm.com def addCheckerCpu(self): 2498887Sgeoffrey.blake@arm.com pass 250