BaseCPU.py revision 8809
12817Sksewell@umich.edu# Copyright (c) 2005-2008 The Regents of The University of Michigan 22817Sksewell@umich.edu# Copyright (c) 2011 Regents of the University of California 32817Sksewell@umich.edu# All rights reserved. 42817Sksewell@umich.edu# 52817Sksewell@umich.edu# Redistribution and use in source and binary forms, with or without 62817Sksewell@umich.edu# modification, are permitted provided that the following conditions are 72817Sksewell@umich.edu# met: redistributions of source code must retain the above copyright 82817Sksewell@umich.edu# notice, this list of conditions and the following disclaimer; 92817Sksewell@umich.edu# redistributions in binary form must reproduce the above copyright 102817Sksewell@umich.edu# notice, this list of conditions and the following disclaimer in the 112817Sksewell@umich.edu# documentation and/or other materials provided with the distribution; 122817Sksewell@umich.edu# neither the name of the copyright holders nor the names of its 132817Sksewell@umich.edu# contributors may be used to endorse or promote products derived from 142817Sksewell@umich.edu# this software without specific prior written permission. 152817Sksewell@umich.edu# 162817Sksewell@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172817Sksewell@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182817Sksewell@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192817Sksewell@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202817Sksewell@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212817Sksewell@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222817Sksewell@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232817Sksewell@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242817Sksewell@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252817Sksewell@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262817Sksewell@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272817Sksewell@umich.edu# 282817Sksewell@umich.edu# Authors: Nathan Binkert 294202Sbinkertn@umich.edu# Rick Strong 302817Sksewell@umich.edu 312817Sksewell@umich.eduimport sys 322817Sksewell@umich.edu 334202Sbinkertn@umich.edufrom m5.defines import buildEnv 342817Sksewell@umich.edufrom m5.params import * 354202Sbinkertn@umich.edufrom m5.proxy import * 364202Sbinkertn@umich.edu 374202Sbinkertn@umich.edufrom Bus import Bus 384202Sbinkertn@umich.edufrom InstTracer import InstTracer 394202Sbinkertn@umich.edufrom ExeTracer import ExeTracer 404202Sbinkertn@umich.edufrom MemObject import MemObject 414202Sbinkertn@umich.edu 424202Sbinkertn@umich.edudefault_tracer = ExeTracer() 434202Sbinkertn@umich.edu 444202Sbinkertn@umich.eduif buildEnv['TARGET_ISA'] == 'alpha': 454202Sbinkertn@umich.edu from AlphaTLB import AlphaDTB, AlphaITB 464202Sbinkertn@umich.edu from AlphaInterrupts import AlphaInterrupts 474202Sbinkertn@umich.eduelif buildEnv['TARGET_ISA'] == 'sparc': 484202Sbinkertn@umich.edu from SparcTLB import SparcTLB 494202Sbinkertn@umich.edu from SparcInterrupts import SparcInterrupts 504202Sbinkertn@umich.eduelif buildEnv['TARGET_ISA'] == 'x86': 514202Sbinkertn@umich.edu from X86TLB import X86TLB 524202Sbinkertn@umich.edu from X86LocalApic import X86LocalApic 534202Sbinkertn@umich.eduelif buildEnv['TARGET_ISA'] == 'mips': 542817Sksewell@umich.edu from MipsTLB import MipsTLB 554202Sbinkertn@umich.edu from MipsInterrupts import MipsInterrupts 564202Sbinkertn@umich.eduelif buildEnv['TARGET_ISA'] == 'arm': 574202Sbinkertn@umich.edu from ArmTLB import ArmTLB 584202Sbinkertn@umich.edu from ArmInterrupts import ArmInterrupts 594202Sbinkertn@umich.eduelif buildEnv['TARGET_ISA'] == 'power': 604202Sbinkertn@umich.edu from PowerTLB import PowerTLB 614202Sbinkertn@umich.edu from PowerInterrupts import PowerInterrupts 624202Sbinkertn@umich.edu 634202Sbinkertn@umich.educlass BaseCPU(MemObject): 644202Sbinkertn@umich.edu type = 'BaseCPU' 654202Sbinkertn@umich.edu abstract = True 664202Sbinkertn@umich.edu 674202Sbinkertn@umich.edu system = Param.System(Parent.any, "system object") 684202Sbinkertn@umich.edu cpu_id = Param.Int(-1, "CPU identifier") 694202Sbinkertn@umich.edu numThreads = Param.Unsigned(1, "number of HW thread contexts") 704202Sbinkertn@umich.edu 714202Sbinkertn@umich.edu function_trace = Param.Bool(False, "Enable function trace") 722817Sksewell@umich.edu function_trace_start = Param.Tick(0, "Cycle to start function trace") 734202Sbinkertn@umich.edu 744202Sbinkertn@umich.edu checker = Param.BaseCPU(NULL, "checker CPU") 752817Sksewell@umich.edu 764202Sbinkertn@umich.edu do_checkpoint_insts = Param.Bool(True, 774202Sbinkertn@umich.edu "enable checkpoint pseudo instructions") 784202Sbinkertn@umich.edu do_statistics_insts = Param.Bool(True, 794202Sbinkertn@umich.edu "enable statistics pseudo instructions") 804202Sbinkertn@umich.edu 812817Sksewell@umich.edu profile = Param.Latency('0ns', "trace the kernel stack") 82 do_quiesce = Param.Bool(True, "enable quiesce instructions") 83 84 workload = VectorParam.Process([], "processes to run") 85 86 if buildEnv['TARGET_ISA'] == 'sparc': 87 dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 88 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") 89 interrupts = Param.SparcInterrupts( 90 SparcInterrupts(), "Interrupt Controller") 91 elif buildEnv['TARGET_ISA'] == 'alpha': 92 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 93 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") 94 interrupts = Param.AlphaInterrupts( 95 AlphaInterrupts(), "Interrupt Controller") 96 elif buildEnv['TARGET_ISA'] == 'x86': 97 dtb = Param.X86TLB(X86TLB(), "Data TLB") 98 itb = Param.X86TLB(X86TLB(), "Instruction TLB") 99 _localApic = X86LocalApic(pio_addr=0x2000000000000000) 100 interrupts = Param.X86LocalApic(_localApic, "Interrupt Controller") 101 elif buildEnv['TARGET_ISA'] == 'mips': 102 dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 103 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") 104 interrupts = Param.MipsInterrupts( 105 MipsInterrupts(), "Interrupt Controller") 106 elif buildEnv['TARGET_ISA'] == 'arm': 107 dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 108 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") 109 interrupts = Param.ArmInterrupts( 110 ArmInterrupts(), "Interrupt Controller") 111 elif buildEnv['TARGET_ISA'] == 'power': 112 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 113 dtb = Param.PowerTLB(PowerTLB(), "Data TLB") 114 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") 115 interrupts = Param.PowerInterrupts( 116 PowerInterrupts(), "Interrupt Controller") 117 else: 118 print "Don't know what TLB to use for ISA %s" % \ 119 buildEnv['TARGET_ISA'] 120 sys.exit(1) 121 122 max_insts_all_threads = Param.Counter(0, 123 "terminate when all threads have reached this inst count") 124 max_insts_any_thread = Param.Counter(0, 125 "terminate when any thread reaches this inst count") 126 max_loads_all_threads = Param.Counter(0, 127 "terminate when all threads have reached this load count") 128 max_loads_any_thread = Param.Counter(0, 129 "terminate when any thread reaches this load count") 130 progress_interval = Param.Tick(0, 131 "interval to print out the progress message") 132 133 defer_registration = Param.Bool(False, 134 "defer registration with system (for sampling)") 135 136 clock = Param.Clock('1t', "clock speed") 137 phase = Param.Latency('0ns', "clock phase") 138 139 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 140 141 icache_port = Port("Instruction Port") 142 dcache_port = Port("Data Port") 143 _cached_ports = ['icache_port', 'dcache_port'] 144 145 if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 146 _cached_ports += ["itb.walker.port", "dtb.walker.port"] 147 148 _uncached_ports = [] 149 if buildEnv['TARGET_ISA'] == 'x86': 150 _uncached_ports = ["interrupts.pio", "interrupts.int_port"] 151 152 def connectCachedPorts(self, bus): 153 for p in self._cached_ports: 154 exec('self.%s = bus.port' % p) 155 156 def connectUncachedPorts(self, bus): 157 for p in self._uncached_ports: 158 exec('self.%s = bus.port' % p) 159 160 def connectAllPorts(self, cached_bus, uncached_bus = None): 161 self.connectCachedPorts(cached_bus) 162 if not uncached_bus: 163 uncached_bus = cached_bus 164 self.connectUncachedPorts(uncached_bus) 165 166 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 167 self.icache = ic 168 self.dcache = dc 169 self.icache_port = ic.cpu_side 170 self.dcache_port = dc.cpu_side 171 self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 172 if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 173 if iwc and dwc: 174 self.itb_walker_cache = iwc 175 self.dtb_walker_cache = dwc 176 self.itb.walker.port = iwc.cpu_side 177 self.dtb.walker.port = dwc.cpu_side 178 self._cached_ports += ["itb_walker_cache.mem_side", \ 179 "dtb_walker_cache.mem_side"] 180 else: 181 self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 182 # Checker doesn't need its own tlb caches because it does 183 # functional accesses only 184 if buildEnv['USE_CHECKER']: 185 self._cached_ports += ["checker.itb.walker.port", \ 186 "checker.dtb.walker.port"] 187 188 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 189 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 190 self.toL2Bus = Bus() 191 self.connectCachedPorts(self.toL2Bus) 192 self.l2cache = l2c 193 self.l2cache.cpu_side = self.toL2Bus.port 194 self._cached_ports = ['l2cache.mem_side'] 195