BaseCPU.py revision 8793
15627Sgblack@eecs.umich.edu# Copyright (c) 2005-2008 The Regents of The University of Michigan 25627Sgblack@eecs.umich.edu# Copyright (c) 2011 Regents of the University of California 35627Sgblack@eecs.umich.edu# All rights reserved. 45627Sgblack@eecs.umich.edu# 57087Snate@binkert.org# Redistribution and use in source and binary forms, with or without 67087Snate@binkert.org# modification, are permitted provided that the following conditions are 77087Snate@binkert.org# met: redistributions of source code must retain the above copyright 87087Snate@binkert.org# notice, this list of conditions and the following disclaimer; 97087Snate@binkert.org# redistributions in binary form must reproduce the above copyright 107087Snate@binkert.org# notice, this list of conditions and the following disclaimer in the 117087Snate@binkert.org# documentation and/or other materials provided with the distribution; 127087Snate@binkert.org# neither the name of the copyright holders nor the names of its 135627Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 147087Snate@binkert.org# this software without specific prior written permission. 157087Snate@binkert.org# 167087Snate@binkert.org# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177087Snate@binkert.org# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187087Snate@binkert.org# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197087Snate@binkert.org# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207087Snate@binkert.org# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217087Snate@binkert.org# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225627Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237087Snate@binkert.org# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245627Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255627Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265627Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275627Sgblack@eecs.umich.edu# 285627Sgblack@eecs.umich.edu# Authors: Nathan Binkert 295627Sgblack@eecs.umich.edu# Rick Strong 305627Sgblack@eecs.umich.edu 315627Sgblack@eecs.umich.eduimport sys 325627Sgblack@eecs.umich.edu 335627Sgblack@eecs.umich.edufrom m5.defines import buildEnv 345627Sgblack@eecs.umich.edufrom m5.params import * 355627Sgblack@eecs.umich.edufrom m5.proxy import * 365627Sgblack@eecs.umich.edu 375627Sgblack@eecs.umich.edufrom Bus import Bus 385627Sgblack@eecs.umich.edufrom InstTracer import InstTracer 395627Sgblack@eecs.umich.edufrom ExeTracer import ExeTracer 405627Sgblack@eecs.umich.edufrom MemObject import MemObject 415627Sgblack@eecs.umich.edu 425627Sgblack@eecs.umich.edudefault_tracer = ExeTracer() 435627Sgblack@eecs.umich.edu 445627Sgblack@eecs.umich.eduif buildEnv['TARGET_ISA'] == 'alpha': 455627Sgblack@eecs.umich.edu from AlphaTLB import AlphaDTB, AlphaITB 465627Sgblack@eecs.umich.edu from AlphaInterrupts import AlphaInterrupts 475627Sgblack@eecs.umich.eduelif buildEnv['TARGET_ISA'] == 'sparc': 485627Sgblack@eecs.umich.edu from SparcTLB import SparcTLB 495627Sgblack@eecs.umich.edu from SparcInterrupts import SparcInterrupts 505627Sgblack@eecs.umich.eduelif buildEnv['TARGET_ISA'] == 'x86': 515627Sgblack@eecs.umich.edu from X86TLB import X86TLB 525627Sgblack@eecs.umich.edu from X86LocalApic import X86LocalApic 535627Sgblack@eecs.umich.eduelif buildEnv['TARGET_ISA'] == 'mips': 545627Sgblack@eecs.umich.edu from MipsTLB import MipsTLB 555627Sgblack@eecs.umich.edu from MipsInterrupts import MipsInterrupts 565627Sgblack@eecs.umich.eduelif buildEnv['TARGET_ISA'] == 'arm': 575627Sgblack@eecs.umich.edu from ArmTLB import ArmTLB 585627Sgblack@eecs.umich.edu from ArmInterrupts import ArmInterrupts 595627Sgblack@eecs.umich.eduelif buildEnv['TARGET_ISA'] == 'power': 605627Sgblack@eecs.umich.edu from PowerTLB import PowerTLB 615627Sgblack@eecs.umich.edu from PowerInterrupts import PowerInterrupts 625627Sgblack@eecs.umich.edu 635627Sgblack@eecs.umich.educlass BaseCPU(MemObject): 645627Sgblack@eecs.umich.edu type = 'BaseCPU' 655627Sgblack@eecs.umich.edu abstract = True 665627Sgblack@eecs.umich.edu 675627Sgblack@eecs.umich.edu system = Param.System(Parent.any, "system object") 685627Sgblack@eecs.umich.edu cpu_id = Param.Int(-1, "CPU identifier") 695627Sgblack@eecs.umich.edu numThreads = Param.Unsigned(1, "number of HW thread contexts") 705627Sgblack@eecs.umich.edu 715627Sgblack@eecs.umich.edu function_trace = Param.Bool(False, "Enable function trace") 725627Sgblack@eecs.umich.edu function_trace_start = Param.Tick(0, "Cycle to start function trace") 735627Sgblack@eecs.umich.edu 745627Sgblack@eecs.umich.edu checker = Param.BaseCPU(NULL, "checker CPU") 755627Sgblack@eecs.umich.edu 765627Sgblack@eecs.umich.edu do_checkpoint_insts = Param.Bool(True, 775627Sgblack@eecs.umich.edu "enable checkpoint pseudo instructions") 785627Sgblack@eecs.umich.edu do_statistics_insts = Param.Bool(True, 795627Sgblack@eecs.umich.edu "enable statistics pseudo instructions") 805627Sgblack@eecs.umich.edu 815627Sgblack@eecs.umich.edu profile = Param.Latency('0ns', "trace the kernel stack") 825627Sgblack@eecs.umich.edu do_quiesce = Param.Bool(True, "enable quiesce instructions") 835627Sgblack@eecs.umich.edu 845627Sgblack@eecs.umich.edu workload = VectorParam.Process([], "processes to run") 855627Sgblack@eecs.umich.edu 865627Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'sparc': 875627Sgblack@eecs.umich.edu dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 885627Sgblack@eecs.umich.edu itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") 895627Sgblack@eecs.umich.edu interrupts = Param.SparcInterrupts( 905627Sgblack@eecs.umich.edu SparcInterrupts(), "Interrupt Controller") 915627Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'alpha': 92 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 93 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") 94 interrupts = Param.AlphaInterrupts( 95 AlphaInterrupts(), "Interrupt Controller") 96 elif buildEnv['TARGET_ISA'] == 'x86': 97 dtb = Param.X86TLB(X86TLB(), "Data TLB") 98 itb = Param.X86TLB(X86TLB(), "Instruction TLB") 99 _localApic = X86LocalApic(pio_addr=0x2000000000000000) 100 interrupts = Param.X86LocalApic(_localApic, "Interrupt Controller") 101 elif buildEnv['TARGET_ISA'] == 'mips': 102 dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 103 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") 104 interrupts = Param.MipsInterrupts( 105 MipsInterrupts(), "Interrupt Controller") 106 elif buildEnv['TARGET_ISA'] == 'arm': 107 dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 108 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") 109 interrupts = Param.ArmInterrupts( 110 ArmInterrupts(), "Interrupt Controller") 111 elif buildEnv['TARGET_ISA'] == 'power': 112 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 113 dtb = Param.PowerTLB(PowerTLB(), "Data TLB") 114 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") 115 interrupts = Param.PowerInterrupts( 116 PowerInterrupts(), "Interrupt Controller") 117 else: 118 print "Don't know what TLB to use for ISA %s" % \ 119 buildEnv['TARGET_ISA'] 120 sys.exit(1) 121 122 max_insts_all_threads = Param.Counter(0, 123 "terminate when all threads have reached this inst count") 124 max_insts_any_thread = Param.Counter(0, 125 "terminate when any thread reaches this inst count") 126 max_loads_all_threads = Param.Counter(0, 127 "terminate when all threads have reached this load count") 128 max_loads_any_thread = Param.Counter(0, 129 "terminate when any thread reaches this load count") 130 progress_interval = Param.Tick(0, 131 "interval to print out the progress message") 132 133 defer_registration = Param.Bool(False, 134 "defer registration with system (for sampling)") 135 136 clock = Param.Clock('1t', "clock speed") 137 phase = Param.Latency('0ns', "clock phase") 138 139 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 140 141 _cached_ports = [] 142 if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 143 _cached_ports = ["itb.walker.port", "dtb.walker.port"] 144 145 _uncached_ports = [] 146 if buildEnv['TARGET_ISA'] == 'x86': 147 _uncached_ports = ["interrupts.pio", "interrupts.int_port"] 148 149 def connectCachedPorts(self, bus): 150 for p in self._cached_ports: 151 exec('self.%s = bus.port' % p) 152 153 def connectUncachedPorts(self, bus): 154 for p in self._uncached_ports: 155 exec('self.%s = bus.port' % p) 156 157 def connectAllPorts(self, cached_bus, uncached_bus = None): 158 self.connectCachedPorts(cached_bus) 159 if not uncached_bus: 160 uncached_bus = cached_bus 161 self.connectUncachedPorts(uncached_bus) 162 163 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 164 assert(len(self._cached_ports) < 7) 165 self.icache = ic 166 self.dcache = dc 167 self.icache_port = ic.cpu_side 168 self.dcache_port = dc.cpu_side 169 self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 170 if buildEnv['TARGET_ISA'] == 'x86' and iwc and dwc: 171 self.itb_walker_cache = iwc 172 self.dtb_walker_cache = dwc 173 self.itb.walker.port = iwc.cpu_side 174 self.dtb.walker.port = dwc.cpu_side 175 self._cached_ports += ["itb_walker_cache.mem_side", \ 176 "dtb_walker_cache.mem_side"] 177 elif buildEnv['TARGET_ISA'] == 'arm': 178 self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 179 180 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 181 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 182 self.toL2Bus = Bus() 183 self.connectCachedPorts(self.toL2Bus) 184 self.l2cache = l2c 185 self.l2cache.cpu_side = self.toL2Bus.port 186 self._cached_ports = ['l2cache.mem_side'] 187