BaseCPU.py revision 8629
15335Shines@cs.fsu.edu# Copyright (c) 2005-2008 The Regents of The University of Michigan 27897Shestness@cs.utexas.edu# Copyright (c) 2011 Regents of the University of California 34486Sbinkertn@umich.edu# All rights reserved. 44486Sbinkertn@umich.edu# 54486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 64486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 74486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 84486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 94486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 104486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 114486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 124486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 134486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 144486Sbinkertn@umich.edu# this software without specific prior written permission. 154486Sbinkertn@umich.edu# 164486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274486Sbinkertn@umich.edu# 284486Sbinkertn@umich.edu# Authors: Nathan Binkert 297897Shestness@cs.utexas.edu# Rick Strong 304486Sbinkertn@umich.edu 316654Snate@binkert.orgimport sys 326654Snate@binkert.org 336654Snate@binkert.orgfrom m5.defines import buildEnv 343102SN/Afrom m5.params import * 353102SN/Afrom m5.proxy import * 366654Snate@binkert.org 372998SN/Afrom Bus import Bus 384776Sgblack@eecs.umich.edufrom InstTracer import InstTracer 394776Sgblack@eecs.umich.edufrom ExeTracer import ExeTracer 406654Snate@binkert.orgfrom MemObject import MemObject 412667SN/A 424776Sgblack@eecs.umich.edudefault_tracer = ExeTracer() 434776Sgblack@eecs.umich.edu 446654Snate@binkert.orgif buildEnv['TARGET_ISA'] == 'alpha': 456023Snate@binkert.org from AlphaTLB import AlphaDTB, AlphaITB 466654Snate@binkert.org if buildEnv['FULL_SYSTEM']: 475647Sgblack@eecs.umich.edu from AlphaInterrupts import AlphaInterrupts 486654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'sparc': 496022Sgblack@eecs.umich.edu from SparcTLB import SparcTLB 506654Snate@binkert.org if buildEnv['FULL_SYSTEM']: 515647Sgblack@eecs.umich.edu from SparcInterrupts import SparcInterrupts 526654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'x86': 536022Sgblack@eecs.umich.edu from X86TLB import X86TLB 546654Snate@binkert.org if buildEnv['FULL_SYSTEM']: 555647Sgblack@eecs.umich.edu from X86LocalApic import X86LocalApic 566654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'mips': 576022Sgblack@eecs.umich.edu from MipsTLB import MipsTLB 586654Snate@binkert.org if buildEnv['FULL_SYSTEM']: 595647Sgblack@eecs.umich.edu from MipsInterrupts import MipsInterrupts 606654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'arm': 616116Snate@binkert.org from ArmTLB import ArmTLB 626654Snate@binkert.org if buildEnv['FULL_SYSTEM']: 635647Sgblack@eecs.umich.edu from ArmInterrupts import ArmInterrupts 646691Stjones1@inf.ed.ac.ukelif buildEnv['TARGET_ISA'] == 'power': 656691Stjones1@inf.ed.ac.uk from PowerTLB import PowerTLB 666691Stjones1@inf.ed.ac.uk if buildEnv['FULL_SYSTEM']: 676691Stjones1@inf.ed.ac.uk from PowerInterrupts import PowerInterrupts 684486Sbinkertn@umich.edu 695529Snate@binkert.orgclass BaseCPU(MemObject): 701366SN/A type = 'BaseCPU' 711310SN/A abstract = True 721310SN/A 732901SN/A system = Param.System(Parent.any, "system object") 745712Shsul@eecs.umich.edu cpu_id = Param.Int(-1, "CPU identifier") 755529Snate@binkert.org numThreads = Param.Unsigned(1, "number of HW thread contexts") 765529Snate@binkert.org 775529Snate@binkert.org function_trace = Param.Bool(False, "Enable function trace") 785529Snate@binkert.org function_trace_start = Param.Tick(0, "Cycle to start function trace") 795529Snate@binkert.org 805821Ssaidi@eecs.umich.edu checker = Param.BaseCPU(NULL, "checker CPU") 813170SN/A 825780Ssteve.reinhardt@amd.com do_checkpoint_insts = Param.Bool(True, 835780Ssteve.reinhardt@amd.com "enable checkpoint pseudo instructions") 845780Ssteve.reinhardt@amd.com do_statistics_insts = Param.Bool(True, 855780Ssteve.reinhardt@amd.com "enable statistics pseudo instructions") 865780Ssteve.reinhardt@amd.com 876654Snate@binkert.org if buildEnv['FULL_SYSTEM']: 885529Snate@binkert.org profile = Param.Latency('0ns', "trace the kernel stack") 893620SN/A do_quiesce = Param.Bool(True, "enable quiesce instructions") 901445SN/A else: 911445SN/A workload = VectorParam.Process("processes to run") 921310SN/A 936654Snate@binkert.org if buildEnv['TARGET_ISA'] == 'sparc': 946022Sgblack@eecs.umich.edu dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 956022Sgblack@eecs.umich.edu itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") 966654Snate@binkert.org if buildEnv['FULL_SYSTEM']: 975647Sgblack@eecs.umich.edu interrupts = Param.SparcInterrupts( 985647Sgblack@eecs.umich.edu SparcInterrupts(), "Interrupt Controller") 996654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'alpha': 1006023Snate@binkert.org dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 1016023Snate@binkert.org itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") 1026654Snate@binkert.org if buildEnv['FULL_SYSTEM']: 1035647Sgblack@eecs.umich.edu interrupts = Param.AlphaInterrupts( 1045647Sgblack@eecs.umich.edu AlphaInterrupts(), "Interrupt Controller") 1056654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'x86': 1066022Sgblack@eecs.umich.edu dtb = Param.X86TLB(X86TLB(), "Data TLB") 1076022Sgblack@eecs.umich.edu itb = Param.X86TLB(X86TLB(), "Instruction TLB") 1086654Snate@binkert.org if buildEnv['FULL_SYSTEM']: 1095658Sgblack@eecs.umich.edu _localApic = X86LocalApic(pio_addr=0x2000000000000000) 1105648Sgblack@eecs.umich.edu interrupts = \ 1115648Sgblack@eecs.umich.edu Param.X86LocalApic(_localApic, "Interrupt Controller") 1126654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'mips': 1136022Sgblack@eecs.umich.edu dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 1146022Sgblack@eecs.umich.edu itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") 1156654Snate@binkert.org if buildEnv['FULL_SYSTEM']: 1165647Sgblack@eecs.umich.edu interrupts = Param.MipsInterrupts( 1175647Sgblack@eecs.umich.edu MipsInterrupts(), "Interrupt Controller") 1186654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'arm': 1196116Snate@binkert.org dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 1206116Snate@binkert.org itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") 1216654Snate@binkert.org if buildEnv['FULL_SYSTEM']: 1225647Sgblack@eecs.umich.edu interrupts = Param.ArmInterrupts( 1235647Sgblack@eecs.umich.edu ArmInterrupts(), "Interrupt Controller") 1246691Stjones1@inf.ed.ac.uk elif buildEnv['TARGET_ISA'] == 'power': 1256691Stjones1@inf.ed.ac.uk UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 1266691Stjones1@inf.ed.ac.uk dtb = Param.PowerTLB(PowerTLB(), "Data TLB") 1276691Stjones1@inf.ed.ac.uk itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") 1286691Stjones1@inf.ed.ac.uk if buildEnv['FULL_SYSTEM']: 1296691Stjones1@inf.ed.ac.uk interrupts = Param.PowerInterrupts( 1306691Stjones1@inf.ed.ac.uk PowerInterrupts(), "Interrupt Controller") 1314997Sgblack@eecs.umich.edu else: 1324997Sgblack@eecs.umich.edu print "Don't know what TLB to use for ISA %s" % \ 1336654Snate@binkert.org buildEnv['TARGET_ISA'] 1344997Sgblack@eecs.umich.edu sys.exit(1) 1354997Sgblack@eecs.umich.edu 1361310SN/A max_insts_all_threads = Param.Counter(0, 1371310SN/A "terminate when all threads have reached this inst count") 1381310SN/A max_insts_any_thread = Param.Counter(0, 1391310SN/A "terminate when any thread reaches this inst count") 1401310SN/A max_loads_all_threads = Param.Counter(0, 1411310SN/A "terminate when all threads have reached this load count") 1421310SN/A max_loads_any_thread = Param.Counter(0, 1431310SN/A "terminate when any thread reaches this load count") 1443878SN/A progress_interval = Param.Tick(0, 1453878SN/A "interval to print out the progress message") 1461310SN/A 1471369SN/A defer_registration = Param.Bool(False, 1481310SN/A "defer registration with system (for sampling)") 1491634SN/A 1504167SN/A clock = Param.Clock('1t', "clock speed") 1514167SN/A phase = Param.Latency('0ns', "clock phase") 1522998SN/A 1534776Sgblack@eecs.umich.edu tracer = Param.InstTracer(default_tracer, "Instruction tracer") 1544776Sgblack@eecs.umich.edu 1557876Sgblack@eecs.umich.edu _cached_ports = [] 1567876Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']: 1577876Sgblack@eecs.umich.edu _cached_ports = ["itb.walker.port", "dtb.walker.port"] 1587876Sgblack@eecs.umich.edu 1597876Sgblack@eecs.umich.edu _uncached_ports = [] 1606654Snate@binkert.org if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']: 1617876Sgblack@eecs.umich.edu _uncached_ports = ["interrupts.pio", "interrupts.int_port"] 1622998SN/A 1637876Sgblack@eecs.umich.edu def connectCachedPorts(self, bus): 1647876Sgblack@eecs.umich.edu for p in self._cached_ports: 1657876Sgblack@eecs.umich.edu exec('self.%s = bus.port' % p) 1667404SAli.Saidi@ARM.com 1677876Sgblack@eecs.umich.edu def connectUncachedPorts(self, bus): 1687876Sgblack@eecs.umich.edu for p in self._uncached_ports: 1697876Sgblack@eecs.umich.edu exec('self.%s = bus.port' % p) 1707876Sgblack@eecs.umich.edu 1717876Sgblack@eecs.umich.edu def connectAllPorts(self, cached_bus, uncached_bus = None): 1727876Sgblack@eecs.umich.edu self.connectCachedPorts(cached_bus) 1737876Sgblack@eecs.umich.edu if not uncached_bus: 1747876Sgblack@eecs.umich.edu uncached_bus = cached_bus 1757876Sgblack@eecs.umich.edu self.connectUncachedPorts(uncached_bus) 1762998SN/A 1777868Sgblack@eecs.umich.edu def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 1787876Sgblack@eecs.umich.edu assert(len(self._cached_ports) < 7) 1792998SN/A self.icache = ic 1802998SN/A self.dcache = dc 1812998SN/A self.icache_port = ic.cpu_side 1822998SN/A self.dcache_port = dc.cpu_side 1837876Sgblack@eecs.umich.edu self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 1847404SAli.Saidi@ARM.com if buildEnv['FULL_SYSTEM']: 1858629SAli.Saidi@ARM.com if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 1868629SAli.Saidi@ARM.com if iwc and dwc: 1878629SAli.Saidi@ARM.com self.itb_walker_cache = iwc 1888629SAli.Saidi@ARM.com self.dtb_walker_cache = dwc 1898629SAli.Saidi@ARM.com self.itb.walker.port = iwc.cpu_side 1908629SAli.Saidi@ARM.com self.dtb.walker.port = dwc.cpu_side 1918629SAli.Saidi@ARM.com self._cached_ports += ["itb_walker_cache.mem_side", \ 1928629SAli.Saidi@ARM.com "dtb_walker_cache.mem_side"] 1938629SAli.Saidi@ARM.com else: 1948629SAli.Saidi@ARM.com self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 1952998SN/A 1967868Sgblack@eecs.umich.edu def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 1977868Sgblack@eecs.umich.edu self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 1982998SN/A self.toL2Bus = Bus() 1997876Sgblack@eecs.umich.edu self.connectCachedPorts(self.toL2Bus) 2002998SN/A self.l2cache = l2c 2013017SN/A self.l2cache.cpu_side = self.toL2Bus.port 2027876Sgblack@eecs.umich.edu self._cached_ports = ['l2cache.mem_side'] 203