BaseCPU.py revision 7897
112276Sanouk.vanlaer@arm.com# Copyright (c) 2005-2008 The Regents of The University of Michigan 28839Sandreas.hansson@arm.com# Copyright (c) 2011 Regents of the University of California 38839Sandreas.hansson@arm.com# All rights reserved. 48839Sandreas.hansson@arm.com# 58839Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without 68839Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are 78839Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright 88839Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer; 98839Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright 108839Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the 118839Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution; 128839Sandreas.hansson@arm.com# neither the name of the copyright holders nor the names of its 135335Shines@cs.fsu.edu# contributors may be used to endorse or promote products derived from 147897Shestness@cs.utexas.edu# this software without specific prior written permission. 154486Sbinkertn@umich.edu# 164486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274486Sbinkertn@umich.edu# 284486Sbinkertn@umich.edu# Authors: Nathan Binkert 294486Sbinkertn@umich.edu# Rick Strong 304486Sbinkertn@umich.edu 314486Sbinkertn@umich.eduimport sys 324486Sbinkertn@umich.edu 334486Sbinkertn@umich.edufrom m5.defines import buildEnv 344486Sbinkertn@umich.edufrom m5.params import * 354486Sbinkertn@umich.edufrom m5.proxy import * 364486Sbinkertn@umich.edu 374486Sbinkertn@umich.edufrom Bus import Bus 384486Sbinkertn@umich.edufrom InstTracer import InstTracer 394486Sbinkertn@umich.edufrom ExeTracer import ExeTracer 404486Sbinkertn@umich.edufrom MemObject import MemObject 417897Shestness@cs.utexas.edu 428839Sandreas.hansson@arm.comdefault_tracer = ExeTracer() 434486Sbinkertn@umich.edu 446654Snate@binkert.orgif buildEnv['TARGET_ISA'] == 'alpha': 456654Snate@binkert.org from AlphaTLB import AlphaDTB, AlphaITB 4611988Sandreas.sandberg@arm.com if buildEnv['FULL_SYSTEM']: 476654Snate@binkert.org from AlphaInterrupts import AlphaInterrupts 483102SN/Aelif buildEnv['TARGET_ISA'] == 'sparc': 493102SN/A from SparcTLB import SparcTLB 506654Snate@binkert.org if buildEnv['FULL_SYSTEM']: 5110720Sandreas.hansson@arm.com from SparcInterrupts import SparcInterrupts 524776Sgblack@eecs.umich.eduelif buildEnv['TARGET_ISA'] == 'x86': 5310663SAli.Saidi@ARM.com from X86TLB import X86TLB 546654Snate@binkert.org if buildEnv['FULL_SYSTEM']: 559793Sakash.bagdia@arm.com from X86LocalApic import X86LocalApic 562667SN/Aelif buildEnv['TARGET_ISA'] == 'mips': 574776Sgblack@eecs.umich.edu from MipsTLB import MipsTLB 584776Sgblack@eecs.umich.edu if buildEnv['FULL_SYSTEM']: 596654Snate@binkert.org from MipsInterrupts import MipsInterrupts 6012434Sgabeblack@google.comelif buildEnv['TARGET_ISA'] == 'arm': 618745Sgblack@eecs.umich.edu from ArmTLB import ArmTLB 629384SAndreas.Sandberg@arm.com if buildEnv['FULL_SYSTEM']: 6312325Sandreas.sandberg@arm.com from ArmInterrupts import ArmInterrupts 646654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'power': 6512434Sgabeblack@google.com from PowerTLB import PowerTLB 668745Sgblack@eecs.umich.edu if buildEnv['FULL_SYSTEM']: 679384SAndreas.Sandberg@arm.com from PowerInterrupts import PowerInterrupts 6812325Sandreas.sandberg@arm.com 696654Snate@binkert.orgclass BaseCPU(MemObject): 7012434Sgabeblack@google.com type = 'BaseCPU' 718745Sgblack@eecs.umich.edu abstract = True 729384SAndreas.Sandberg@arm.com 7312325Sandreas.sandberg@arm.com system = Param.System(Parent.any, "system object") 746654Snate@binkert.org cpu_id = Param.Int(-1, "CPU identifier") 7512434Sgabeblack@google.com numThreads = Param.Unsigned(1, "number of HW thread contexts") 768745Sgblack@eecs.umich.edu 779384SAndreas.Sandberg@arm.com function_trace = Param.Bool(False, "Enable function trace") 7812325Sandreas.sandberg@arm.com function_trace_start = Param.Tick(0, "Cycle to start function trace") 796654Snate@binkert.org 8012434Sgabeblack@google.com checker = Param.BaseCPU(NULL, "checker CPU") 8112434Sgabeblack@google.com 828745Sgblack@eecs.umich.edu do_checkpoint_insts = Param.Bool(True, 839384SAndreas.Sandberg@arm.com "enable checkpoint pseudo instructions") 8412325Sandreas.sandberg@arm.com do_statistics_insts = Param.Bool(True, 856691Stjones1@inf.ed.ac.uk "enable statistics pseudo instructions") 8612434Sgabeblack@google.com 878745Sgblack@eecs.umich.edu if buildEnv['FULL_SYSTEM']: 889384SAndreas.Sandberg@arm.com profile = Param.Latency('0ns', "trace the kernel stack") 8912325Sandreas.sandberg@arm.com do_quiesce = Param.Bool(True, "enable quiesce instructions") 9011723Sar4jc@virginia.edu else: 9112434Sgabeblack@google.com workload = VectorParam.Process("processes to run") 9211723Sar4jc@virginia.edu 9311723Sar4jc@virginia.edu if buildEnv['TARGET_ISA'] == 'sparc': 9412325Sandreas.sandberg@arm.com dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 954486Sbinkertn@umich.edu itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") 965529Snate@binkert.org if buildEnv['FULL_SYSTEM']: 971366SN/A interrupts = Param.SparcInterrupts( 981310SN/A SparcInterrupts(), "Interrupt Controller") 999338SAndreas.Sandberg@arm.com elif buildEnv['TARGET_ISA'] == 'alpha': 1009254SAndreas.Sandberg@arm.com dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 10111988Sandreas.sandberg@arm.com itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") 10211988Sandreas.sandberg@arm.com if buildEnv['FULL_SYSTEM']: 10311988Sandreas.sandberg@arm.com interrupts = Param.AlphaInterrupts( 10411988Sandreas.sandberg@arm.com AlphaInterrupts(), "Interrupt Controller") 10511988Sandreas.sandberg@arm.com elif buildEnv['TARGET_ISA'] == 'x86': 10611988Sandreas.sandberg@arm.com dtb = Param.X86TLB(X86TLB(), "Data TLB") 10711988Sandreas.sandberg@arm.com itb = Param.X86TLB(X86TLB(), "Instruction TLB") 10811988Sandreas.sandberg@arm.com if buildEnv['FULL_SYSTEM']: 10911988Sandreas.sandberg@arm.com _localApic = X86LocalApic(pio_addr=0x2000000000000000) 11011988Sandreas.sandberg@arm.com interrupts = \ 1119254SAndreas.Sandberg@arm.com Param.X86LocalApic(_localApic, "Interrupt Controller") 1129518SAndreas.Sandberg@ARM.com elif buildEnv['TARGET_ISA'] == 'mips': 1139518SAndreas.Sandberg@ARM.com dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 1149518SAndreas.Sandberg@ARM.com itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") 1159518SAndreas.Sandberg@ARM.com if buildEnv['FULL_SYSTEM']: 1169518SAndreas.Sandberg@ARM.com interrupts = Param.MipsInterrupts( 1179518SAndreas.Sandberg@ARM.com MipsInterrupts(), "Interrupt Controller") 1189518SAndreas.Sandberg@ARM.com elif buildEnv['TARGET_ISA'] == 'arm': 1199518SAndreas.Sandberg@ARM.com dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 1209518SAndreas.Sandberg@ARM.com itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") 1219518SAndreas.Sandberg@ARM.com if buildEnv['FULL_SYSTEM']: 1229518SAndreas.Sandberg@ARM.com interrupts = Param.ArmInterrupts( 1239518SAndreas.Sandberg@ARM.com ArmInterrupts(), "Interrupt Controller") 1249518SAndreas.Sandberg@ARM.com elif buildEnv['TARGET_ISA'] == 'power': 1259518SAndreas.Sandberg@ARM.com UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 1269518SAndreas.Sandberg@ARM.com dtb = Param.PowerTLB(PowerTLB(), "Data TLB") 1279518SAndreas.Sandberg@ARM.com itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") 1289518SAndreas.Sandberg@ARM.com if buildEnv['FULL_SYSTEM']: 1299518SAndreas.Sandberg@ARM.com interrupts = Param.PowerInterrupts( 1309518SAndreas.Sandberg@ARM.com PowerInterrupts(), "Interrupt Controller") 1319254SAndreas.Sandberg@arm.com else: 1329254SAndreas.Sandberg@arm.com print "Don't know what TLB to use for ISA %s" % \ 1339254SAndreas.Sandberg@arm.com buildEnv['TARGET_ISA'] 1349254SAndreas.Sandberg@arm.com sys.exit(1) 1352901SN/A 1365712Shsul@eecs.umich.edu max_insts_all_threads = Param.Counter(0, 13710190Sakash.bagdia@arm.com "terminate when all threads have reached this inst count") 1385529Snate@binkert.org max_insts_any_thread = Param.Counter(0, 13912276Sanouk.vanlaer@arm.com "terminate when any thread reaches this inst count") 14012276Sanouk.vanlaer@arm.com max_loads_all_threads = Param.Counter(0, 1415529Snate@binkert.org "terminate when all threads have reached this load count") 14212277Sjose.marinho@arm.com max_loads_any_thread = Param.Counter(0, 14312277Sjose.marinho@arm.com "terminate when any thread reaches this load count") 14412277Sjose.marinho@arm.com progress_interval = Param.Tick(0, 14512277Sjose.marinho@arm.com "interval to print out the progress message") 1465529Snate@binkert.org 1479161Sandreas.hansson@arm.com defer_registration = Param.Bool(False, 1485529Snate@binkert.org "defer registration with system (for sampling)") 1495821Ssaidi@eecs.umich.edu 1503170SN/A clock = Param.Clock('1t', "clock speed") 15111877Sbrandon.potter@amd.com phase = Param.Latency('0ns', "clock phase") 15211877Sbrandon.potter@amd.com 1535780Ssteve.reinhardt@amd.com tracer = Param.InstTracer(default_tracer, "Instruction tracer") 1545780Ssteve.reinhardt@amd.com 1555780Ssteve.reinhardt@amd.com _cached_ports = [] 1565780Ssteve.reinhardt@amd.com if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']: 1575780Ssteve.reinhardt@amd.com _cached_ports = ["itb.walker.port", "dtb.walker.port"] 1588784Sgblack@eecs.umich.edu 1598784Sgblack@eecs.umich.edu _uncached_ports = [] 1608784Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']: 16112122Sjose.marinho@arm.com _uncached_ports = ["interrupts.pio", "interrupts.int_port"] 16212122Sjose.marinho@arm.com 16312122Sjose.marinho@arm.com def connectCachedPorts(self, bus): 1648793Sgblack@eecs.umich.edu for p in self._cached_ports: 1651310SN/A exec('self.%s = bus.port' % p) 16612434Sgabeblack@google.com 16712434Sgabeblack@google.com def connectUncachedPorts(self, bus): 1686654Snate@binkert.org for p in self._uncached_ports: 16911150Smitch.hayenga@arm.com exec('self.%s = bus.port' % p) 17011150Smitch.hayenga@arm.com 17112325Sandreas.sandberg@arm.com def connectAllPorts(self, cached_bus, uncached_bus = None): 1726654Snate@binkert.org self.connectCachedPorts(cached_bus) 17311150Smitch.hayenga@arm.com if not uncached_bus: 17411150Smitch.hayenga@arm.com uncached_bus = cached_bus 17512325Sandreas.sandberg@arm.com self.connectUncachedPorts(uncached_bus) 1766654Snate@binkert.org 17711150Smitch.hayenga@arm.com def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 17812325Sandreas.sandberg@arm.com assert(len(self._cached_ports) < 7) 1796654Snate@binkert.org self.icache = ic 18011150Smitch.hayenga@arm.com self.dcache = dc 18111150Smitch.hayenga@arm.com self.icache_port = ic.cpu_side 18212325Sandreas.sandberg@arm.com self.dcache_port = dc.cpu_side 1836654Snate@binkert.org self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 18410037SARM gem5 Developers if buildEnv['FULL_SYSTEM']: 18510037SARM gem5 Developers if buildEnv['TARGET_ISA'] == 'x86': 18611150Smitch.hayenga@arm.com self.itb_walker_cache = iwc 18711150Smitch.hayenga@arm.com self.dtb_walker_cache = dwc 18812325Sandreas.sandberg@arm.com self.itb.walker.port = iwc.cpu_side 1896691Stjones1@inf.ed.ac.uk self.dtb.walker.port = dwc.cpu_side 1906691Stjones1@inf.ed.ac.uk self._cached_ports += ["itb_walker_cache.mem_side", \ 19111150Smitch.hayenga@arm.com "dtb_walker_cache.mem_side"] 19211150Smitch.hayenga@arm.com elif buildEnv['TARGET_ISA'] == 'arm': 19312325Sandreas.sandberg@arm.com self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 19411723Sar4jc@virginia.edu 19511723Sar4jc@virginia.edu def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 19611723Sar4jc@virginia.edu self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 19712325Sandreas.sandberg@arm.com self.toL2Bus = Bus() 1984997Sgblack@eecs.umich.edu self.connectCachedPorts(self.toL2Bus) 1994997Sgblack@eecs.umich.edu self.l2cache = l2c 2006654Snate@binkert.org self.l2cache.cpu_side = self.toL2Bus.port 2014997Sgblack@eecs.umich.edu self._cached_ports = ['l2cache.mem_side'] 2024997Sgblack@eecs.umich.edu 2031310SN/A if buildEnv['TARGET_ISA'] == 'mips': 2041310SN/A CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description") 2051310SN/A CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description") 2061310SN/A CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description") 2079647Sdam.sunwoo@arm.com CP0_EBase_CPUNum = Param.Unsigned(0,"No Description") 2089647Sdam.sunwoo@arm.com CP0_PRId_CompanyOptions = Param.Unsigned(0,"Company Options in Processor ID Register") 2091310SN/A CP0_PRId_CompanyID = Param.Unsigned(0,"Company Identifier in Processor ID Register") 2101310SN/A CP0_PRId_ProcessorID = Param.Unsigned(1,"Processor ID (0=>Not MIPS32/64 Processor, 1=>MIPS, 2-255 => Other Company") 2111310SN/A CP0_PRId_Revision = Param.Unsigned(0,"Processor Revision Number in Processor ID Register") 2121310SN/A CP0_Config_BE = Param.Unsigned(0,"Big Endian?") 2139180Sandreas.hansson@arm.com CP0_Config_AT = Param.Unsigned(0,"No Description") 2149180Sandreas.hansson@arm.com CP0_Config_AR = Param.Unsigned(0,"No Description") 2151310SN/A CP0_Config_MT = Param.Unsigned(0,"No Description") 2169433SAndreas.Sandberg@ARM.com CP0_Config_VI = Param.Unsigned(0,"No Description") 2179433SAndreas.Sandberg@ARM.com CP0_Config1_M = Param.Unsigned(0,"Config2 Implemented?") 2189433SAndreas.Sandberg@ARM.com CP0_Config1_MMU = Param.Unsigned(0,"MMU Type") 2191634SN/A CP0_Config1_IS = Param.Unsigned(0,"No Description") 2204776Sgblack@eecs.umich.edu CP0_Config1_IL = Param.Unsigned(0,"No Description") 2214776Sgblack@eecs.umich.edu CP0_Config1_IA = Param.Unsigned(0,"No Description") 2228839Sandreas.hansson@arm.com CP0_Config1_DS = Param.Unsigned(0,"No Description") 2238839Sandreas.hansson@arm.com CP0_Config1_DL = Param.Unsigned(0,"No Description") 2248707Sandreas.hansson@arm.com CP0_Config1_DA = Param.Unsigned(0,"No Description") 2258707Sandreas.hansson@arm.com CP0_Config1_C2 = Param.Bool(False,"No Description") 2268756Sgblack@eecs.umich.edu CP0_Config1_MD = Param.Bool(False,"No Description") 2278707Sandreas.hansson@arm.com CP0_Config1_PC = Param.Bool(False,"No Description") 2287876Sgblack@eecs.umich.edu CP0_Config1_WR = Param.Bool(False,"No Description") 2298839Sandreas.hansson@arm.com CP0_Config1_CA = Param.Bool(False,"No Description") 2308839Sandreas.hansson@arm.com CP0_Config1_EP = Param.Bool(False,"No Description") 2318745Sgblack@eecs.umich.edu CP0_Config1_FP = Param.Bool(False,"FPU Implemented?") 23211150Smitch.hayenga@arm.com CP0_Config2_M = Param.Bool(False,"Config3 Implemented?") 23311150Smitch.hayenga@arm.com CP0_Config2_TU = Param.Unsigned(0,"No Description") 23411150Smitch.hayenga@arm.com CP0_Config2_TS = Param.Unsigned(0,"No Description") 2352998SN/A CP0_Config2_TL = Param.Unsigned(0,"No Description") 2368863Snilay@cs.wisc.edu CP0_Config2_TA = Param.Unsigned(0,"No Description") 2378863Snilay@cs.wisc.edu CP0_Config2_SU = Param.Unsigned(0,"No Description") 23811150Smitch.hayenga@arm.com CP0_Config2_SS = Param.Unsigned(0,"No Description") 2398863Snilay@cs.wisc.edu CP0_Config2_SL = Param.Unsigned(0,"No Description") 24011150Smitch.hayenga@arm.com CP0_Config2_SA = Param.Unsigned(0,"No Description") 2418863Snilay@cs.wisc.edu CP0_Config3_M = Param.Bool(False,"Config4 Implemented?") 2429793Sakash.bagdia@arm.com CP0_Config3_DSPP = Param.Bool(False,"DSP Extensions Present?") 2439793Sakash.bagdia@arm.com CP0_Config3_LPA = Param.Bool(False,"No Description") 2449793Sakash.bagdia@arm.com CP0_Config3_VEIC = Param.Bool(False,"No Description") 24511150Smitch.hayenga@arm.com CP0_Config3_VInt = Param.Bool(False,"No Description") 2469544Sandreas.hansson@arm.com CP0_Config3_SP = Param.Bool(False,"No Description") 24711150Smitch.hayenga@arm.com CP0_Config3_MT = Param.Bool(False,"Multithreading Extensions Present?") 2489544Sandreas.hansson@arm.com CP0_Config3_SM = Param.Bool(False,"No Description") 2498863Snilay@cs.wisc.edu CP0_Config3_TL = Param.Bool(False,"No Description") 25011150Smitch.hayenga@arm.com CP0_WatchHi_M = Param.Bool(False,"No Description") 2518863Snilay@cs.wisc.edu CP0_PerfCtr_M = Param.Bool(False,"No Description") 25211150Smitch.hayenga@arm.com CP0_PerfCtr_W = Param.Bool(False,"No Description") 2538863Snilay@cs.wisc.edu CP0_PRId = Param.Unsigned(0,"CP0 Status Register") 25411150Smitch.hayenga@arm.com CP0_Config = Param.Unsigned(0,"CP0 Config Register") 25511723Sar4jc@virginia.edu CP0_Config1 = Param.Unsigned(0,"CP0 Config1 Register") 25611723Sar4jc@virginia.edu CP0_Config2 = Param.Unsigned(0,"CP0 Config2 Register") 25711723Sar4jc@virginia.edu CP0_Config3 = Param.Unsigned(0,"CP0 Config3 Register") 2588863Snilay@cs.wisc.edu