BaseCPU.py revision 6654
15627Sgblack@eecs.umich.edu# Copyright (c) 2005-2008 The Regents of The University of Michigan 25627Sgblack@eecs.umich.edu# All rights reserved. 35627Sgblack@eecs.umich.edu# 45627Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 57087Snate@binkert.org# modification, are permitted provided that the following conditions are 67087Snate@binkert.org# met: redistributions of source code must retain the above copyright 77087Snate@binkert.org# notice, this list of conditions and the following disclaimer; 87087Snate@binkert.org# redistributions in binary form must reproduce the above copyright 97087Snate@binkert.org# notice, this list of conditions and the following disclaimer in the 107087Snate@binkert.org# documentation and/or other materials provided with the distribution; 117087Snate@binkert.org# neither the name of the copyright holders nor the names of its 127087Snate@binkert.org# contributors may be used to endorse or promote products derived from 135627Sgblack@eecs.umich.edu# this software without specific prior written permission. 147087Snate@binkert.org# 157087Snate@binkert.org# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 167087Snate@binkert.org# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 177087Snate@binkert.org# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 187087Snate@binkert.org# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 197087Snate@binkert.org# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 207087Snate@binkert.org# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 217087Snate@binkert.org# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 225627Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 237087Snate@binkert.org# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 245627Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 255627Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 265627Sgblack@eecs.umich.edu# 275627Sgblack@eecs.umich.edu# Authors: Nathan Binkert 285627Sgblack@eecs.umich.edu 295627Sgblack@eecs.umich.eduimport sys 305627Sgblack@eecs.umich.edu 315627Sgblack@eecs.umich.edufrom m5.defines import buildEnv 325627Sgblack@eecs.umich.edufrom m5.params import * 335627Sgblack@eecs.umich.edufrom m5.proxy import * 345627Sgblack@eecs.umich.edu 355627Sgblack@eecs.umich.edufrom Bus import Bus 365627Sgblack@eecs.umich.edufrom InstTracer import InstTracer 375627Sgblack@eecs.umich.edufrom ExeTracer import ExeTracer 385627Sgblack@eecs.umich.edufrom MemObject import MemObject 395627Sgblack@eecs.umich.edu 405627Sgblack@eecs.umich.edudefault_tracer = ExeTracer() 415627Sgblack@eecs.umich.edu 428229Snate@binkert.orgif buildEnv['TARGET_ISA'] == 'alpha': 438229Snate@binkert.org from AlphaTLB import AlphaDTB, AlphaITB 448229Snate@binkert.org if buildEnv['FULL_SYSTEM']: 458229Snate@binkert.org from AlphaInterrupts import AlphaInterrupts 465627Sgblack@eecs.umich.eduelif buildEnv['TARGET_ISA'] == 'sparc': 475627Sgblack@eecs.umich.edu from SparcTLB import SparcTLB 485627Sgblack@eecs.umich.edu if buildEnv['FULL_SYSTEM']: 495627Sgblack@eecs.umich.edu from SparcInterrupts import SparcInterrupts 505627Sgblack@eecs.umich.eduelif buildEnv['TARGET_ISA'] == 'x86': 515627Sgblack@eecs.umich.edu from X86TLB import X86TLB 525627Sgblack@eecs.umich.edu if buildEnv['FULL_SYSTEM']: 535627Sgblack@eecs.umich.edu from X86LocalApic import X86LocalApic 545627Sgblack@eecs.umich.eduelif buildEnv['TARGET_ISA'] == 'mips': 555627Sgblack@eecs.umich.edu from MipsTLB import MipsTLB 565627Sgblack@eecs.umich.edu if buildEnv['FULL_SYSTEM']: 575627Sgblack@eecs.umich.edu from MipsInterrupts import MipsInterrupts 585627Sgblack@eecs.umich.eduelif buildEnv['TARGET_ISA'] == 'arm': 595627Sgblack@eecs.umich.edu from ArmTLB import ArmTLB 605627Sgblack@eecs.umich.edu if buildEnv['FULL_SYSTEM']: 615627Sgblack@eecs.umich.edu from ArmInterrupts import ArmInterrupts 625627Sgblack@eecs.umich.edu 635627Sgblack@eecs.umich.educlass BaseCPU(MemObject): 645627Sgblack@eecs.umich.edu type = 'BaseCPU' 655627Sgblack@eecs.umich.edu abstract = True 665627Sgblack@eecs.umich.edu 675627Sgblack@eecs.umich.edu system = Param.System(Parent.any, "system object") 685627Sgblack@eecs.umich.edu cpu_id = Param.Int(-1, "CPU identifier") 695627Sgblack@eecs.umich.edu numThreads = Param.Unsigned(1, "number of HW thread contexts") 705627Sgblack@eecs.umich.edu 715627Sgblack@eecs.umich.edu function_trace = Param.Bool(False, "Enable function trace") 725627Sgblack@eecs.umich.edu function_trace_start = Param.Tick(0, "Cycle to start function trace") 735627Sgblack@eecs.umich.edu 745627Sgblack@eecs.umich.edu checker = Param.BaseCPU(NULL, "checker CPU") 755627Sgblack@eecs.umich.edu 765627Sgblack@eecs.umich.edu do_checkpoint_insts = Param.Bool(True, 775627Sgblack@eecs.umich.edu "enable checkpoint pseudo instructions") 785627Sgblack@eecs.umich.edu do_statistics_insts = Param.Bool(True, 795627Sgblack@eecs.umich.edu "enable statistics pseudo instructions") 805627Sgblack@eecs.umich.edu 815627Sgblack@eecs.umich.edu if buildEnv['FULL_SYSTEM']: 825627Sgblack@eecs.umich.edu profile = Param.Latency('0ns', "trace the kernel stack") 835627Sgblack@eecs.umich.edu do_quiesce = Param.Bool(True, "enable quiesce instructions") 845627Sgblack@eecs.umich.edu else: 855627Sgblack@eecs.umich.edu workload = VectorParam.Process("processes to run") 865627Sgblack@eecs.umich.edu 875627Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'sparc': 885627Sgblack@eecs.umich.edu dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 895627Sgblack@eecs.umich.edu itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") 90 if buildEnv['FULL_SYSTEM']: 91 interrupts = Param.SparcInterrupts( 92 SparcInterrupts(), "Interrupt Controller") 93 elif buildEnv['TARGET_ISA'] == 'alpha': 94 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 95 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") 96 if buildEnv['FULL_SYSTEM']: 97 interrupts = Param.AlphaInterrupts( 98 AlphaInterrupts(), "Interrupt Controller") 99 elif buildEnv['TARGET_ISA'] == 'x86': 100 dtb = Param.X86TLB(X86TLB(), "Data TLB") 101 itb = Param.X86TLB(X86TLB(), "Instruction TLB") 102 if buildEnv['FULL_SYSTEM']: 103 _localApic = X86LocalApic(pio_addr=0x2000000000000000) 104 interrupts = \ 105 Param.X86LocalApic(_localApic, "Interrupt Controller") 106 elif buildEnv['TARGET_ISA'] == 'mips': 107 dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 108 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") 109 if buildEnv['FULL_SYSTEM']: 110 interrupts = Param.MipsInterrupts( 111 MipsInterrupts(), "Interrupt Controller") 112 elif buildEnv['TARGET_ISA'] == 'arm': 113 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 114 dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 115 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") 116 if buildEnv['FULL_SYSTEM']: 117 interrupts = Param.ArmInterrupts( 118 ArmInterrupts(), "Interrupt Controller") 119 else: 120 print "Don't know what TLB to use for ISA %s" % \ 121 buildEnv['TARGET_ISA'] 122 sys.exit(1) 123 124 max_insts_all_threads = Param.Counter(0, 125 "terminate when all threads have reached this inst count") 126 max_insts_any_thread = Param.Counter(0, 127 "terminate when any thread reaches this inst count") 128 max_loads_all_threads = Param.Counter(0, 129 "terminate when all threads have reached this load count") 130 max_loads_any_thread = Param.Counter(0, 131 "terminate when any thread reaches this load count") 132 progress_interval = Param.Tick(0, 133 "interval to print out the progress message") 134 135 defer_registration = Param.Bool(False, 136 "defer registration with system (for sampling)") 137 138 clock = Param.Clock('1t', "clock speed") 139 phase = Param.Latency('0ns', "clock phase") 140 141 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 142 143 _mem_ports = [] 144 if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']: 145 _mem_ports = ["itb.walker.port", 146 "dtb.walker.port", 147 "interrupts.pio", 148 "interrupts.int_port"] 149 150 def connectMemPorts(self, bus): 151 for p in self._mem_ports: 152 if p != 'physmem_port': 153 exec('self.%s = bus.port' % p) 154 155 def addPrivateSplitL1Caches(self, ic, dc): 156 assert(len(self._mem_ports) < 6) 157 self.icache = ic 158 self.dcache = dc 159 self.icache_port = ic.cpu_side 160 self.dcache_port = dc.cpu_side 161 self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] 162 if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']: 163 self._mem_ports += ["itb.walker_port", "dtb.walker_port"] 164 165 def addTwoLevelCacheHierarchy(self, ic, dc, l2c): 166 self.addPrivateSplitL1Caches(ic, dc) 167 self.toL2Bus = Bus() 168 self.connectMemPorts(self.toL2Bus) 169 self.l2cache = l2c 170 self.l2cache.cpu_side = self.toL2Bus.port 171 self._mem_ports = ['l2cache.mem_side'] 172 173 if buildEnv['TARGET_ISA'] == 'mips': 174 CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description") 175 CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description") 176 CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description") 177 CP0_EBase_CPUNum = Param.Unsigned(0,"No Description") 178 CP0_PRId_CompanyOptions = Param.Unsigned(0,"Company Options in Processor ID Register") 179 CP0_PRId_CompanyID = Param.Unsigned(0,"Company Identifier in Processor ID Register") 180 CP0_PRId_ProcessorID = Param.Unsigned(1,"Processor ID (0=>Not MIPS32/64 Processor, 1=>MIPS, 2-255 => Other Company") 181 CP0_PRId_Revision = Param.Unsigned(0,"Processor Revision Number in Processor ID Register") 182 CP0_Config_BE = Param.Unsigned(0,"Big Endian?") 183 CP0_Config_AT = Param.Unsigned(0,"No Description") 184 CP0_Config_AR = Param.Unsigned(0,"No Description") 185 CP0_Config_MT = Param.Unsigned(0,"No Description") 186 CP0_Config_VI = Param.Unsigned(0,"No Description") 187 CP0_Config1_M = Param.Unsigned(0,"Config2 Implemented?") 188 CP0_Config1_MMU = Param.Unsigned(0,"MMU Type") 189 CP0_Config1_IS = Param.Unsigned(0,"No Description") 190 CP0_Config1_IL = Param.Unsigned(0,"No Description") 191 CP0_Config1_IA = Param.Unsigned(0,"No Description") 192 CP0_Config1_DS = Param.Unsigned(0,"No Description") 193 CP0_Config1_DL = Param.Unsigned(0,"No Description") 194 CP0_Config1_DA = Param.Unsigned(0,"No Description") 195 CP0_Config1_C2 = Param.Bool(False,"No Description") 196 CP0_Config1_MD = Param.Bool(False,"No Description") 197 CP0_Config1_PC = Param.Bool(False,"No Description") 198 CP0_Config1_WR = Param.Bool(False,"No Description") 199 CP0_Config1_CA = Param.Bool(False,"No Description") 200 CP0_Config1_EP = Param.Bool(False,"No Description") 201 CP0_Config1_FP = Param.Bool(False,"FPU Implemented?") 202 CP0_Config2_M = Param.Bool(False,"Config3 Implemented?") 203 CP0_Config2_TU = Param.Unsigned(0,"No Description") 204 CP0_Config2_TS = Param.Unsigned(0,"No Description") 205 CP0_Config2_TL = Param.Unsigned(0,"No Description") 206 CP0_Config2_TA = Param.Unsigned(0,"No Description") 207 CP0_Config2_SU = Param.Unsigned(0,"No Description") 208 CP0_Config2_SS = Param.Unsigned(0,"No Description") 209 CP0_Config2_SL = Param.Unsigned(0,"No Description") 210 CP0_Config2_SA = Param.Unsigned(0,"No Description") 211 CP0_Config3_M = Param.Bool(False,"Config4 Implemented?") 212 CP0_Config3_DSPP = Param.Bool(False,"DSP Extensions Present?") 213 CP0_Config3_LPA = Param.Bool(False,"No Description") 214 CP0_Config3_VEIC = Param.Bool(False,"No Description") 215 CP0_Config3_VInt = Param.Bool(False,"No Description") 216 CP0_Config3_SP = Param.Bool(False,"No Description") 217 CP0_Config3_MT = Param.Bool(False,"Multithreading Extensions Present?") 218 CP0_Config3_SM = Param.Bool(False,"No Description") 219 CP0_Config3_TL = Param.Bool(False,"No Description") 220 CP0_WatchHi_M = Param.Bool(False,"No Description") 221 CP0_PerfCtr_M = Param.Bool(False,"No Description") 222 CP0_PerfCtr_W = Param.Bool(False,"No Description") 223 CP0_PRId = Param.Unsigned(0,"CP0 Status Register") 224 CP0_Config = Param.Unsigned(0,"CP0 Config Register") 225 CP0_Config1 = Param.Unsigned(0,"CP0 Config1 Register") 226 CP0_Config2 = Param.Unsigned(0,"CP0 Config2 Register") 227 CP0_Config3 = Param.Unsigned(0,"CP0 Config3 Register") 228