BaseCPU.py revision 6023
15335Shines@cs.fsu.edu# Copyright (c) 2005-2008 The Regents of The University of Michigan 24486Sbinkertn@umich.edu# All rights reserved. 34486Sbinkertn@umich.edu# 44486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 54486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 64486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 74486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 84486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 94486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 104486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 114486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 124486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 134486Sbinkertn@umich.edu# this software without specific prior written permission. 144486Sbinkertn@umich.edu# 154486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 164486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 174486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 184486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 194486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 204486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 214486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 224486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 234486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 244486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 254486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 264486Sbinkertn@umich.edu# 274486Sbinkertn@umich.edu# Authors: Nathan Binkert 284486Sbinkertn@umich.edu 295529Snate@binkert.orgfrom MemObject import MemObject 303102SN/Afrom m5.params import * 313102SN/Afrom m5.proxy import * 322667SN/Afrom m5 import build_env 332998SN/Afrom Bus import Bus 344776Sgblack@eecs.umich.edufrom InstTracer import InstTracer 354776Sgblack@eecs.umich.edufrom ExeTracer import ExeTracer 363584SN/Aimport sys 372667SN/A 384776Sgblack@eecs.umich.edudefault_tracer = ExeTracer() 394776Sgblack@eecs.umich.edu 404997Sgblack@eecs.umich.eduif build_env['TARGET_ISA'] == 'alpha': 416023Snate@binkert.org from AlphaTLB import AlphaDTB, AlphaITB 425647Sgblack@eecs.umich.edu if build_env['FULL_SYSTEM']: 435647Sgblack@eecs.umich.edu from AlphaInterrupts import AlphaInterrupts 444997Sgblack@eecs.umich.eduelif build_env['TARGET_ISA'] == 'sparc': 456022Sgblack@eecs.umich.edu from SparcTLB import SparcTLB 465647Sgblack@eecs.umich.edu if build_env['FULL_SYSTEM']: 475647Sgblack@eecs.umich.edu from SparcInterrupts import SparcInterrupts 484997Sgblack@eecs.umich.eduelif build_env['TARGET_ISA'] == 'x86': 496022Sgblack@eecs.umich.edu from X86TLB import X86TLB 505647Sgblack@eecs.umich.edu if build_env['FULL_SYSTEM']: 515647Sgblack@eecs.umich.edu from X86LocalApic import X86LocalApic 524997Sgblack@eecs.umich.eduelif build_env['TARGET_ISA'] == 'mips': 536022Sgblack@eecs.umich.edu from MipsTLB import MipsTLB 545647Sgblack@eecs.umich.edu if build_env['FULL_SYSTEM']: 555647Sgblack@eecs.umich.edu from MipsInterrupts import MipsInterrupts 565335Shines@cs.fsu.eduelif build_env['TARGET_ISA'] == 'arm': 576023Snate@binkert.org from ArmTLB import ArmDTB 585647Sgblack@eecs.umich.edu if build_env['FULL_SYSTEM']: 595647Sgblack@eecs.umich.edu from ArmInterrupts import ArmInterrupts 604486Sbinkertn@umich.edu 615529Snate@binkert.orgclass BaseCPU(MemObject): 621366SN/A type = 'BaseCPU' 631310SN/A abstract = True 641310SN/A 652901SN/A system = Param.System(Parent.any, "system object") 665712Shsul@eecs.umich.edu cpu_id = Param.Int(-1, "CPU identifier") 675529Snate@binkert.org numThreads = Param.Unsigned(1, "number of HW thread contexts") 685529Snate@binkert.org 695529Snate@binkert.org function_trace = Param.Bool(False, "Enable function trace") 705529Snate@binkert.org function_trace_start = Param.Tick(0, "Cycle to start function trace") 715529Snate@binkert.org 725821Ssaidi@eecs.umich.edu checker = Param.BaseCPU(NULL, "checker CPU") 733170SN/A 745780Ssteve.reinhardt@amd.com do_checkpoint_insts = Param.Bool(True, 755780Ssteve.reinhardt@amd.com "enable checkpoint pseudo instructions") 765780Ssteve.reinhardt@amd.com do_statistics_insts = Param.Bool(True, 775780Ssteve.reinhardt@amd.com "enable statistics pseudo instructions") 785780Ssteve.reinhardt@amd.com 791530SN/A if build_env['FULL_SYSTEM']: 805529Snate@binkert.org profile = Param.Latency('0ns', "trace the kernel stack") 813620SN/A do_quiesce = Param.Bool(True, "enable quiesce instructions") 821445SN/A else: 831445SN/A workload = VectorParam.Process("processes to run") 841310SN/A 854997Sgblack@eecs.umich.edu if build_env['TARGET_ISA'] == 'sparc': 866022Sgblack@eecs.umich.edu dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 876022Sgblack@eecs.umich.edu itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") 885647Sgblack@eecs.umich.edu if build_env['FULL_SYSTEM']: 895647Sgblack@eecs.umich.edu interrupts = Param.SparcInterrupts( 905647Sgblack@eecs.umich.edu SparcInterrupts(), "Interrupt Controller") 914997Sgblack@eecs.umich.edu elif build_env['TARGET_ISA'] == 'alpha': 926023Snate@binkert.org dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 936023Snate@binkert.org itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") 945647Sgblack@eecs.umich.edu if build_env['FULL_SYSTEM']: 955647Sgblack@eecs.umich.edu interrupts = Param.AlphaInterrupts( 965647Sgblack@eecs.umich.edu AlphaInterrupts(), "Interrupt Controller") 974997Sgblack@eecs.umich.edu elif build_env['TARGET_ISA'] == 'x86': 986022Sgblack@eecs.umich.edu dtb = Param.X86TLB(X86TLB(), "Data TLB") 996022Sgblack@eecs.umich.edu itb = Param.X86TLB(X86TLB(), "Instruction TLB") 1005647Sgblack@eecs.umich.edu if build_env['FULL_SYSTEM']: 1015658Sgblack@eecs.umich.edu _localApic = X86LocalApic(pio_addr=0x2000000000000000) 1025648Sgblack@eecs.umich.edu interrupts = \ 1035648Sgblack@eecs.umich.edu Param.X86LocalApic(_localApic, "Interrupt Controller") 1044997Sgblack@eecs.umich.edu elif build_env['TARGET_ISA'] == 'mips': 1056022Sgblack@eecs.umich.edu dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 1066022Sgblack@eecs.umich.edu itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") 1075647Sgblack@eecs.umich.edu if build_env['FULL_SYSTEM']: 1085647Sgblack@eecs.umich.edu interrupts = Param.MipsInterrupts( 1095647Sgblack@eecs.umich.edu MipsInterrupts(), "Interrupt Controller") 1105335Shines@cs.fsu.edu elif build_env['TARGET_ISA'] == 'arm': 1115335Shines@cs.fsu.edu UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 1126023Snate@binkert.org dtb = Param.ArmTLB(ArmDTB(), "Data TLB") 1136023Snate@binkert.org itb = Param.ArmTLB(ArmITB(), "Instruction TLB") 1145647Sgblack@eecs.umich.edu if build_env['FULL_SYSTEM']: 1155647Sgblack@eecs.umich.edu interrupts = Param.ArmInterrupts( 1165647Sgblack@eecs.umich.edu ArmInterrupts(), "Interrupt Controller") 1174997Sgblack@eecs.umich.edu else: 1184997Sgblack@eecs.umich.edu print "Don't know what TLB to use for ISA %s" % \ 1194997Sgblack@eecs.umich.edu build_env['TARGET_ISA'] 1204997Sgblack@eecs.umich.edu sys.exit(1) 1214997Sgblack@eecs.umich.edu 1221310SN/A max_insts_all_threads = Param.Counter(0, 1231310SN/A "terminate when all threads have reached this inst count") 1241310SN/A max_insts_any_thread = Param.Counter(0, 1251310SN/A "terminate when any thread reaches this inst count") 1261310SN/A max_loads_all_threads = Param.Counter(0, 1271310SN/A "terminate when all threads have reached this load count") 1281310SN/A max_loads_any_thread = Param.Counter(0, 1291310SN/A "terminate when any thread reaches this load count") 1303878SN/A progress_interval = Param.Tick(0, 1313878SN/A "interval to print out the progress message") 1321310SN/A 1331369SN/A defer_registration = Param.Bool(False, 1341310SN/A "defer registration with system (for sampling)") 1351634SN/A 1364167SN/A clock = Param.Clock('1t', "clock speed") 1374167SN/A phase = Param.Latency('0ns', "clock phase") 1382998SN/A 1394776Sgblack@eecs.umich.edu tracer = Param.InstTracer(default_tracer, "Instruction tracer") 1404776Sgblack@eecs.umich.edu 1412998SN/A _mem_ports = [] 1425281Sgblack@eecs.umich.edu if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: 1435648Sgblack@eecs.umich.edu _mem_ports = ["itb.walker.port", 1445648Sgblack@eecs.umich.edu "dtb.walker.port", 1455651Sgblack@eecs.umich.edu "interrupts.pio", 1465651Sgblack@eecs.umich.edu "interrupts.int_port"] 1472998SN/A 1482998SN/A def connectMemPorts(self, bus): 1492998SN/A for p in self._mem_ports: 1504968Sacolyte@umich.edu if p != 'physmem_port': 1514968Sacolyte@umich.edu exec('self.%s = bus.port' % p) 1522998SN/A 1532998SN/A def addPrivateSplitL1Caches(self, ic, dc): 1545281Sgblack@eecs.umich.edu assert(len(self._mem_ports) < 6) 1552998SN/A self.icache = ic 1562998SN/A self.dcache = dc 1572998SN/A self.icache_port = ic.cpu_side 1582998SN/A self.dcache_port = dc.cpu_side 1592998SN/A self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] 1605281Sgblack@eecs.umich.edu if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: 1615281Sgblack@eecs.umich.edu self._mem_ports += ["itb.walker_port", "dtb.walker_port"] 1622998SN/A 1632998SN/A def addTwoLevelCacheHierarchy(self, ic, dc, l2c): 1642998SN/A self.addPrivateSplitL1Caches(ic, dc) 1652998SN/A self.toL2Bus = Bus() 1662998SN/A self.connectMemPorts(self.toL2Bus) 1672998SN/A self.l2cache = l2c 1683017SN/A self.l2cache.cpu_side = self.toL2Bus.port 1692998SN/A self._mem_ports = ['l2cache.mem_side'] 1705222Sksewell@umich.edu 1715222Sksewell@umich.edu if build_env['TARGET_ISA'] == 'mips': 1725222Sksewell@umich.edu CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description") 1735222Sksewell@umich.edu CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description") 1745222Sksewell@umich.edu CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description") 1755222Sksewell@umich.edu CP0_EBase_CPUNum = Param.Unsigned(0,"No Description") 1765222Sksewell@umich.edu CP0_PRId_CompanyOptions = Param.Unsigned(0,"Company Options in Processor ID Register") 1775222Sksewell@umich.edu CP0_PRId_CompanyID = Param.Unsigned(0,"Company Identifier in Processor ID Register") 1785222Sksewell@umich.edu CP0_PRId_ProcessorID = Param.Unsigned(1,"Processor ID (0=>Not MIPS32/64 Processor, 1=>MIPS, 2-255 => Other Company") 1795222Sksewell@umich.edu CP0_PRId_Revision = Param.Unsigned(0,"Processor Revision Number in Processor ID Register") 1805222Sksewell@umich.edu CP0_Config_BE = Param.Unsigned(0,"Big Endian?") 1815222Sksewell@umich.edu CP0_Config_AT = Param.Unsigned(0,"No Description") 1825222Sksewell@umich.edu CP0_Config_AR = Param.Unsigned(0,"No Description") 1835222Sksewell@umich.edu CP0_Config_MT = Param.Unsigned(0,"No Description") 1845222Sksewell@umich.edu CP0_Config_VI = Param.Unsigned(0,"No Description") 1855222Sksewell@umich.edu CP0_Config1_M = Param.Unsigned(0,"Config2 Implemented?") 1865222Sksewell@umich.edu CP0_Config1_MMU = Param.Unsigned(0,"MMU Type") 1875222Sksewell@umich.edu CP0_Config1_IS = Param.Unsigned(0,"No Description") 1885222Sksewell@umich.edu CP0_Config1_IL = Param.Unsigned(0,"No Description") 1895222Sksewell@umich.edu CP0_Config1_IA = Param.Unsigned(0,"No Description") 1905222Sksewell@umich.edu CP0_Config1_DS = Param.Unsigned(0,"No Description") 1915222Sksewell@umich.edu CP0_Config1_DL = Param.Unsigned(0,"No Description") 1925222Sksewell@umich.edu CP0_Config1_DA = Param.Unsigned(0,"No Description") 1935222Sksewell@umich.edu CP0_Config1_C2 = Param.Bool(False,"No Description") 1945222Sksewell@umich.edu CP0_Config1_MD = Param.Bool(False,"No Description") 1955222Sksewell@umich.edu CP0_Config1_PC = Param.Bool(False,"No Description") 1965222Sksewell@umich.edu CP0_Config1_WR = Param.Bool(False,"No Description") 1975222Sksewell@umich.edu CP0_Config1_CA = Param.Bool(False,"No Description") 1985222Sksewell@umich.edu CP0_Config1_EP = Param.Bool(False,"No Description") 1995222Sksewell@umich.edu CP0_Config1_FP = Param.Bool(False,"FPU Implemented?") 2005222Sksewell@umich.edu CP0_Config2_M = Param.Bool(False,"Config3 Implemented?") 2015222Sksewell@umich.edu CP0_Config2_TU = Param.Unsigned(0,"No Description") 2025222Sksewell@umich.edu CP0_Config2_TS = Param.Unsigned(0,"No Description") 2035222Sksewell@umich.edu CP0_Config2_TL = Param.Unsigned(0,"No Description") 2045222Sksewell@umich.edu CP0_Config2_TA = Param.Unsigned(0,"No Description") 2055222Sksewell@umich.edu CP0_Config2_SU = Param.Unsigned(0,"No Description") 2065222Sksewell@umich.edu CP0_Config2_SS = Param.Unsigned(0,"No Description") 2075222Sksewell@umich.edu CP0_Config2_SL = Param.Unsigned(0,"No Description") 2085222Sksewell@umich.edu CP0_Config2_SA = Param.Unsigned(0,"No Description") 2095222Sksewell@umich.edu CP0_Config3_M = Param.Bool(False,"Config4 Implemented?") 2105222Sksewell@umich.edu CP0_Config3_DSPP = Param.Bool(False,"DSP Extensions Present?") 2115222Sksewell@umich.edu CP0_Config3_LPA = Param.Bool(False,"No Description") 2125222Sksewell@umich.edu CP0_Config3_VEIC = Param.Bool(False,"No Description") 2135222Sksewell@umich.edu CP0_Config3_VInt = Param.Bool(False,"No Description") 2145222Sksewell@umich.edu CP0_Config3_SP = Param.Bool(False,"No Description") 2155222Sksewell@umich.edu CP0_Config3_MT = Param.Bool(False,"Multithreading Extensions Present?") 2165222Sksewell@umich.edu CP0_Config3_SM = Param.Bool(False,"No Description") 2175222Sksewell@umich.edu CP0_Config3_TL = Param.Bool(False,"No Description") 2185222Sksewell@umich.edu CP0_WatchHi_M = Param.Bool(False,"No Description") 2195222Sksewell@umich.edu CP0_PerfCtr_M = Param.Bool(False,"No Description") 2205222Sksewell@umich.edu CP0_PerfCtr_W = Param.Bool(False,"No Description") 2215222Sksewell@umich.edu CP0_PRId = Param.Unsigned(0,"CP0 Status Register") 2225222Sksewell@umich.edu CP0_Config = Param.Unsigned(0,"CP0 Config Register") 2235222Sksewell@umich.edu CP0_Config1 = Param.Unsigned(0,"CP0 Config1 Register") 2245222Sksewell@umich.edu CP0_Config2 = Param.Unsigned(0,"CP0 Config2 Register") 2255222Sksewell@umich.edu CP0_Config3 = Param.Unsigned(0,"CP0 Config3 Register") 226