BaseCPU.py revision 4997
14486Sbinkertn@umich.edu# Copyright (c) 2005-2007 The Regents of The University of Michigan 24486Sbinkertn@umich.edu# All rights reserved. 34486Sbinkertn@umich.edu# 44486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 54486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 64486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 74486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 84486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 94486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 104486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 114486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 124486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 134486Sbinkertn@umich.edu# this software without specific prior written permission. 144486Sbinkertn@umich.edu# 154486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 164486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 174486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 184486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 194486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 204486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 214486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 224486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 234486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 244486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 254486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 264486Sbinkertn@umich.edu# 274486Sbinkertn@umich.edu# Authors: Nathan Binkert 284486Sbinkertn@umich.edu 293102SN/Afrom m5.SimObject import SimObject 303102SN/Afrom m5.params import * 313102SN/Afrom m5.proxy import * 322667SN/Afrom m5 import build_env 332998SN/Afrom Bus import Bus 344776Sgblack@eecs.umich.edufrom InstTracer import InstTracer 354776Sgblack@eecs.umich.edufrom ExeTracer import ExeTracer 363584SN/Aimport sys 372667SN/A 384776Sgblack@eecs.umich.edudefault_tracer = ExeTracer() 394776Sgblack@eecs.umich.edu 404997Sgblack@eecs.umich.eduif build_env['TARGET_ISA'] == 'alpha': 414997Sgblack@eecs.umich.edu from AlphaTLB import AlphaDTB, AlphaITB 424997Sgblack@eecs.umich.eduelif build_env['TARGET_ISA'] == 'sparc': 434997Sgblack@eecs.umich.edu from SparcTLB import SparcDTB, SparcITB 444997Sgblack@eecs.umich.eduelif build_env['TARGET_ISA'] == 'x86': 454997Sgblack@eecs.umich.edu from X86TLB import X86DTB, X86ITB 464997Sgblack@eecs.umich.eduelif build_env['TARGET_ISA'] == 'mips': 474997Sgblack@eecs.umich.edu from MipsTLB import MipsDTB, MipsITB 484486Sbinkertn@umich.edu 491692SN/Aclass BaseCPU(SimObject): 501366SN/A type = 'BaseCPU' 511310SN/A abstract = True 521310SN/A 532901SN/A system = Param.System(Parent.any, "system object") 543170SN/A cpu_id = Param.Int("CPU identifier") 553170SN/A 561530SN/A if build_env['FULL_SYSTEM']: 573620SN/A do_quiesce = Param.Bool(True, "enable quiesce instructions") 583617SN/A do_checkpoint_insts = Param.Bool(True, 593617SN/A "enable checkpoint pseudo instructions") 603617SN/A do_statistics_insts = Param.Bool(True, 613617SN/A "enable statistics pseudo instructions") 621445SN/A else: 631445SN/A workload = VectorParam.Process("processes to run") 641310SN/A 654997Sgblack@eecs.umich.edu if build_env['TARGET_ISA'] == 'sparc': 664997Sgblack@eecs.umich.edu dtb = Param.SparcDTB(SparcDTB(), "Data TLB") 674997Sgblack@eecs.umich.edu itb = Param.SparcITB(SparcITB(), "Instruction TLB") 684997Sgblack@eecs.umich.edu elif build_env['TARGET_ISA'] == 'alpha': 694997Sgblack@eecs.umich.edu dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB") 704997Sgblack@eecs.umich.edu itb = Param.AlphaITB(AlphaITB(), "Instruction TLB") 714997Sgblack@eecs.umich.edu elif build_env['TARGET_ISA'] == 'x86': 724997Sgblack@eecs.umich.edu dtb = Param.X86DTB(X86DTB(), "Data TLB") 734997Sgblack@eecs.umich.edu itb = Param.X86ITB(X86ITB(), "Instruction TLB") 744997Sgblack@eecs.umich.edu elif build_env['TARGET_ISA'] == 'mips': 754997Sgblack@eecs.umich.edu dtb = Param.MipsDTB(MipsDTB(), "Data TLB") 764997Sgblack@eecs.umich.edu itb = Param.MipsITB(MipsITB(), "Instruction TLB") 774997Sgblack@eecs.umich.edu else: 784997Sgblack@eecs.umich.edu print "Don't know what TLB to use for ISA %s" % \ 794997Sgblack@eecs.umich.edu build_env['TARGET_ISA'] 804997Sgblack@eecs.umich.edu sys.exit(1) 814997Sgblack@eecs.umich.edu 821310SN/A max_insts_all_threads = Param.Counter(0, 831310SN/A "terminate when all threads have reached this inst count") 841310SN/A max_insts_any_thread = Param.Counter(0, 851310SN/A "terminate when any thread reaches this inst count") 861310SN/A max_loads_all_threads = Param.Counter(0, 871310SN/A "terminate when all threads have reached this load count") 881310SN/A max_loads_any_thread = Param.Counter(0, 891310SN/A "terminate when any thread reaches this load count") 903878SN/A progress_interval = Param.Tick(0, 913878SN/A "interval to print out the progress message") 921310SN/A 931369SN/A defer_registration = Param.Bool(False, 941310SN/A "defer registration with system (for sampling)") 951634SN/A 964167SN/A clock = Param.Clock('1t', "clock speed") 974167SN/A phase = Param.Latency('0ns', "clock phase") 982998SN/A 994776Sgblack@eecs.umich.edu tracer = Param.InstTracer(default_tracer, "Instruction tracer") 1004776Sgblack@eecs.umich.edu 1012998SN/A _mem_ports = [] 1022998SN/A 1032998SN/A def connectMemPorts(self, bus): 1042998SN/A for p in self._mem_ports: 1054968Sacolyte@umich.edu if p != 'physmem_port': 1064968Sacolyte@umich.edu exec('self.%s = bus.port' % p) 1072998SN/A 1082998SN/A def addPrivateSplitL1Caches(self, ic, dc): 1094968Sacolyte@umich.edu assert(len(self._mem_ports) == 2 or len(self._mem_ports) == 3) 1102998SN/A self.icache = ic 1112998SN/A self.dcache = dc 1122998SN/A self.icache_port = ic.cpu_side 1132998SN/A self.dcache_port = dc.cpu_side 1142998SN/A self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] 1152998SN/A 1162998SN/A def addTwoLevelCacheHierarchy(self, ic, dc, l2c): 1172998SN/A self.addPrivateSplitL1Caches(ic, dc) 1182998SN/A self.toL2Bus = Bus() 1192998SN/A self.connectMemPorts(self.toL2Bus) 1202998SN/A self.l2cache = l2c 1213017SN/A self.l2cache.cpu_side = self.toL2Bus.port 1222998SN/A self._mem_ports = ['l2cache.mem_side'] 123