BaseCPU.py revision 4167
11689SN/Afrom m5.SimObject import SimObject 22326SN/Afrom m5.params import * 31689SN/Afrom m5.proxy import * 41689SN/Afrom m5 import build_env 51689SN/Afrom AlphaTLB import AlphaDTB, AlphaITB 61689SN/Afrom SparcTLB import SparcDTB, SparcITB 71689SN/Afrom Bus import Bus 81689SN/Aimport sys 91689SN/A 101689SN/Aclass BaseCPU(SimObject): 111689SN/A type = 'BaseCPU' 121689SN/A abstract = True 131689SN/A 141689SN/A system = Param.System(Parent.any, "system object") 151689SN/A cpu_id = Param.Int("CPU identifier") 161689SN/A 171689SN/A if build_env['FULL_SYSTEM']: 181689SN/A do_quiesce = Param.Bool(True, "enable quiesce instructions") 191689SN/A do_checkpoint_insts = Param.Bool(True, 201689SN/A "enable checkpoint pseudo instructions") 211689SN/A do_statistics_insts = Param.Bool(True, 221689SN/A "enable statistics pseudo instructions") 231689SN/A 241689SN/A if build_env['TARGET_ISA'] == 'sparc': 251689SN/A dtb = Param.SparcDTB(SparcDTB(), "Data TLB") 261689SN/A itb = Param.SparcITB(SparcITB(), "Instruction TLB") 272665Ssaidi@eecs.umich.edu elif build_env['TARGET_ISA'] == 'alpha': 282665Ssaidi@eecs.umich.edu dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB") 291689SN/A itb = Param.AlphaITB(AlphaITB(), "Instruction TLB") 301689SN/A else: 311060SN/A print "Unknown architecture, can't pick TLBs" 321060SN/A sys.exit(1) 331689SN/A else: 341060SN/A workload = VectorParam.Process("processes to run") 351060SN/A 361060SN/A max_insts_all_threads = Param.Counter(0, 371060SN/A "terminate when all threads have reached this inst count") 382292SN/A max_insts_any_thread = Param.Counter(0, 391717SN/A "terminate when any thread reaches this inst count") 405529Snate@binkert.org max_loads_all_threads = Param.Counter(0, 411060SN/A "terminate when all threads have reached this load count") 421681SN/A max_loads_any_thread = Param.Counter(0, 435529Snate@binkert.org "terminate when any thread reaches this load count") 442873Sktlim@umich.edu progress_interval = Param.Tick(0, 454329Sktlim@umich.edu "interval to print out the progress message") 464329Sktlim@umich.edu 474329Sktlim@umich.edu defer_registration = Param.Bool(False, 482292SN/A "defer registration with system (for sampling)") 492292SN/A 502292SN/A clock = Param.Clock('1t', "clock speed") 512292SN/A phase = Param.Latency('0ns', "clock phase") 522820Sktlim@umich.edu 532292SN/A _mem_ports = [] 542820Sktlim@umich.edu 552820Sktlim@umich.edu def connectMemPorts(self, bus): 565529Snate@binkert.org for p in self._mem_ports: 572307SN/A exec('self.%s = bus.port' % p) 581060SN/A 592292SN/A def addPrivateSplitL1Caches(self, ic, dc): 602292SN/A assert(len(self._mem_ports) == 2) 612292SN/A self.icache = ic 621060SN/A self.dcache = dc 631060SN/A self.icache_port = ic.cpu_side 641060SN/A self.dcache_port = dc.cpu_side 651060SN/A self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] 661060SN/A 671060SN/A def addTwoLevelCacheHierarchy(self, ic, dc, l2c): 681681SN/A self.addPrivateSplitL1Caches(ic, dc) 692292SN/A self.toL2Bus = Bus() 702292SN/A self.connectMemPorts(self.toL2Bus) 712292SN/A self.l2cache = l2c 722292SN/A self.l2cache.cpu_side = self.toL2Bus.port 732292SN/A self._mem_ports = ['l2cache.mem_side'] 742292SN/A