BaseCPU.py revision 3617
1from m5.SimObject import SimObject 2from m5.params import * 3from m5.proxy import * 4from m5 import build_env 5from AlphaTLB import AlphaDTB, AlphaITB 6from SparcTLB import SparcDTB, SparcITB 7from Bus import Bus 8import sys 9 10class BaseCPU(SimObject): 11 type = 'BaseCPU' 12 abstract = True 13 14 system = Param.System(Parent.any, "system object") 15 cpu_id = Param.Int("CPU identifier") 16 17 if build_env['FULL_SYSTEM']: 18 do_qiesce = Param.Bool(True, "enable quiesce instructions") 19 do_checkpoint_insts = Param.Bool(True, 20 "enable checkpoint pseudo instructions") 21 do_statistics_insts = Param.Bool(True, 22 "enable statistics pseudo instructions") 23 24 if build_env['TARGET_ISA'] == 'sparc': 25 dtb = Param.SparcDTB(SparcDTB(), "Data TLB") 26 itb = Param.SparcITB(SparcITB(), "Instruction TLB") 27 elif build_env['TARGET_ISA'] == 'alpha': 28 dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB") 29 itb = Param.AlphaITB(AlphaITB(), "Instruction TLB") 30 else: 31 print "Unknown architecture, can't pick TLBs" 32 sys.exit(1) 33 else: 34 workload = VectorParam.Process("processes to run") 35 36 max_insts_all_threads = Param.Counter(0, 37 "terminate when all threads have reached this inst count") 38 max_insts_any_thread = Param.Counter(0, 39 "terminate when any thread reaches this inst count") 40 max_loads_all_threads = Param.Counter(0, 41 "terminate when all threads have reached this load count") 42 max_loads_any_thread = Param.Counter(0, 43 "terminate when any thread reaches this load count") 44 progress_interval = Param.Tick(0, "interval to print out the progress message") 45 46 defer_registration = Param.Bool(False, 47 "defer registration with system (for sampling)") 48 49 clock = Param.Clock(Parent.clock, "clock speed") 50 51 _mem_ports = [] 52 53 def connectMemPorts(self, bus): 54 for p in self._mem_ports: 55 exec('self.%s = bus.port' % p) 56 57 def addPrivateSplitL1Caches(self, ic, dc): 58 assert(len(self._mem_ports) == 2) 59 self.icache = ic 60 self.dcache = dc 61 self.icache_port = ic.cpu_side 62 self.dcache_port = dc.cpu_side 63 self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] 64 65 def addTwoLevelCacheHierarchy(self, ic, dc, l2c): 66 self.addPrivateSplitL1Caches(ic, dc) 67 self.toL2Bus = Bus() 68 self.connectMemPorts(self.toL2Bus) 69 self.l2cache = l2c 70 self.l2cache.cpu_side = self.toL2Bus.port 71 self._mem_ports = ['l2cache.mem_side'] 72