BaseCPU.py revision 3584 
1from m5.SimObject import SimObject
2from m5.params import *
3from m5.proxy import *
4from m5 import build_env
5from AlphaTLB import AlphaDTB, AlphaITB
6from SparcTLB import SparcDTB, SparcITB
7from Bus import Bus
8import sys
9
10class BaseCPU(SimObject):
11    type = 'BaseCPU'
12    abstract = True
13
14    system = Param.System(Parent.any, "system object")
15    cpu_id = Param.Int("CPU identifier")
16
17    if build_env['FULL_SYSTEM']:
18        if build_env['TARGET_ISA'] == 'sparc':
19            dtb = Param.SparcDTB(SparcDTB(), "Data TLB")
20            itb = Param.SparcITB(SparcITB(), "Instruction TLB")
21        elif build_env['TARGET_ISA'] == 'alpha':
22            dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
23            itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
24        else:
25            print "Unknown architecture, can't pick TLBs"
26            sys.exit(1)
27    else:
28        workload = VectorParam.Process("processes to run")
29
30    max_insts_all_threads = Param.Counter(0,
31        "terminate when all threads have reached this inst count")
32    max_insts_any_thread = Param.Counter(0,
33        "terminate when any thread reaches this inst count")
34    max_loads_all_threads = Param.Counter(0,
35        "terminate when all threads have reached this load count")
36    max_loads_any_thread = Param.Counter(0,
37        "terminate when any thread reaches this load count")
38    progress_interval = Param.Tick(0, "interval to print out the progress message")
39
40    defer_registration = Param.Bool(False,
41        "defer registration with system (for sampling)")
42
43    clock = Param.Clock(Parent.clock, "clock speed")
44
45    _mem_ports = []
46
47    def connectMemPorts(self, bus):
48        for p in self._mem_ports:
49            exec('self.%s = bus.port' % p)
50
51    def addPrivateSplitL1Caches(self, ic, dc):
52        assert(len(self._mem_ports) == 2)
53        self.icache = ic
54        self.dcache = dc
55        self.icache_port = ic.cpu_side
56        self.dcache_port = dc.cpu_side
57        self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
58
59    def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
60        self.addPrivateSplitL1Caches(ic, dc)
61        self.toL2Bus = Bus()
62        self.connectMemPorts(self.toL2Bus)
63        self.l2cache = l2c
64        self.l2cache.cpu_side = self.toL2Bus.port
65        self._mem_ports = ['l2cache.mem_side']
66