BaseCPU.py revision 3170
11689SN/Afrom m5.SimObject import SimObject 29783Sandreas.hansson@arm.comfrom m5.params import * 310239Sbinhpham@cs.rutgers.edufrom m5.proxy import * 47598Sminkyu.jeong@arm.comfrom m5 import build_env 57598Sminkyu.jeong@arm.comfrom AlphaTLB import AlphaDTB, AlphaITB 67598Sminkyu.jeong@arm.comfrom Bus import Bus 77598Sminkyu.jeong@arm.com 87598Sminkyu.jeong@arm.comclass BaseCPU(SimObject): 97598Sminkyu.jeong@arm.com type = 'BaseCPU' 107598Sminkyu.jeong@arm.com abstract = True 117598Sminkyu.jeong@arm.com mem = Param.MemObject("memory") 127598Sminkyu.jeong@arm.com 137598Sminkyu.jeong@arm.com system = Param.System(Parent.any, "system object") 147598Sminkyu.jeong@arm.com cpu_id = Param.Int("CPU identifier") 152326SN/A 161689SN/A if build_env['FULL_SYSTEM']: 171689SN/A dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB") 181689SN/A itb = Param.AlphaITB(AlphaITB(), "Instruction TLB") 191689SN/A else: 201689SN/A workload = VectorParam.Process("processes to run") 211689SN/A 221689SN/A max_insts_all_threads = Param.Counter(0, 231689SN/A "terminate when all threads have reached this inst count") 241689SN/A max_insts_any_thread = Param.Counter(0, 251689SN/A "terminate when any thread reaches this inst count") 261689SN/A max_loads_all_threads = Param.Counter(0, 271689SN/A "terminate when all threads have reached this load count") 281689SN/A max_loads_any_thread = Param.Counter(0, 291689SN/A "terminate when any thread reaches this load count") 301689SN/A progress_interval = Param.Tick(0, "interval to print out the progress message") 311689SN/A 321689SN/A defer_registration = Param.Bool(False, 331689SN/A "defer registration with system (for sampling)") 341689SN/A 351689SN/A clock = Param.Clock(Parent.clock, "clock speed") 361689SN/A 371689SN/A _mem_ports = [] 381689SN/A 391689SN/A def connectMemPorts(self, bus): 402665Ssaidi@eecs.umich.edu for p in self._mem_ports: 412665Ssaidi@eecs.umich.edu exec('self.%s = bus.port' % p) 421689SN/A 431689SN/A def addPrivateSplitL1Caches(self, ic, dc): 449944Smatt.horsnell@ARM.com assert(len(self._mem_ports) == 2) 459944Smatt.horsnell@ARM.com self.icache = ic 469944Smatt.horsnell@ARM.com self.dcache = dc 471060SN/A self.icache_port = ic.cpu_side 481060SN/A self.dcache_port = dc.cpu_side 491689SN/A self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] 501060SN/A# self.mem = dc 511060SN/A 521060SN/A def addTwoLevelCacheHierarchy(self, ic, dc, l2c): 538230Snate@binkert.org self.addPrivateSplitL1Caches(ic, dc) 546658Snate@binkert.org self.toL2Bus = Bus() 558887Sgeoffrey.blake@arm.com self.connectMemPorts(self.toL2Bus) 562292SN/A self.l2cache = l2c 571717SN/A self.l2cache.cpu_side = self.toL2Bus.port 588229Snate@binkert.org self._mem_ports = ['l2cache.mem_side'] 598232Snate@binkert.org