BaseCPU.py revision 1692 
16782SN/Afrom m5 import *
28683SN/Aclass BaseCPU(SimObject):
36782SN/A    type = 'BaseCPU'
46782SN/A    abstract = True
56782SN/A    icache = Param.BaseMem(NULL, "L1 instruction cache object")
66782SN/A    dcache = Param.BaseMem(NULL, "L1 data cache object")
76782SN/A
86782SN/A    if build_env['FULL_SYSTEM']:
96782SN/A        dtb = Param.AlphaDTB("Data TLB")
106782SN/A        itb = Param.AlphaITB("Instruction TLB")
116782SN/A        mem = Param.FunctionalMemory("memory")
126782SN/A        system = Param.BaseSystem(Parent.any, "system object")
136782SN/A    else:
146782SN/A        workload = VectorParam.Process("processes to run")
156782SN/A
166782SN/A    max_insts_all_threads = Param.Counter(0,
176782SN/A        "terminate when all threads have reached this inst count")
186782SN/A    max_insts_any_thread = Param.Counter(0,
196782SN/A        "terminate when any thread reaches this inst count")
206782SN/A    max_loads_all_threads = Param.Counter(0,
216782SN/A        "terminate when all threads have reached this load count")
226782SN/A    max_loads_any_thread = Param.Counter(0,
236782SN/A        "terminate when any thread reaches this load count")
246782SN/A
256782SN/A    defer_registration = Param.Bool(False,
266782SN/A        "defer registration with system (for sampling)")
276782SN/A
286782SN/A    cycle_time = Param.Latency(Parent.frequency.latency, "clock speed")
297056SN/A