BaseCPU.py revision 13709
112276Sanouk.vanlaer@arm.com# Copyright (c) 2012-2013, 2015-2017 ARM Limited 28839Sandreas.hansson@arm.com# All rights reserved. 38839Sandreas.hansson@arm.com# 48839Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 58839Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 68839Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 78839Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 88839Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 98839Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 108839Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 118839Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 128839Sandreas.hansson@arm.com# 135335Shines@cs.fsu.edu# Copyright (c) 2005-2008 The Regents of The University of Michigan 147897Shestness@cs.utexas.edu# Copyright (c) 2011 Regents of the University of California 154486Sbinkertn@umich.edu# All rights reserved. 164486Sbinkertn@umich.edu# 174486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 184486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 194486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 204486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 214486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 224486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 234486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 244486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 254486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 264486Sbinkertn@umich.edu# this software without specific prior written permission. 274486Sbinkertn@umich.edu# 284486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 324486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 364486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 384486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394486Sbinkertn@umich.edu# 404486Sbinkertn@umich.edu# Authors: Nathan Binkert 417897Shestness@cs.utexas.edu# Rick Strong 428839Sandreas.hansson@arm.com# Andreas Hansson 4312470Sglenn.bergmans@arm.com# Glenn Bergmans 444486Sbinkertn@umich.edu 4512563Sgabeblack@google.comfrom __future__ import print_function 4612563Sgabeblack@google.com 476654Snate@binkert.orgimport sys 486654Snate@binkert.org 4911988Sandreas.sandberg@arm.comfrom m5.SimObject import * 506654Snate@binkert.orgfrom m5.defines import buildEnv 513102SN/Afrom m5.params import * 523102SN/Afrom m5.proxy import * 5312470Sglenn.bergmans@arm.comfrom m5.util.fdthelper import * 546654Snate@binkert.org 5513665Sandreas.sandberg@arm.comfrom m5.objects.XBar import L2XBar 5613665Sandreas.sandberg@arm.comfrom m5.objects.InstTracer import InstTracer 5713665Sandreas.sandberg@arm.comfrom m5.objects.CPUTracers import ExeTracer 5813665Sandreas.sandberg@arm.comfrom m5.objects.MemObject import MemObject 5913665Sandreas.sandberg@arm.comfrom m5.objects.SubSystem import SubSystem 6013665Sandreas.sandberg@arm.comfrom m5.objects.ClockDomain import * 6113665Sandreas.sandberg@arm.comfrom m5.objects.Platform import Platform 622667SN/A 634776Sgblack@eecs.umich.edudefault_tracer = ExeTracer() 644776Sgblack@eecs.umich.edu 656654Snate@binkert.orgif buildEnv['TARGET_ISA'] == 'alpha': 6613665Sandreas.sandberg@arm.com from m5.objects.AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB 6713665Sandreas.sandberg@arm.com from m5.objects.AlphaInterrupts import AlphaInterrupts 6813665Sandreas.sandberg@arm.com from m5.objects.AlphaISA import AlphaISA 6912325Sandreas.sandberg@arm.com default_isa_class = AlphaISA 706654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'sparc': 7113665Sandreas.sandberg@arm.com from m5.objects.SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB 7213665Sandreas.sandberg@arm.com from m5.objects.SparcInterrupts import SparcInterrupts 7313665Sandreas.sandberg@arm.com from m5.objects.SparcISA import SparcISA 7412325Sandreas.sandberg@arm.com default_isa_class = SparcISA 756654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'x86': 7613665Sandreas.sandberg@arm.com from m5.objects.X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB 7713665Sandreas.sandberg@arm.com from m5.objects.X86LocalApic import X86LocalApic 7813665Sandreas.sandberg@arm.com from m5.objects.X86ISA import X86ISA 7912325Sandreas.sandberg@arm.com default_isa_class = X86ISA 806654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'mips': 8113665Sandreas.sandberg@arm.com from m5.objects.MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB 8213665Sandreas.sandberg@arm.com from m5.objects.MipsInterrupts import MipsInterrupts 8313665Sandreas.sandberg@arm.com from m5.objects.MipsISA import MipsISA 8412325Sandreas.sandberg@arm.com default_isa_class = MipsISA 856654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'arm': 8613665Sandreas.sandberg@arm.com from m5.objects.ArmTLB import ArmTLB as ArchDTB, ArmTLB as ArchITB 8713665Sandreas.sandberg@arm.com from m5.objects.ArmTLB import ArmStage2IMMU, ArmStage2DMMU 8813665Sandreas.sandberg@arm.com from m5.objects.ArmInterrupts import ArmInterrupts 8913665Sandreas.sandberg@arm.com from m5.objects.ArmISA import ArmISA 9012325Sandreas.sandberg@arm.com default_isa_class = ArmISA 916691Stjones1@inf.ed.ac.ukelif buildEnv['TARGET_ISA'] == 'power': 9213665Sandreas.sandberg@arm.com from m5.objects.PowerTLB import PowerTLB as ArchDTB, PowerTLB as ArchITB 9313665Sandreas.sandberg@arm.com from m5.objects.PowerInterrupts import PowerInterrupts 9413665Sandreas.sandberg@arm.com from m5.objects.PowerISA import PowerISA 9512325Sandreas.sandberg@arm.com default_isa_class = PowerISA 9611723Sar4jc@virginia.eduelif buildEnv['TARGET_ISA'] == 'riscv': 9713665Sandreas.sandberg@arm.com from m5.objects.RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB 9813665Sandreas.sandberg@arm.com from m5.objects.RiscvInterrupts import RiscvInterrupts 9913665Sandreas.sandberg@arm.com from m5.objects.RiscvISA import RiscvISA 10012325Sandreas.sandberg@arm.com default_isa_class = RiscvISA 1014486Sbinkertn@umich.edu 1025529Snate@binkert.orgclass BaseCPU(MemObject): 1031366SN/A type = 'BaseCPU' 1041310SN/A abstract = True 1059338SAndreas.Sandberg@arm.com cxx_header = "cpu/base.hh" 1069254SAndreas.Sandberg@arm.com 10711988Sandreas.sandberg@arm.com cxx_exports = [ 10811988Sandreas.sandberg@arm.com PyBindMethod("switchOut"), 10911988Sandreas.sandberg@arm.com PyBindMethod("takeOverFrom"), 11011988Sandreas.sandberg@arm.com PyBindMethod("switchedOut"), 11111988Sandreas.sandberg@arm.com PyBindMethod("flushTLBs"), 11211988Sandreas.sandberg@arm.com PyBindMethod("totalInsts"), 11311988Sandreas.sandberg@arm.com PyBindMethod("scheduleInstStop"), 11411988Sandreas.sandberg@arm.com PyBindMethod("scheduleLoadStop"), 11511988Sandreas.sandberg@arm.com PyBindMethod("getCurrentInstCount"), 11611988Sandreas.sandberg@arm.com ] 1179254SAndreas.Sandberg@arm.com 1189518SAndreas.Sandberg@ARM.com @classmethod 1199518SAndreas.Sandberg@ARM.com def memory_mode(cls): 1209518SAndreas.Sandberg@ARM.com """Which memory mode does this CPU require?""" 1219518SAndreas.Sandberg@ARM.com return 'invalid' 1229518SAndreas.Sandberg@ARM.com 1239518SAndreas.Sandberg@ARM.com @classmethod 1249518SAndreas.Sandberg@ARM.com def require_caches(cls): 1259518SAndreas.Sandberg@ARM.com """Does the CPU model require caches? 1269518SAndreas.Sandberg@ARM.com 1279518SAndreas.Sandberg@ARM.com Some CPU models might make assumptions that require them to 1289518SAndreas.Sandberg@ARM.com have caches. 1299518SAndreas.Sandberg@ARM.com """ 1309518SAndreas.Sandberg@ARM.com return False 1319518SAndreas.Sandberg@ARM.com 1329518SAndreas.Sandberg@ARM.com @classmethod 1339518SAndreas.Sandberg@ARM.com def support_take_over(cls): 1349518SAndreas.Sandberg@ARM.com """Does the CPU model support CPU takeOverFrom?""" 1359518SAndreas.Sandberg@ARM.com return False 1369518SAndreas.Sandberg@ARM.com 1379254SAndreas.Sandberg@arm.com def takeOverFrom(self, old_cpu): 1389254SAndreas.Sandberg@arm.com self._ccObject.takeOverFrom(old_cpu._ccObject) 1399254SAndreas.Sandberg@arm.com 1409254SAndreas.Sandberg@arm.com 1412901SN/A system = Param.System(Parent.any, "system object") 1425712Shsul@eecs.umich.edu cpu_id = Param.Int(-1, "CPU identifier") 14310190Sakash.bagdia@arm.com socket_id = Param.Unsigned(0, "Physical Socket identifier") 1445529Snate@binkert.org numThreads = Param.Unsigned(1, "number of HW thread contexts") 14512276Sanouk.vanlaer@arm.com pwr_gating_latency = Param.Cycles(300, 14612276Sanouk.vanlaer@arm.com "Latency to enter power gating state when all contexts are suspended") 1475529Snate@binkert.org 14812277Sjose.marinho@arm.com power_gating_on_idle = Param.Bool(False, "Control whether the core goes "\ 14912277Sjose.marinho@arm.com "to the OFF power state after all thread are disabled for "\ 15012277Sjose.marinho@arm.com "pwr_gating_latency cycles") 15112277Sjose.marinho@arm.com 1525529Snate@binkert.org function_trace = Param.Bool(False, "Enable function trace") 1539161Sandreas.hansson@arm.com function_trace_start = Param.Tick(0, "Tick to start function trace") 1545529Snate@binkert.org 1555821Ssaidi@eecs.umich.edu checker = Param.BaseCPU(NULL, "checker CPU") 1563170SN/A 15711877Sbrandon.potter@amd.com syscallRetryLatency = Param.Cycles(10000, "Cycles to wait until retry") 15811877Sbrandon.potter@amd.com 1595780Ssteve.reinhardt@amd.com do_checkpoint_insts = Param.Bool(True, 1605780Ssteve.reinhardt@amd.com "enable checkpoint pseudo instructions") 1615780Ssteve.reinhardt@amd.com do_statistics_insts = Param.Bool(True, 1625780Ssteve.reinhardt@amd.com "enable statistics pseudo instructions") 1635780Ssteve.reinhardt@amd.com 1648784Sgblack@eecs.umich.edu profile = Param.Latency('0ns', "trace the kernel stack") 1658784Sgblack@eecs.umich.edu do_quiesce = Param.Bool(True, "enable quiesce instructions") 1668784Sgblack@eecs.umich.edu 16712122Sjose.marinho@arm.com wait_for_remote_gdb = Param.Bool(False, 16812122Sjose.marinho@arm.com "Wait for a remote GDB connection"); 16912122Sjose.marinho@arm.com 1708793Sgblack@eecs.umich.edu workload = VectorParam.Process([], "processes to run") 1711310SN/A 17212434Sgabeblack@google.com dtb = Param.BaseTLB(ArchDTB(), "Data TLB") 17312434Sgabeblack@google.com itb = Param.BaseTLB(ArchITB(), "Instruction TLB") 1746654Snate@binkert.org if buildEnv['TARGET_ISA'] == 'sparc': 17511150Smitch.hayenga@arm.com interrupts = VectorParam.SparcInterrupts( 17611150Smitch.hayenga@arm.com [], "Interrupt Controller") 17712325Sandreas.sandberg@arm.com isa = VectorParam.SparcISA([], "ISA instance") 1786654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'alpha': 17911150Smitch.hayenga@arm.com interrupts = VectorParam.AlphaInterrupts( 18011150Smitch.hayenga@arm.com [], "Interrupt Controller") 18112325Sandreas.sandberg@arm.com isa = VectorParam.AlphaISA([], "ISA instance") 1826654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'x86': 18311150Smitch.hayenga@arm.com interrupts = VectorParam.X86LocalApic([], "Interrupt Controller") 18412325Sandreas.sandberg@arm.com isa = VectorParam.X86ISA([], "ISA instance") 1856654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'mips': 18611150Smitch.hayenga@arm.com interrupts = VectorParam.MipsInterrupts( 18711150Smitch.hayenga@arm.com [], "Interrupt Controller") 18812325Sandreas.sandberg@arm.com isa = VectorParam.MipsISA([], "ISA instance") 1896654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'arm': 19010037SARM gem5 Developers istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans") 19110037SARM gem5 Developers dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans") 19211150Smitch.hayenga@arm.com interrupts = VectorParam.ArmInterrupts( 19311150Smitch.hayenga@arm.com [], "Interrupt Controller") 19412325Sandreas.sandberg@arm.com isa = VectorParam.ArmISA([], "ISA instance") 1956691Stjones1@inf.ed.ac.uk elif buildEnv['TARGET_ISA'] == 'power': 1966691Stjones1@inf.ed.ac.uk UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 19711150Smitch.hayenga@arm.com interrupts = VectorParam.PowerInterrupts( 19811150Smitch.hayenga@arm.com [], "Interrupt Controller") 19912325Sandreas.sandberg@arm.com isa = VectorParam.PowerISA([], "ISA instance") 20011723Sar4jc@virginia.edu elif buildEnv['TARGET_ISA'] == 'riscv': 20111723Sar4jc@virginia.edu interrupts = VectorParam.RiscvInterrupts( 20211723Sar4jc@virginia.edu [], "Interrupt Controller") 20312325Sandreas.sandberg@arm.com isa = VectorParam.RiscvISA([], "ISA instance") 2044997Sgblack@eecs.umich.edu else: 20512563Sgabeblack@google.com print("Don't know what TLB to use for ISA %s" % 20612563Sgabeblack@google.com buildEnv['TARGET_ISA']) 2074997Sgblack@eecs.umich.edu sys.exit(1) 2084997Sgblack@eecs.umich.edu 2091310SN/A max_insts_all_threads = Param.Counter(0, 2101310SN/A "terminate when all threads have reached this inst count") 2111310SN/A max_insts_any_thread = Param.Counter(0, 2121310SN/A "terminate when any thread reaches this inst count") 2139647Sdam.sunwoo@arm.com simpoint_start_insts = VectorParam.Counter([], 2149647Sdam.sunwoo@arm.com "starting instruction counts of simpoints") 2151310SN/A max_loads_all_threads = Param.Counter(0, 2161310SN/A "terminate when all threads have reached this load count") 2171310SN/A max_loads_any_thread = Param.Counter(0, 2181310SN/A "terminate when any thread reaches this load count") 2199180Sandreas.hansson@arm.com progress_interval = Param.Frequency('0Hz', 2209180Sandreas.hansson@arm.com "frequency to print out the progress message") 2211310SN/A 2229433SAndreas.Sandberg@ARM.com switched_out = Param.Bool(False, 2239433SAndreas.Sandberg@ARM.com "Leave the CPU switched out after startup (used when switching " \ 2249433SAndreas.Sandberg@ARM.com "between CPU models)") 2251634SN/A 2264776Sgblack@eecs.umich.edu tracer = Param.InstTracer(default_tracer, "Instruction tracer") 2274776Sgblack@eecs.umich.edu 2288839Sandreas.hansson@arm.com icache_port = MasterPort("Instruction Port") 2298839Sandreas.hansson@arm.com dcache_port = MasterPort("Data Port") 2308707Sandreas.hansson@arm.com _cached_ports = ['icache_port', 'dcache_port'] 2318707Sandreas.hansson@arm.com 2328756Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 2338707Sandreas.hansson@arm.com _cached_ports += ["itb.walker.port", "dtb.walker.port"] 2347876Sgblack@eecs.umich.edu 2358839Sandreas.hansson@arm.com _uncached_slave_ports = [] 2368839Sandreas.hansson@arm.com _uncached_master_ports = [] 2378745Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'x86': 23811150Smitch.hayenga@arm.com _uncached_slave_ports += ["interrupts[0].pio", 23911150Smitch.hayenga@arm.com "interrupts[0].int_slave"] 24011150Smitch.hayenga@arm.com _uncached_master_ports += ["interrupts[0].int_master"] 2412998SN/A 2428863Snilay@cs.wisc.edu def createInterruptController(self): 2438863Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] == 'sparc': 24413709Sandreas.sandberg@arm.com self.interrupts = [SparcInterrupts() for i in range(self.numThreads)] 2458863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'alpha': 24613709Sandreas.sandberg@arm.com self.interrupts = [AlphaInterrupts() for i in range(self.numThreads)] 2478863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'x86': 2489793Sakash.bagdia@arm.com self.apic_clk_domain = DerivedClockDomain(clk_domain = 2499793Sakash.bagdia@arm.com Parent.clk_domain, 2509793Sakash.bagdia@arm.com clk_divider = 16) 25111150Smitch.hayenga@arm.com self.interrupts = [X86LocalApic(clk_domain = self.apic_clk_domain, 2529544Sandreas.hansson@arm.com pio_addr=0x2000000000000000) 25313709Sandreas.sandberg@arm.com for i in range(self.numThreads)] 2549544Sandreas.hansson@arm.com _localApic = self.interrupts 2558863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'mips': 25613709Sandreas.sandberg@arm.com self.interrupts = [MipsInterrupts() for i in range(self.numThreads)] 2578863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'arm': 25813709Sandreas.sandberg@arm.com self.interrupts = [ArmInterrupts() for i in range(self.numThreads)] 2598863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'power': 26013709Sandreas.sandberg@arm.com self.interrupts = [PowerInterrupts() for i in range(self.numThreads)] 26111723Sar4jc@virginia.edu elif buildEnv['TARGET_ISA'] == 'riscv': 26211723Sar4jc@virginia.edu self.interrupts = \ 26313709Sandreas.sandberg@arm.com [RiscvInterrupts() for i in range(self.numThreads)] 2648863Snilay@cs.wisc.edu else: 26512563Sgabeblack@google.com print("Don't know what Interrupt Controller to use for ISA %s" % 26612563Sgabeblack@google.com buildEnv['TARGET_ISA']) 2678863Snilay@cs.wisc.edu sys.exit(1) 2688863Snilay@cs.wisc.edu 2697876Sgblack@eecs.umich.edu def connectCachedPorts(self, bus): 2707876Sgblack@eecs.umich.edu for p in self._cached_ports: 2718839Sandreas.hansson@arm.com exec('self.%s = bus.slave' % p) 2727404SAli.Saidi@ARM.com 2737876Sgblack@eecs.umich.edu def connectUncachedPorts(self, bus): 2748839Sandreas.hansson@arm.com for p in self._uncached_slave_ports: 2758839Sandreas.hansson@arm.com exec('self.%s = bus.master' % p) 2768839Sandreas.hansson@arm.com for p in self._uncached_master_ports: 2778839Sandreas.hansson@arm.com exec('self.%s = bus.slave' % p) 2787876Sgblack@eecs.umich.edu 2797876Sgblack@eecs.umich.edu def connectAllPorts(self, cached_bus, uncached_bus = None): 2807876Sgblack@eecs.umich.edu self.connectCachedPorts(cached_bus) 2817876Sgblack@eecs.umich.edu if not uncached_bus: 2827876Sgblack@eecs.umich.edu uncached_bus = cached_bus 2837876Sgblack@eecs.umich.edu self.connectUncachedPorts(uncached_bus) 2842998SN/A 2857868Sgblack@eecs.umich.edu def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 2862998SN/A self.icache = ic 2872998SN/A self.dcache = dc 2882998SN/A self.icache_port = ic.cpu_side 2892998SN/A self.dcache_port = dc.cpu_side 2907876Sgblack@eecs.umich.edu self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 2918796Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 2928796Sgblack@eecs.umich.edu if iwc and dwc: 2938796Sgblack@eecs.umich.edu self.itb_walker_cache = iwc 2948796Sgblack@eecs.umich.edu self.dtb_walker_cache = dwc 29510717Sandreas.hansson@arm.com self.itb.walker.port = iwc.cpu_side 29610717Sandreas.hansson@arm.com self.dtb.walker.port = dwc.cpu_side 2978796Sgblack@eecs.umich.edu self._cached_ports += ["itb_walker_cache.mem_side", \ 2988796Sgblack@eecs.umich.edu "dtb_walker_cache.mem_side"] 2998796Sgblack@eecs.umich.edu else: 3008796Sgblack@eecs.umich.edu self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 3018887Sgeoffrey.blake@arm.com 3028809Sgblack@eecs.umich.edu # Checker doesn't need its own tlb caches because it does 3038809Sgblack@eecs.umich.edu # functional accesses only 3048887Sgeoffrey.blake@arm.com if self.checker != NULL: 3058809Sgblack@eecs.umich.edu self._cached_ports += ["checker.itb.walker.port", \ 3068809Sgblack@eecs.umich.edu "checker.dtb.walker.port"] 3072998SN/A 30812440Sxiaoyuma@google.com def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc=None, dwc=None, 30912440Sxiaoyuma@google.com xbar=None): 3107868Sgblack@eecs.umich.edu self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 31112440Sxiaoyuma@google.com self.toL2Bus = xbar if xbar else L2XBar() 3127876Sgblack@eecs.umich.edu self.connectCachedPorts(self.toL2Bus) 3132998SN/A self.l2cache = l2c 3148839Sandreas.hansson@arm.com self.toL2Bus.master = self.l2cache.cpu_side 3157876Sgblack@eecs.umich.edu self._cached_ports = ['l2cache.mem_side'] 3168887Sgeoffrey.blake@arm.com 3179384SAndreas.Sandberg@arm.com def createThreads(self): 31812325Sandreas.sandberg@arm.com # If no ISAs have been created, assume that the user wants the 31912325Sandreas.sandberg@arm.com # default ISA. 32012325Sandreas.sandberg@arm.com if len(self.isa) == 0: 32113709Sandreas.sandberg@arm.com self.isa = [ default_isa_class() for i in range(self.numThreads) ] 32212325Sandreas.sandberg@arm.com else: 32312325Sandreas.sandberg@arm.com if len(self.isa) != int(self.numThreads): 32412325Sandreas.sandberg@arm.com raise RuntimeError("Number of ISA instances doesn't " 32512325Sandreas.sandberg@arm.com "match thread count") 3269384SAndreas.Sandberg@arm.com if self.checker != NULL: 3279384SAndreas.Sandberg@arm.com self.checker.createThreads() 3289384SAndreas.Sandberg@arm.com 3298887Sgeoffrey.blake@arm.com def addCheckerCpu(self): 3308887Sgeoffrey.blake@arm.com pass 33112470Sglenn.bergmans@arm.com 33212470Sglenn.bergmans@arm.com def createPhandleKey(self, thread): 33312470Sglenn.bergmans@arm.com # This method creates a unique key for this cpu as a function of a 33412470Sglenn.bergmans@arm.com # certain thread 33512470Sglenn.bergmans@arm.com return 'CPU-%d-%d-%d' % (self.socket_id, self.cpu_id, thread) 33612470Sglenn.bergmans@arm.com 33712470Sglenn.bergmans@arm.com #Generate simple CPU Device Tree structure 33812470Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 33912470Sglenn.bergmans@arm.com """Generate cpu nodes for each thread and the corresponding part of the 34012470Sglenn.bergmans@arm.com cpu-map node. Note that this implementation does not support clusters 34112470Sglenn.bergmans@arm.com of clusters. Note that GEM5 is not compatible with the official way of 34212470Sglenn.bergmans@arm.com numbering cores as defined in the Device Tree documentation. Where the 34312470Sglenn.bergmans@arm.com cpu_id needs to reset to 0 for each cluster by specification, GEM5 34412470Sglenn.bergmans@arm.com expects the cpu_id to be globally unique and incremental. This 34512470Sglenn.bergmans@arm.com generated node adheres the GEM5 way of doing things.""" 34612470Sglenn.bergmans@arm.com if bool(self.switched_out): 34712470Sglenn.bergmans@arm.com return 34812470Sglenn.bergmans@arm.com 34912470Sglenn.bergmans@arm.com cpus_node = FdtNode('cpus') 35012470Sglenn.bergmans@arm.com cpus_node.append(state.CPUCellsProperty()) 35112470Sglenn.bergmans@arm.com #Special size override of 0 35212470Sglenn.bergmans@arm.com cpus_node.append(FdtPropertyWords('#size-cells', [0])) 35312470Sglenn.bergmans@arm.com 35412470Sglenn.bergmans@arm.com # Generate cpu nodes 35512470Sglenn.bergmans@arm.com for i in range(int(self.numThreads)): 35612470Sglenn.bergmans@arm.com reg = (int(self.socket_id)<<8) + int(self.cpu_id) + i 35712470Sglenn.bergmans@arm.com node = FdtNode("cpu@%x" % reg) 35812470Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("device_type", "cpu")) 35912470Sglenn.bergmans@arm.com node.appendCompatible(["gem5,arm-cpu"]) 36012470Sglenn.bergmans@arm.com node.append(FdtPropertyWords("reg", state.CPUAddrCells(reg))) 36112470Sglenn.bergmans@arm.com platform, found = self.system.unproxy(self).find_any(Platform) 36212470Sglenn.bergmans@arm.com if found: 36312470Sglenn.bergmans@arm.com platform.annotateCpuDeviceNode(node, state) 36412470Sglenn.bergmans@arm.com else: 36512470Sglenn.bergmans@arm.com warn("Platform not found for device tree generation; " \ 36612470Sglenn.bergmans@arm.com "system or multiple CPUs may not start") 36712470Sglenn.bergmans@arm.com 36812470Sglenn.bergmans@arm.com freq = round(self.clk_domain.unproxy(self).clock[0].frequency) 36912470Sglenn.bergmans@arm.com node.append(FdtPropertyWords("clock-frequency", freq)) 37012470Sglenn.bergmans@arm.com 37112470Sglenn.bergmans@arm.com # Unique key for this CPU 37212470Sglenn.bergmans@arm.com phandle_key = self.createPhandleKey(i) 37312470Sglenn.bergmans@arm.com node.appendPhandle(phandle_key) 37412470Sglenn.bergmans@arm.com cpus_node.append(node) 37512470Sglenn.bergmans@arm.com 37612470Sglenn.bergmans@arm.com yield cpus_node 377