BaseCPU.py revision 12470
112276Sanouk.vanlaer@arm.com# Copyright (c) 2012-2013, 2015-2017 ARM Limited 28839Sandreas.hansson@arm.com# All rights reserved. 38839Sandreas.hansson@arm.com# 48839Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 58839Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 68839Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 78839Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 88839Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 98839Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 108839Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 118839Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 128839Sandreas.hansson@arm.com# 135335Shines@cs.fsu.edu# Copyright (c) 2005-2008 The Regents of The University of Michigan 147897Shestness@cs.utexas.edu# Copyright (c) 2011 Regents of the University of California 154486Sbinkertn@umich.edu# All rights reserved. 164486Sbinkertn@umich.edu# 174486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 184486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 194486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 204486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 214486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 224486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 234486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 244486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 254486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 264486Sbinkertn@umich.edu# this software without specific prior written permission. 274486Sbinkertn@umich.edu# 284486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 324486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 364486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 384486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394486Sbinkertn@umich.edu# 404486Sbinkertn@umich.edu# Authors: Nathan Binkert 417897Shestness@cs.utexas.edu# Rick Strong 428839Sandreas.hansson@arm.com# Andreas Hansson 4312470Sglenn.bergmans@arm.com# Glenn Bergmans 444486Sbinkertn@umich.edu 456654Snate@binkert.orgimport sys 466654Snate@binkert.org 4711988Sandreas.sandberg@arm.comfrom m5.SimObject import * 486654Snate@binkert.orgfrom m5.defines import buildEnv 493102SN/Afrom m5.params import * 503102SN/Afrom m5.proxy import * 5112470Sglenn.bergmans@arm.comfrom m5.util.fdthelper import * 526654Snate@binkert.org 5310720Sandreas.hansson@arm.comfrom XBar import L2XBar 544776Sgblack@eecs.umich.edufrom InstTracer import InstTracer 5510663SAli.Saidi@ARM.comfrom CPUTracers import ExeTracer 566654Snate@binkert.orgfrom MemObject import MemObject 5712470Sglenn.bergmans@arm.comfrom SubSystem import SubSystem 589793Sakash.bagdia@arm.comfrom ClockDomain import * 5912470Sglenn.bergmans@arm.comfrom Platform import Platform 602667SN/A 614776Sgblack@eecs.umich.edudefault_tracer = ExeTracer() 624776Sgblack@eecs.umich.edu 636654Snate@binkert.orgif buildEnv['TARGET_ISA'] == 'alpha': 6412434Sgabeblack@google.com from AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB 658745Sgblack@eecs.umich.edu from AlphaInterrupts import AlphaInterrupts 669384SAndreas.Sandberg@arm.com from AlphaISA import AlphaISA 6712325Sandreas.sandberg@arm.com default_isa_class = AlphaISA 686654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'sparc': 6912434Sgabeblack@google.com from SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB 708745Sgblack@eecs.umich.edu from SparcInterrupts import SparcInterrupts 719384SAndreas.Sandberg@arm.com from SparcISA import SparcISA 7212325Sandreas.sandberg@arm.com default_isa_class = SparcISA 736654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'x86': 7412434Sgabeblack@google.com from X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB 758745Sgblack@eecs.umich.edu from X86LocalApic import X86LocalApic 769384SAndreas.Sandberg@arm.com from X86ISA import X86ISA 7712325Sandreas.sandberg@arm.com default_isa_class = X86ISA 786654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'mips': 7912434Sgabeblack@google.com from MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB 808745Sgblack@eecs.umich.edu from MipsInterrupts import MipsInterrupts 819384SAndreas.Sandberg@arm.com from MipsISA import MipsISA 8212325Sandreas.sandberg@arm.com default_isa_class = MipsISA 836654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'arm': 8412434Sgabeblack@google.com from ArmTLB import ArmTLB as ArchDTB, ArmTLB as ArchITB 8512434Sgabeblack@google.com from ArmTLB import ArmStage2IMMU, ArmStage2DMMU 868745Sgblack@eecs.umich.edu from ArmInterrupts import ArmInterrupts 879384SAndreas.Sandberg@arm.com from ArmISA import ArmISA 8812325Sandreas.sandberg@arm.com default_isa_class = ArmISA 896691Stjones1@inf.ed.ac.ukelif buildEnv['TARGET_ISA'] == 'power': 9012434Sgabeblack@google.com from PowerTLB import PowerTLB as ArchDTB, PowerTLB as ArchITB 918745Sgblack@eecs.umich.edu from PowerInterrupts import PowerInterrupts 929384SAndreas.Sandberg@arm.com from PowerISA import PowerISA 9312325Sandreas.sandberg@arm.com default_isa_class = PowerISA 9411723Sar4jc@virginia.eduelif buildEnv['TARGET_ISA'] == 'riscv': 9512434Sgabeblack@google.com from RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB 9611723Sar4jc@virginia.edu from RiscvInterrupts import RiscvInterrupts 9711723Sar4jc@virginia.edu from RiscvISA import RiscvISA 9812325Sandreas.sandberg@arm.com default_isa_class = RiscvISA 994486Sbinkertn@umich.edu 1005529Snate@binkert.orgclass BaseCPU(MemObject): 1011366SN/A type = 'BaseCPU' 1021310SN/A abstract = True 1039338SAndreas.Sandberg@arm.com cxx_header = "cpu/base.hh" 1049254SAndreas.Sandberg@arm.com 10511988Sandreas.sandberg@arm.com cxx_exports = [ 10611988Sandreas.sandberg@arm.com PyBindMethod("switchOut"), 10711988Sandreas.sandberg@arm.com PyBindMethod("takeOverFrom"), 10811988Sandreas.sandberg@arm.com PyBindMethod("switchedOut"), 10911988Sandreas.sandberg@arm.com PyBindMethod("flushTLBs"), 11011988Sandreas.sandberg@arm.com PyBindMethod("totalInsts"), 11111988Sandreas.sandberg@arm.com PyBindMethod("scheduleInstStop"), 11211988Sandreas.sandberg@arm.com PyBindMethod("scheduleLoadStop"), 11311988Sandreas.sandberg@arm.com PyBindMethod("getCurrentInstCount"), 11411988Sandreas.sandberg@arm.com ] 1159254SAndreas.Sandberg@arm.com 1169518SAndreas.Sandberg@ARM.com @classmethod 1179518SAndreas.Sandberg@ARM.com def memory_mode(cls): 1189518SAndreas.Sandberg@ARM.com """Which memory mode does this CPU require?""" 1199518SAndreas.Sandberg@ARM.com return 'invalid' 1209518SAndreas.Sandberg@ARM.com 1219518SAndreas.Sandberg@ARM.com @classmethod 1229518SAndreas.Sandberg@ARM.com def require_caches(cls): 1239518SAndreas.Sandberg@ARM.com """Does the CPU model require caches? 1249518SAndreas.Sandberg@ARM.com 1259518SAndreas.Sandberg@ARM.com Some CPU models might make assumptions that require them to 1269518SAndreas.Sandberg@ARM.com have caches. 1279518SAndreas.Sandberg@ARM.com """ 1289518SAndreas.Sandberg@ARM.com return False 1299518SAndreas.Sandberg@ARM.com 1309518SAndreas.Sandberg@ARM.com @classmethod 1319518SAndreas.Sandberg@ARM.com def support_take_over(cls): 1329518SAndreas.Sandberg@ARM.com """Does the CPU model support CPU takeOverFrom?""" 1339518SAndreas.Sandberg@ARM.com return False 1349518SAndreas.Sandberg@ARM.com 1359254SAndreas.Sandberg@arm.com def takeOverFrom(self, old_cpu): 1369254SAndreas.Sandberg@arm.com self._ccObject.takeOverFrom(old_cpu._ccObject) 1379254SAndreas.Sandberg@arm.com 1389254SAndreas.Sandberg@arm.com 1392901SN/A system = Param.System(Parent.any, "system object") 1405712Shsul@eecs.umich.edu cpu_id = Param.Int(-1, "CPU identifier") 14110190Sakash.bagdia@arm.com socket_id = Param.Unsigned(0, "Physical Socket identifier") 1425529Snate@binkert.org numThreads = Param.Unsigned(1, "number of HW thread contexts") 14312276Sanouk.vanlaer@arm.com pwr_gating_latency = Param.Cycles(300, 14412276Sanouk.vanlaer@arm.com "Latency to enter power gating state when all contexts are suspended") 1455529Snate@binkert.org 14612277Sjose.marinho@arm.com power_gating_on_idle = Param.Bool(False, "Control whether the core goes "\ 14712277Sjose.marinho@arm.com "to the OFF power state after all thread are disabled for "\ 14812277Sjose.marinho@arm.com "pwr_gating_latency cycles") 14912277Sjose.marinho@arm.com 1505529Snate@binkert.org function_trace = Param.Bool(False, "Enable function trace") 1519161Sandreas.hansson@arm.com function_trace_start = Param.Tick(0, "Tick to start function trace") 1525529Snate@binkert.org 1535821Ssaidi@eecs.umich.edu checker = Param.BaseCPU(NULL, "checker CPU") 1543170SN/A 15511877Sbrandon.potter@amd.com syscallRetryLatency = Param.Cycles(10000, "Cycles to wait until retry") 15611877Sbrandon.potter@amd.com 1575780Ssteve.reinhardt@amd.com do_checkpoint_insts = Param.Bool(True, 1585780Ssteve.reinhardt@amd.com "enable checkpoint pseudo instructions") 1595780Ssteve.reinhardt@amd.com do_statistics_insts = Param.Bool(True, 1605780Ssteve.reinhardt@amd.com "enable statistics pseudo instructions") 1615780Ssteve.reinhardt@amd.com 1628784Sgblack@eecs.umich.edu profile = Param.Latency('0ns', "trace the kernel stack") 1638784Sgblack@eecs.umich.edu do_quiesce = Param.Bool(True, "enable quiesce instructions") 1648784Sgblack@eecs.umich.edu 16512122Sjose.marinho@arm.com wait_for_remote_gdb = Param.Bool(False, 16612122Sjose.marinho@arm.com "Wait for a remote GDB connection"); 16712122Sjose.marinho@arm.com 1688793Sgblack@eecs.umich.edu workload = VectorParam.Process([], "processes to run") 1691310SN/A 17012434Sgabeblack@google.com dtb = Param.BaseTLB(ArchDTB(), "Data TLB") 17112434Sgabeblack@google.com itb = Param.BaseTLB(ArchITB(), "Instruction TLB") 1726654Snate@binkert.org if buildEnv['TARGET_ISA'] == 'sparc': 17311150Smitch.hayenga@arm.com interrupts = VectorParam.SparcInterrupts( 17411150Smitch.hayenga@arm.com [], "Interrupt Controller") 17512325Sandreas.sandberg@arm.com isa = VectorParam.SparcISA([], "ISA instance") 1766654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'alpha': 17711150Smitch.hayenga@arm.com interrupts = VectorParam.AlphaInterrupts( 17811150Smitch.hayenga@arm.com [], "Interrupt Controller") 17912325Sandreas.sandberg@arm.com isa = VectorParam.AlphaISA([], "ISA instance") 1806654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'x86': 18111150Smitch.hayenga@arm.com interrupts = VectorParam.X86LocalApic([], "Interrupt Controller") 18212325Sandreas.sandberg@arm.com isa = VectorParam.X86ISA([], "ISA instance") 1836654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'mips': 18411150Smitch.hayenga@arm.com interrupts = VectorParam.MipsInterrupts( 18511150Smitch.hayenga@arm.com [], "Interrupt Controller") 18612325Sandreas.sandberg@arm.com isa = VectorParam.MipsISA([], "ISA instance") 1876654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'arm': 18810037SARM gem5 Developers istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans") 18910037SARM gem5 Developers dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans") 19011150Smitch.hayenga@arm.com interrupts = VectorParam.ArmInterrupts( 19111150Smitch.hayenga@arm.com [], "Interrupt Controller") 19212325Sandreas.sandberg@arm.com isa = VectorParam.ArmISA([], "ISA instance") 1936691Stjones1@inf.ed.ac.uk elif buildEnv['TARGET_ISA'] == 'power': 1946691Stjones1@inf.ed.ac.uk UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 19511150Smitch.hayenga@arm.com interrupts = VectorParam.PowerInterrupts( 19611150Smitch.hayenga@arm.com [], "Interrupt Controller") 19712325Sandreas.sandberg@arm.com isa = VectorParam.PowerISA([], "ISA instance") 19811723Sar4jc@virginia.edu elif buildEnv['TARGET_ISA'] == 'riscv': 19911723Sar4jc@virginia.edu interrupts = VectorParam.RiscvInterrupts( 20011723Sar4jc@virginia.edu [], "Interrupt Controller") 20112325Sandreas.sandberg@arm.com isa = VectorParam.RiscvISA([], "ISA instance") 2024997Sgblack@eecs.umich.edu else: 2034997Sgblack@eecs.umich.edu print "Don't know what TLB to use for ISA %s" % \ 2046654Snate@binkert.org buildEnv['TARGET_ISA'] 2054997Sgblack@eecs.umich.edu sys.exit(1) 2064997Sgblack@eecs.umich.edu 2071310SN/A max_insts_all_threads = Param.Counter(0, 2081310SN/A "terminate when all threads have reached this inst count") 2091310SN/A max_insts_any_thread = Param.Counter(0, 2101310SN/A "terminate when any thread reaches this inst count") 2119647Sdam.sunwoo@arm.com simpoint_start_insts = VectorParam.Counter([], 2129647Sdam.sunwoo@arm.com "starting instruction counts of simpoints") 2131310SN/A max_loads_all_threads = Param.Counter(0, 2141310SN/A "terminate when all threads have reached this load count") 2151310SN/A max_loads_any_thread = Param.Counter(0, 2161310SN/A "terminate when any thread reaches this load count") 2179180Sandreas.hansson@arm.com progress_interval = Param.Frequency('0Hz', 2189180Sandreas.hansson@arm.com "frequency to print out the progress message") 2191310SN/A 2209433SAndreas.Sandberg@ARM.com switched_out = Param.Bool(False, 2219433SAndreas.Sandberg@ARM.com "Leave the CPU switched out after startup (used when switching " \ 2229433SAndreas.Sandberg@ARM.com "between CPU models)") 2231634SN/A 2244776Sgblack@eecs.umich.edu tracer = Param.InstTracer(default_tracer, "Instruction tracer") 2254776Sgblack@eecs.umich.edu 2268839Sandreas.hansson@arm.com icache_port = MasterPort("Instruction Port") 2278839Sandreas.hansson@arm.com dcache_port = MasterPort("Data Port") 2288707Sandreas.hansson@arm.com _cached_ports = ['icache_port', 'dcache_port'] 2298707Sandreas.hansson@arm.com 2308756Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 2318707Sandreas.hansson@arm.com _cached_ports += ["itb.walker.port", "dtb.walker.port"] 2327876Sgblack@eecs.umich.edu 2338839Sandreas.hansson@arm.com _uncached_slave_ports = [] 2348839Sandreas.hansson@arm.com _uncached_master_ports = [] 2358745Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'x86': 23611150Smitch.hayenga@arm.com _uncached_slave_ports += ["interrupts[0].pio", 23711150Smitch.hayenga@arm.com "interrupts[0].int_slave"] 23811150Smitch.hayenga@arm.com _uncached_master_ports += ["interrupts[0].int_master"] 2392998SN/A 2408863Snilay@cs.wisc.edu def createInterruptController(self): 2418863Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] == 'sparc': 24211150Smitch.hayenga@arm.com self.interrupts = [SparcInterrupts() for i in xrange(self.numThreads)] 2438863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'alpha': 24411150Smitch.hayenga@arm.com self.interrupts = [AlphaInterrupts() for i in xrange(self.numThreads)] 2458863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'x86': 2469793Sakash.bagdia@arm.com self.apic_clk_domain = DerivedClockDomain(clk_domain = 2479793Sakash.bagdia@arm.com Parent.clk_domain, 2489793Sakash.bagdia@arm.com clk_divider = 16) 24911150Smitch.hayenga@arm.com self.interrupts = [X86LocalApic(clk_domain = self.apic_clk_domain, 2509544Sandreas.hansson@arm.com pio_addr=0x2000000000000000) 25111150Smitch.hayenga@arm.com for i in xrange(self.numThreads)] 2529544Sandreas.hansson@arm.com _localApic = self.interrupts 2538863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'mips': 25411150Smitch.hayenga@arm.com self.interrupts = [MipsInterrupts() for i in xrange(self.numThreads)] 2558863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'arm': 25611150Smitch.hayenga@arm.com self.interrupts = [ArmInterrupts() for i in xrange(self.numThreads)] 2578863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'power': 25811150Smitch.hayenga@arm.com self.interrupts = [PowerInterrupts() for i in xrange(self.numThreads)] 25911723Sar4jc@virginia.edu elif buildEnv['TARGET_ISA'] == 'riscv': 26011723Sar4jc@virginia.edu self.interrupts = \ 26111723Sar4jc@virginia.edu [RiscvInterrupts() for i in xrange(self.numThreads)] 2628863Snilay@cs.wisc.edu else: 2638863Snilay@cs.wisc.edu print "Don't know what Interrupt Controller to use for ISA %s" % \ 2648863Snilay@cs.wisc.edu buildEnv['TARGET_ISA'] 2658863Snilay@cs.wisc.edu sys.exit(1) 2668863Snilay@cs.wisc.edu 2677876Sgblack@eecs.umich.edu def connectCachedPorts(self, bus): 2687876Sgblack@eecs.umich.edu for p in self._cached_ports: 2698839Sandreas.hansson@arm.com exec('self.%s = bus.slave' % p) 2707404SAli.Saidi@ARM.com 2717876Sgblack@eecs.umich.edu def connectUncachedPorts(self, bus): 2728839Sandreas.hansson@arm.com for p in self._uncached_slave_ports: 2738839Sandreas.hansson@arm.com exec('self.%s = bus.master' % p) 2748839Sandreas.hansson@arm.com for p in self._uncached_master_ports: 2758839Sandreas.hansson@arm.com exec('self.%s = bus.slave' % p) 2767876Sgblack@eecs.umich.edu 2777876Sgblack@eecs.umich.edu def connectAllPorts(self, cached_bus, uncached_bus = None): 2787876Sgblack@eecs.umich.edu self.connectCachedPorts(cached_bus) 2797876Sgblack@eecs.umich.edu if not uncached_bus: 2807876Sgblack@eecs.umich.edu uncached_bus = cached_bus 2817876Sgblack@eecs.umich.edu self.connectUncachedPorts(uncached_bus) 2822998SN/A 2837868Sgblack@eecs.umich.edu def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 2842998SN/A self.icache = ic 2852998SN/A self.dcache = dc 2862998SN/A self.icache_port = ic.cpu_side 2872998SN/A self.dcache_port = dc.cpu_side 2887876Sgblack@eecs.umich.edu self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 2898796Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 2908796Sgblack@eecs.umich.edu if iwc and dwc: 2918796Sgblack@eecs.umich.edu self.itb_walker_cache = iwc 2928796Sgblack@eecs.umich.edu self.dtb_walker_cache = dwc 29310717Sandreas.hansson@arm.com self.itb.walker.port = iwc.cpu_side 29410717Sandreas.hansson@arm.com self.dtb.walker.port = dwc.cpu_side 2958796Sgblack@eecs.umich.edu self._cached_ports += ["itb_walker_cache.mem_side", \ 2968796Sgblack@eecs.umich.edu "dtb_walker_cache.mem_side"] 2978796Sgblack@eecs.umich.edu else: 2988796Sgblack@eecs.umich.edu self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 2998887Sgeoffrey.blake@arm.com 3008809Sgblack@eecs.umich.edu # Checker doesn't need its own tlb caches because it does 3018809Sgblack@eecs.umich.edu # functional accesses only 3028887Sgeoffrey.blake@arm.com if self.checker != NULL: 3038809Sgblack@eecs.umich.edu self._cached_ports += ["checker.itb.walker.port", \ 3048809Sgblack@eecs.umich.edu "checker.dtb.walker.port"] 3052998SN/A 30612440Sxiaoyuma@google.com def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc=None, dwc=None, 30712440Sxiaoyuma@google.com xbar=None): 3087868Sgblack@eecs.umich.edu self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 30912440Sxiaoyuma@google.com self.toL2Bus = xbar if xbar else L2XBar() 3107876Sgblack@eecs.umich.edu self.connectCachedPorts(self.toL2Bus) 3112998SN/A self.l2cache = l2c 3128839Sandreas.hansson@arm.com self.toL2Bus.master = self.l2cache.cpu_side 3137876Sgblack@eecs.umich.edu self._cached_ports = ['l2cache.mem_side'] 3148887Sgeoffrey.blake@arm.com 3159384SAndreas.Sandberg@arm.com def createThreads(self): 31612325Sandreas.sandberg@arm.com # If no ISAs have been created, assume that the user wants the 31712325Sandreas.sandberg@arm.com # default ISA. 31812325Sandreas.sandberg@arm.com if len(self.isa) == 0: 31912325Sandreas.sandberg@arm.com self.isa = [ default_isa_class() for i in xrange(self.numThreads) ] 32012325Sandreas.sandberg@arm.com else: 32112325Sandreas.sandberg@arm.com if len(self.isa) != int(self.numThreads): 32212325Sandreas.sandberg@arm.com raise RuntimeError("Number of ISA instances doesn't " 32312325Sandreas.sandberg@arm.com "match thread count") 3249384SAndreas.Sandberg@arm.com if self.checker != NULL: 3259384SAndreas.Sandberg@arm.com self.checker.createThreads() 3269384SAndreas.Sandberg@arm.com 3278887Sgeoffrey.blake@arm.com def addCheckerCpu(self): 3288887Sgeoffrey.blake@arm.com pass 32912470Sglenn.bergmans@arm.com 33012470Sglenn.bergmans@arm.com def createPhandleKey(self, thread): 33112470Sglenn.bergmans@arm.com # This method creates a unique key for this cpu as a function of a 33212470Sglenn.bergmans@arm.com # certain thread 33312470Sglenn.bergmans@arm.com return 'CPU-%d-%d-%d' % (self.socket_id, self.cpu_id, thread) 33412470Sglenn.bergmans@arm.com 33512470Sglenn.bergmans@arm.com #Generate simple CPU Device Tree structure 33612470Sglenn.bergmans@arm.com def generateDeviceTree(self, state): 33712470Sglenn.bergmans@arm.com """Generate cpu nodes for each thread and the corresponding part of the 33812470Sglenn.bergmans@arm.com cpu-map node. Note that this implementation does not support clusters 33912470Sglenn.bergmans@arm.com of clusters. Note that GEM5 is not compatible with the official way of 34012470Sglenn.bergmans@arm.com numbering cores as defined in the Device Tree documentation. Where the 34112470Sglenn.bergmans@arm.com cpu_id needs to reset to 0 for each cluster by specification, GEM5 34212470Sglenn.bergmans@arm.com expects the cpu_id to be globally unique and incremental. This 34312470Sglenn.bergmans@arm.com generated node adheres the GEM5 way of doing things.""" 34412470Sglenn.bergmans@arm.com if bool(self.switched_out): 34512470Sglenn.bergmans@arm.com return 34612470Sglenn.bergmans@arm.com 34712470Sglenn.bergmans@arm.com cpus_node = FdtNode('cpus') 34812470Sglenn.bergmans@arm.com cpus_node.append(state.CPUCellsProperty()) 34912470Sglenn.bergmans@arm.com #Special size override of 0 35012470Sglenn.bergmans@arm.com cpus_node.append(FdtPropertyWords('#size-cells', [0])) 35112470Sglenn.bergmans@arm.com 35212470Sglenn.bergmans@arm.com # Generate cpu nodes 35312470Sglenn.bergmans@arm.com for i in range(int(self.numThreads)): 35412470Sglenn.bergmans@arm.com reg = (int(self.socket_id)<<8) + int(self.cpu_id) + i 35512470Sglenn.bergmans@arm.com node = FdtNode("cpu@%x" % reg) 35612470Sglenn.bergmans@arm.com node.append(FdtPropertyStrings("device_type", "cpu")) 35712470Sglenn.bergmans@arm.com node.appendCompatible(["gem5,arm-cpu"]) 35812470Sglenn.bergmans@arm.com node.append(FdtPropertyWords("reg", state.CPUAddrCells(reg))) 35912470Sglenn.bergmans@arm.com platform, found = self.system.unproxy(self).find_any(Platform) 36012470Sglenn.bergmans@arm.com if found: 36112470Sglenn.bergmans@arm.com platform.annotateCpuDeviceNode(node, state) 36212470Sglenn.bergmans@arm.com else: 36312470Sglenn.bergmans@arm.com warn("Platform not found for device tree generation; " \ 36412470Sglenn.bergmans@arm.com "system or multiple CPUs may not start") 36512470Sglenn.bergmans@arm.com 36612470Sglenn.bergmans@arm.com freq = round(self.clk_domain.unproxy(self).clock[0].frequency) 36712470Sglenn.bergmans@arm.com node.append(FdtPropertyWords("clock-frequency", freq)) 36812470Sglenn.bergmans@arm.com 36912470Sglenn.bergmans@arm.com # Unique key for this CPU 37012470Sglenn.bergmans@arm.com phandle_key = self.createPhandleKey(i) 37112470Sglenn.bergmans@arm.com node.appendPhandle(phandle_key) 37212470Sglenn.bergmans@arm.com cpus_node.append(node) 37312470Sglenn.bergmans@arm.com 37412470Sglenn.bergmans@arm.com yield cpus_node 375