BaseCPU.py revision 12434
15335Shines@cs.fsu.edu# Copyright (c) 2012-2013, 2015-2017 ARM Limited 27897Shestness@cs.utexas.edu# All rights reserved. 34486Sbinkertn@umich.edu# 44486Sbinkertn@umich.edu# The license below extends only to copyright in the software and shall 54486Sbinkertn@umich.edu# not be construed as granting a license to any other intellectual 64486Sbinkertn@umich.edu# property including but not limited to intellectual property relating 74486Sbinkertn@umich.edu# to a hardware implementation of the functionality of the software 84486Sbinkertn@umich.edu# licensed hereunder. You may use the software subject to the license 94486Sbinkertn@umich.edu# terms below provided that you ensure that this notice is replicated 104486Sbinkertn@umich.edu# unmodified and in its entirety in all distributions of the software, 114486Sbinkertn@umich.edu# modified or unmodified, in source code or in binary form. 124486Sbinkertn@umich.edu# 134486Sbinkertn@umich.edu# Copyright (c) 2005-2008 The Regents of The University of Michigan 144486Sbinkertn@umich.edu# Copyright (c) 2011 Regents of the University of California 154486Sbinkertn@umich.edu# All rights reserved. 164486Sbinkertn@umich.edu# 174486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 184486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 194486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 204486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 214486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 224486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 234486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 244486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 254486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 264486Sbinkertn@umich.edu# this software without specific prior written permission. 274486Sbinkertn@umich.edu# 284486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 297897Shestness@cs.utexas.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316654Snate@binkert.org# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326654Snate@binkert.org# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336654Snate@binkert.org# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 343102SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 353102SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366654Snate@binkert.org# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372998SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 384776Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394776Sgblack@eecs.umich.edu# 406654Snate@binkert.org# Authors: Nathan Binkert 412667SN/A# Rick Strong 424776Sgblack@eecs.umich.edu# Andreas Hansson 434776Sgblack@eecs.umich.edu 446654Snate@binkert.orgimport sys 456023Snate@binkert.org 466654Snate@binkert.orgfrom m5.SimObject import * 475647Sgblack@eecs.umich.edufrom m5.defines import buildEnv 486654Snate@binkert.orgfrom m5.params import * 496022Sgblack@eecs.umich.edufrom m5.proxy import * 506654Snate@binkert.org 515647Sgblack@eecs.umich.edufrom XBar import L2XBar 526654Snate@binkert.orgfrom InstTracer import InstTracer 536022Sgblack@eecs.umich.edufrom CPUTracers import ExeTracer 546654Snate@binkert.orgfrom MemObject import MemObject 555647Sgblack@eecs.umich.edufrom ClockDomain import * 566654Snate@binkert.org 576022Sgblack@eecs.umich.edudefault_tracer = ExeTracer() 586654Snate@binkert.org 595647Sgblack@eecs.umich.eduif buildEnv['TARGET_ISA'] == 'alpha': 606654Snate@binkert.org from AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB 616116Snate@binkert.org from AlphaInterrupts import AlphaInterrupts 626654Snate@binkert.org from AlphaISA import AlphaISA 635647Sgblack@eecs.umich.edu default_isa_class = AlphaISA 646691Stjones1@inf.ed.ac.ukelif buildEnv['TARGET_ISA'] == 'sparc': 656691Stjones1@inf.ed.ac.uk from SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB 666691Stjones1@inf.ed.ac.uk from SparcInterrupts import SparcInterrupts 676691Stjones1@inf.ed.ac.uk from SparcISA import SparcISA 684486Sbinkertn@umich.edu default_isa_class = SparcISA 695529Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'x86': 701366SN/A from X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB 711310SN/A from X86LocalApic import X86LocalApic 721310SN/A from X86ISA import X86ISA 732901SN/A default_isa_class = X86ISA 745712Shsul@eecs.umich.eduelif buildEnv['TARGET_ISA'] == 'mips': 755529Snate@binkert.org from MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB 765529Snate@binkert.org from MipsInterrupts import MipsInterrupts 775529Snate@binkert.org from MipsISA import MipsISA 785529Snate@binkert.org default_isa_class = MipsISA 795529Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'arm': 805821Ssaidi@eecs.umich.edu from ArmTLB import ArmTLB as ArchDTB, ArmTLB as ArchITB 813170SN/A from ArmTLB import ArmStage2IMMU, ArmStage2DMMU 825780Ssteve.reinhardt@amd.com from ArmInterrupts import ArmInterrupts 835780Ssteve.reinhardt@amd.com from ArmISA import ArmISA 845780Ssteve.reinhardt@amd.com default_isa_class = ArmISA 855780Ssteve.reinhardt@amd.comelif buildEnv['TARGET_ISA'] == 'power': 865780Ssteve.reinhardt@amd.com from PowerTLB import PowerTLB as ArchDTB, PowerTLB as ArchITB 876654Snate@binkert.org from PowerInterrupts import PowerInterrupts 885529Snate@binkert.org from PowerISA import PowerISA 893620SN/A default_isa_class = PowerISA 901445SN/Aelif buildEnv['TARGET_ISA'] == 'riscv': 911445SN/A from RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB 921310SN/A from RiscvInterrupts import RiscvInterrupts 936654Snate@binkert.org from RiscvISA import RiscvISA 946022Sgblack@eecs.umich.edu default_isa_class = RiscvISA 956022Sgblack@eecs.umich.edu 966654Snate@binkert.orgclass BaseCPU(MemObject): 975647Sgblack@eecs.umich.edu type = 'BaseCPU' 985647Sgblack@eecs.umich.edu abstract = True 996654Snate@binkert.org cxx_header = "cpu/base.hh" 1006023Snate@binkert.org 1016023Snate@binkert.org cxx_exports = [ 1026654Snate@binkert.org PyBindMethod("switchOut"), 1035647Sgblack@eecs.umich.edu PyBindMethod("takeOverFrom"), 1045647Sgblack@eecs.umich.edu PyBindMethod("switchedOut"), 1056654Snate@binkert.org PyBindMethod("flushTLBs"), 1066022Sgblack@eecs.umich.edu PyBindMethod("totalInsts"), 1076022Sgblack@eecs.umich.edu PyBindMethod("scheduleInstStop"), 1086654Snate@binkert.org PyBindMethod("scheduleLoadStop"), 1095658Sgblack@eecs.umich.edu PyBindMethod("getCurrentInstCount"), 1105648Sgblack@eecs.umich.edu ] 1115648Sgblack@eecs.umich.edu 1126654Snate@binkert.org @classmethod 1136022Sgblack@eecs.umich.edu def memory_mode(cls): 1146022Sgblack@eecs.umich.edu """Which memory mode does this CPU require?""" 1156654Snate@binkert.org return 'invalid' 1165647Sgblack@eecs.umich.edu 1175647Sgblack@eecs.umich.edu @classmethod 1186654Snate@binkert.org def require_caches(cls): 1196116Snate@binkert.org """Does the CPU model require caches? 1206116Snate@binkert.org 1216654Snate@binkert.org Some CPU models might make assumptions that require them to 1225647Sgblack@eecs.umich.edu have caches. 1235647Sgblack@eecs.umich.edu """ 1246691Stjones1@inf.ed.ac.uk return False 1256691Stjones1@inf.ed.ac.uk 1266691Stjones1@inf.ed.ac.uk @classmethod 1276691Stjones1@inf.ed.ac.uk def support_take_over(cls): 1286691Stjones1@inf.ed.ac.uk """Does the CPU model support CPU takeOverFrom?""" 1296691Stjones1@inf.ed.ac.uk return False 1306691Stjones1@inf.ed.ac.uk 1314997Sgblack@eecs.umich.edu def takeOverFrom(self, old_cpu): 1324997Sgblack@eecs.umich.edu self._ccObject.takeOverFrom(old_cpu._ccObject) 1336654Snate@binkert.org 1344997Sgblack@eecs.umich.edu 1354997Sgblack@eecs.umich.edu system = Param.System(Parent.any, "system object") 1361310SN/A cpu_id = Param.Int(-1, "CPU identifier") 1371310SN/A socket_id = Param.Unsigned(0, "Physical Socket identifier") 1381310SN/A numThreads = Param.Unsigned(1, "number of HW thread contexts") 1391310SN/A pwr_gating_latency = Param.Cycles(300, 1401310SN/A "Latency to enter power gating state when all contexts are suspended") 1411310SN/A 1421310SN/A power_gating_on_idle = Param.Bool(False, "Control whether the core goes "\ 1431310SN/A "to the OFF power state after all thread are disabled for "\ 1443878SN/A "pwr_gating_latency cycles") 1453878SN/A 1461310SN/A function_trace = Param.Bool(False, "Enable function trace") 1471369SN/A function_trace_start = Param.Tick(0, "Tick to start function trace") 1481310SN/A 1491634SN/A checker = Param.BaseCPU(NULL, "checker CPU") 1504167SN/A 1514167SN/A syscallRetryLatency = Param.Cycles(10000, "Cycles to wait until retry") 1522998SN/A 1534776Sgblack@eecs.umich.edu do_checkpoint_insts = Param.Bool(True, 1544776Sgblack@eecs.umich.edu "enable checkpoint pseudo instructions") 1557876Sgblack@eecs.umich.edu do_statistics_insts = Param.Bool(True, 1567876Sgblack@eecs.umich.edu "enable statistics pseudo instructions") 1577876Sgblack@eecs.umich.edu 1587876Sgblack@eecs.umich.edu profile = Param.Latency('0ns', "trace the kernel stack") 1597876Sgblack@eecs.umich.edu do_quiesce = Param.Bool(True, "enable quiesce instructions") 1606654Snate@binkert.org 1617876Sgblack@eecs.umich.edu wait_for_remote_gdb = Param.Bool(False, 1622998SN/A "Wait for a remote GDB connection"); 1637876Sgblack@eecs.umich.edu 1647876Sgblack@eecs.umich.edu workload = VectorParam.Process([], "processes to run") 1657876Sgblack@eecs.umich.edu 1667404SAli.Saidi@ARM.com dtb = Param.BaseTLB(ArchDTB(), "Data TLB") 1677876Sgblack@eecs.umich.edu itb = Param.BaseTLB(ArchITB(), "Instruction TLB") 1687876Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'sparc': 1697876Sgblack@eecs.umich.edu interrupts = VectorParam.SparcInterrupts( 1707876Sgblack@eecs.umich.edu [], "Interrupt Controller") 1717876Sgblack@eecs.umich.edu isa = VectorParam.SparcISA([], "ISA instance") 1727876Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'alpha': 1737876Sgblack@eecs.umich.edu interrupts = VectorParam.AlphaInterrupts( 1747876Sgblack@eecs.umich.edu [], "Interrupt Controller") 1757876Sgblack@eecs.umich.edu isa = VectorParam.AlphaISA([], "ISA instance") 1762998SN/A elif buildEnv['TARGET_ISA'] == 'x86': 1777868Sgblack@eecs.umich.edu interrupts = VectorParam.X86LocalApic([], "Interrupt Controller") 1787876Sgblack@eecs.umich.edu isa = VectorParam.X86ISA([], "ISA instance") 1792998SN/A elif buildEnv['TARGET_ISA'] == 'mips': 1802998SN/A interrupts = VectorParam.MipsInterrupts( 1812998SN/A [], "Interrupt Controller") 1822998SN/A isa = VectorParam.MipsISA([], "ISA instance") 1837876Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'arm': 1847404SAli.Saidi@ARM.com istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans") 1857868Sgblack@eecs.umich.edu dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans") 1867868Sgblack@eecs.umich.edu interrupts = VectorParam.ArmInterrupts( 1877868Sgblack@eecs.umich.edu [], "Interrupt Controller") 1887868Sgblack@eecs.umich.edu isa = VectorParam.ArmISA([], "ISA instance") 1897868Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'power': 1907876Sgblack@eecs.umich.edu UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 1917876Sgblack@eecs.umich.edu interrupts = VectorParam.PowerInterrupts( 1927868Sgblack@eecs.umich.edu [], "Interrupt Controller") 1937876Sgblack@eecs.umich.edu isa = VectorParam.PowerISA([], "ISA instance") 1942998SN/A elif buildEnv['TARGET_ISA'] == 'riscv': 1957868Sgblack@eecs.umich.edu interrupts = VectorParam.RiscvInterrupts( 1967868Sgblack@eecs.umich.edu [], "Interrupt Controller") 1972998SN/A isa = VectorParam.RiscvISA([], "ISA instance") 1987876Sgblack@eecs.umich.edu else: 1992998SN/A print "Don't know what TLB to use for ISA %s" % \ 2003017SN/A buildEnv['TARGET_ISA'] 2017876Sgblack@eecs.umich.edu sys.exit(1) 2025222Sksewell@umich.edu 2036654Snate@binkert.org max_insts_all_threads = Param.Counter(0, 2045222Sksewell@umich.edu "terminate when all threads have reached this inst count") 2055222Sksewell@umich.edu max_insts_any_thread = Param.Counter(0, 2065222Sksewell@umich.edu "terminate when any thread reaches this inst count") 2075222Sksewell@umich.edu simpoint_start_insts = VectorParam.Counter([], 2085222Sksewell@umich.edu "starting instruction counts of simpoints") 2095222Sksewell@umich.edu max_loads_all_threads = Param.Counter(0, 2105222Sksewell@umich.edu "terminate when all threads have reached this load count") 2115222Sksewell@umich.edu max_loads_any_thread = Param.Counter(0, 2125222Sksewell@umich.edu "terminate when any thread reaches this load count") 2135222Sksewell@umich.edu progress_interval = Param.Frequency('0Hz', 2145222Sksewell@umich.edu "frequency to print out the progress message") 2155222Sksewell@umich.edu 2165222Sksewell@umich.edu switched_out = Param.Bool(False, 2175222Sksewell@umich.edu "Leave the CPU switched out after startup (used when switching " \ 2185222Sksewell@umich.edu "between CPU models)") 2195222Sksewell@umich.edu 2205222Sksewell@umich.edu tracer = Param.InstTracer(default_tracer, "Instruction tracer") 2215222Sksewell@umich.edu 2225222Sksewell@umich.edu icache_port = MasterPort("Instruction Port") 2235222Sksewell@umich.edu dcache_port = MasterPort("Data Port") 2245222Sksewell@umich.edu _cached_ports = ['icache_port', 'dcache_port'] 2255222Sksewell@umich.edu 2265222Sksewell@umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 2275222Sksewell@umich.edu _cached_ports += ["itb.walker.port", "dtb.walker.port"] 2285222Sksewell@umich.edu 2295222Sksewell@umich.edu _uncached_slave_ports = [] 2305222Sksewell@umich.edu _uncached_master_ports = [] 2315222Sksewell@umich.edu if buildEnv['TARGET_ISA'] == 'x86': 2325222Sksewell@umich.edu _uncached_slave_ports += ["interrupts[0].pio", 2335222Sksewell@umich.edu "interrupts[0].int_slave"] 2345222Sksewell@umich.edu _uncached_master_ports += ["interrupts[0].int_master"] 2355222Sksewell@umich.edu 2365222Sksewell@umich.edu def createInterruptController(self): 2375222Sksewell@umich.edu if buildEnv['TARGET_ISA'] == 'sparc': 2385222Sksewell@umich.edu self.interrupts = [SparcInterrupts() for i in xrange(self.numThreads)] 2395222Sksewell@umich.edu elif buildEnv['TARGET_ISA'] == 'alpha': 2405222Sksewell@umich.edu self.interrupts = [AlphaInterrupts() for i in xrange(self.numThreads)] 2415222Sksewell@umich.edu elif buildEnv['TARGET_ISA'] == 'x86': 2425222Sksewell@umich.edu self.apic_clk_domain = DerivedClockDomain(clk_domain = 2435222Sksewell@umich.edu Parent.clk_domain, 2445222Sksewell@umich.edu clk_divider = 16) 2455222Sksewell@umich.edu self.interrupts = [X86LocalApic(clk_domain = self.apic_clk_domain, 2465222Sksewell@umich.edu pio_addr=0x2000000000000000) 2475222Sksewell@umich.edu for i in xrange(self.numThreads)] 2485222Sksewell@umich.edu _localApic = self.interrupts 2495222Sksewell@umich.edu elif buildEnv['TARGET_ISA'] == 'mips': 2505222Sksewell@umich.edu self.interrupts = [MipsInterrupts() for i in xrange(self.numThreads)] 2515222Sksewell@umich.edu elif buildEnv['TARGET_ISA'] == 'arm': 2525222Sksewell@umich.edu self.interrupts = [ArmInterrupts() for i in xrange(self.numThreads)] 2535222Sksewell@umich.edu elif buildEnv['TARGET_ISA'] == 'power': 2545222Sksewell@umich.edu self.interrupts = [PowerInterrupts() for i in xrange(self.numThreads)] 2555222Sksewell@umich.edu elif buildEnv['TARGET_ISA'] == 'riscv': 2565222Sksewell@umich.edu self.interrupts = \ 2575222Sksewell@umich.edu [RiscvInterrupts() for i in xrange(self.numThreads)] 258 else: 259 print "Don't know what Interrupt Controller to use for ISA %s" % \ 260 buildEnv['TARGET_ISA'] 261 sys.exit(1) 262 263 def connectCachedPorts(self, bus): 264 for p in self._cached_ports: 265 exec('self.%s = bus.slave' % p) 266 267 def connectUncachedPorts(self, bus): 268 for p in self._uncached_slave_ports: 269 exec('self.%s = bus.master' % p) 270 for p in self._uncached_master_ports: 271 exec('self.%s = bus.slave' % p) 272 273 def connectAllPorts(self, cached_bus, uncached_bus = None): 274 self.connectCachedPorts(cached_bus) 275 if not uncached_bus: 276 uncached_bus = cached_bus 277 self.connectUncachedPorts(uncached_bus) 278 279 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 280 self.icache = ic 281 self.dcache = dc 282 self.icache_port = ic.cpu_side 283 self.dcache_port = dc.cpu_side 284 self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 285 if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 286 if iwc and dwc: 287 self.itb_walker_cache = iwc 288 self.dtb_walker_cache = dwc 289 self.itb.walker.port = iwc.cpu_side 290 self.dtb.walker.port = dwc.cpu_side 291 self._cached_ports += ["itb_walker_cache.mem_side", \ 292 "dtb_walker_cache.mem_side"] 293 else: 294 self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 295 296 # Checker doesn't need its own tlb caches because it does 297 # functional accesses only 298 if self.checker != NULL: 299 self._cached_ports += ["checker.itb.walker.port", \ 300 "checker.dtb.walker.port"] 301 302 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 303 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 304 self.toL2Bus = L2XBar() 305 self.connectCachedPorts(self.toL2Bus) 306 self.l2cache = l2c 307 self.toL2Bus.master = self.l2cache.cpu_side 308 self._cached_ports = ['l2cache.mem_side'] 309 310 def createThreads(self): 311 # If no ISAs have been created, assume that the user wants the 312 # default ISA. 313 if len(self.isa) == 0: 314 self.isa = [ default_isa_class() for i in xrange(self.numThreads) ] 315 else: 316 if len(self.isa) != int(self.numThreads): 317 raise RuntimeError("Number of ISA instances doesn't " 318 "match thread count") 319 if self.checker != NULL: 320 self.checker.createThreads() 321 322 def addCheckerCpu(self): 323 pass 324