BaseCPU.py revision 12277
12348SN/A# Copyright (c) 2012-2013, 2015-2017 ARM Limited 22348SN/A# All rights reserved. 32348SN/A# 42348SN/A# The license below extends only to copyright in the software and shall 52348SN/A# not be construed as granting a license to any other intellectual 62348SN/A# property including but not limited to intellectual property relating 72348SN/A# to a hardware implementation of the functionality of the software 82348SN/A# licensed hereunder. You may use the software subject to the license 92348SN/A# terms below provided that you ensure that this notice is replicated 102348SN/A# unmodified and in its entirety in all distributions of the software, 112348SN/A# modified or unmodified, in source code or in binary form. 122348SN/A# 132348SN/A# Copyright (c) 2005-2008 The Regents of The University of Michigan 142348SN/A# Copyright (c) 2011 Regents of the University of California 152348SN/A# All rights reserved. 162348SN/A# 172348SN/A# Redistribution and use in source and binary forms, with or without 182348SN/A# modification, are permitted provided that the following conditions are 192348SN/A# met: redistributions of source code must retain the above copyright 202348SN/A# notice, this list of conditions and the following disclaimer; 212348SN/A# redistributions in binary form must reproduce the above copyright 222348SN/A# notice, this list of conditions and the following disclaimer in the 232348SN/A# documentation and/or other materials provided with the distribution; 242348SN/A# neither the name of the copyright holders nor the names of its 252348SN/A# contributors may be used to endorse or promote products derived from 262348SN/A# this software without specific prior written permission. 272689Sktlim@umich.edu# 282689Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292348SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302325SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312325SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322325SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332325SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 348229Snate@binkert.org# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 357813Ssteve.reinhardt@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362325SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372348SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382348SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392348SN/A# 402348SN/A# Authors: Nathan Binkert 412348SN/A# Rick Strong 422348SN/A# Andreas Hansson 432348SN/A 442348SN/Aimport sys 452348SN/A 462348SN/Afrom m5.SimObject import * 472348SN/Afrom m5.defines import buildEnv 482348SN/Afrom m5.params import * 492348SN/Afrom m5.proxy import * 502348SN/A 512348SN/Afrom XBar import L2XBar 525804Snate@binkert.orgfrom InstTracer import InstTracer 535804Snate@binkert.orgfrom CPUTracers import ExeTracer 542325SN/Afrom MemObject import MemObject 555804Snate@binkert.orgfrom ClockDomain import * 565804Snate@binkert.org 579086Sandreas.hansson@arm.comdefault_tracer = ExeTracer() 582325SN/A 592325SN/Aif buildEnv['TARGET_ISA'] == 'alpha': 602325SN/A from AlphaTLB import AlphaDTB, AlphaITB 612348SN/A from AlphaInterrupts import AlphaInterrupts 622348SN/A from AlphaISA import AlphaISA 632348SN/A isa_class = AlphaISA 642348SN/Aelif buildEnv['TARGET_ISA'] == 'sparc': 652325SN/A from SparcTLB import SparcTLB 662325SN/A from SparcInterrupts import SparcInterrupts 672348SN/A from SparcISA import SparcISA 682325SN/A isa_class = SparcISA 692325SN/Aelif buildEnv['TARGET_ISA'] == 'x86': 702348SN/A from X86TLB import X86TLB 712325SN/A from X86LocalApic import X86LocalApic 722325SN/A from X86ISA import X86ISA 732325SN/A isa_class = X86ISA 742348SN/Aelif buildEnv['TARGET_ISA'] == 'mips': 752325SN/A from MipsTLB import MipsTLB 762325SN/A from MipsInterrupts import MipsInterrupts 772348SN/A from MipsISA import MipsISA 782348SN/A isa_class = MipsISA 792348SN/Aelif buildEnv['TARGET_ISA'] == 'arm': 802325SN/A from ArmTLB import ArmTLB, ArmStage2IMMU, ArmStage2DMMU 812325SN/A from ArmInterrupts import ArmInterrupts 822325SN/A from ArmISA import ArmISA 832348SN/A isa_class = ArmISA 842325SN/Aelif buildEnv['TARGET_ISA'] == 'power': 852325SN/A from PowerTLB import PowerTLB 862348SN/A from PowerInterrupts import PowerInterrupts 872325SN/A from PowerISA import PowerISA 882325SN/A isa_class = PowerISA 892348SN/Aelif buildEnv['TARGET_ISA'] == 'riscv': 902325SN/A from RiscvTLB import RiscvTLB 912325SN/A from RiscvInterrupts import RiscvInterrupts 922348SN/A from RiscvISA import RiscvISA 932348SN/A isa_class = RiscvISA 942348SN/A 952325SN/Aclass BaseCPU(MemObject): 962325SN/A type = 'BaseCPU' 972325SN/A abstract = True 985804Snate@binkert.org cxx_header = "cpu/base.hh" 995804Snate@binkert.org 1005804Snate@binkert.org cxx_exports = [ 1015804Snate@binkert.org PyBindMethod("switchOut"), 1022325SN/A PyBindMethod("takeOverFrom"), 1032325SN/A PyBindMethod("switchedOut"), 1042325SN/A PyBindMethod("flushTLBs"), 1052325SN/A PyBindMethod("totalInsts"), 1062325SN/A PyBindMethod("scheduleInstStop"), 1072325SN/A PyBindMethod("scheduleLoadStop"), 1082325SN/A PyBindMethod("getCurrentInstCount"), 1092325SN/A ] 1102325SN/A 1112325SN/A @classmethod 1122348SN/A def memory_mode(cls): 1132325SN/A """Which memory mode does this CPU require?""" 1142325SN/A return 'invalid' 1152325SN/A 1162325SN/A @classmethod 1172325SN/A def require_caches(cls): 1182325SN/A """Does the CPU model require caches? 1192325SN/A 1202325SN/A Some CPU models might make assumptions that require them to 1212325SN/A have caches. 1222325SN/A """ 1232325SN/A return False 1242325SN/A 1252325SN/A @classmethod 1262348SN/A def support_take_over(cls): 1272325SN/A """Does the CPU model support CPU takeOverFrom?""" 1282325SN/A return False 1292325SN/A 1302325SN/A def takeOverFrom(self, old_cpu): 1312325SN/A self._ccObject.takeOverFrom(old_cpu._ccObject) 1322325SN/A 1332325SN/A 134 system = Param.System(Parent.any, "system object") 135 cpu_id = Param.Int(-1, "CPU identifier") 136 socket_id = Param.Unsigned(0, "Physical Socket identifier") 137 numThreads = Param.Unsigned(1, "number of HW thread contexts") 138 pwr_gating_latency = Param.Cycles(300, 139 "Latency to enter power gating state when all contexts are suspended") 140 141 power_gating_on_idle = Param.Bool(False, "Control whether the core goes "\ 142 "to the OFF power state after all thread are disabled for "\ 143 "pwr_gating_latency cycles") 144 145 function_trace = Param.Bool(False, "Enable function trace") 146 function_trace_start = Param.Tick(0, "Tick to start function trace") 147 148 checker = Param.BaseCPU(NULL, "checker CPU") 149 150 syscallRetryLatency = Param.Cycles(10000, "Cycles to wait until retry") 151 152 do_checkpoint_insts = Param.Bool(True, 153 "enable checkpoint pseudo instructions") 154 do_statistics_insts = Param.Bool(True, 155 "enable statistics pseudo instructions") 156 157 profile = Param.Latency('0ns', "trace the kernel stack") 158 do_quiesce = Param.Bool(True, "enable quiesce instructions") 159 160 wait_for_remote_gdb = Param.Bool(False, 161 "Wait for a remote GDB connection"); 162 163 workload = VectorParam.Process([], "processes to run") 164 165 if buildEnv['TARGET_ISA'] == 'sparc': 166 dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 167 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") 168 interrupts = VectorParam.SparcInterrupts( 169 [], "Interrupt Controller") 170 isa = VectorParam.SparcISA([ isa_class() ], "ISA instance") 171 elif buildEnv['TARGET_ISA'] == 'alpha': 172 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 173 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") 174 interrupts = VectorParam.AlphaInterrupts( 175 [], "Interrupt Controller") 176 isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance") 177 elif buildEnv['TARGET_ISA'] == 'x86': 178 dtb = Param.X86TLB(X86TLB(), "Data TLB") 179 itb = Param.X86TLB(X86TLB(), "Instruction TLB") 180 interrupts = VectorParam.X86LocalApic([], "Interrupt Controller") 181 isa = VectorParam.X86ISA([ isa_class() ], "ISA instance") 182 elif buildEnv['TARGET_ISA'] == 'mips': 183 dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 184 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") 185 interrupts = VectorParam.MipsInterrupts( 186 [], "Interrupt Controller") 187 isa = VectorParam.MipsISA([ isa_class() ], "ISA instance") 188 elif buildEnv['TARGET_ISA'] == 'arm': 189 dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 190 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") 191 istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans") 192 dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans") 193 interrupts = VectorParam.ArmInterrupts( 194 [], "Interrupt Controller") 195 isa = VectorParam.ArmISA([ isa_class() ], "ISA instance") 196 elif buildEnv['TARGET_ISA'] == 'power': 197 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 198 dtb = Param.PowerTLB(PowerTLB(), "Data TLB") 199 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") 200 interrupts = VectorParam.PowerInterrupts( 201 [], "Interrupt Controller") 202 isa = VectorParam.PowerISA([ isa_class() ], "ISA instance") 203 elif buildEnv['TARGET_ISA'] == 'riscv': 204 dtb = Param.RiscvTLB(RiscvTLB(), "Data TLB") 205 itb = Param.RiscvTLB(RiscvTLB(), "Instruction TLB") 206 interrupts = VectorParam.RiscvInterrupts( 207 [], "Interrupt Controller") 208 isa = VectorParam.RiscvISA([ isa_class() ], "ISA instance") 209 else: 210 print "Don't know what TLB to use for ISA %s" % \ 211 buildEnv['TARGET_ISA'] 212 sys.exit(1) 213 214 max_insts_all_threads = Param.Counter(0, 215 "terminate when all threads have reached this inst count") 216 max_insts_any_thread = Param.Counter(0, 217 "terminate when any thread reaches this inst count") 218 simpoint_start_insts = VectorParam.Counter([], 219 "starting instruction counts of simpoints") 220 max_loads_all_threads = Param.Counter(0, 221 "terminate when all threads have reached this load count") 222 max_loads_any_thread = Param.Counter(0, 223 "terminate when any thread reaches this load count") 224 progress_interval = Param.Frequency('0Hz', 225 "frequency to print out the progress message") 226 227 switched_out = Param.Bool(False, 228 "Leave the CPU switched out after startup (used when switching " \ 229 "between CPU models)") 230 231 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 232 233 icache_port = MasterPort("Instruction Port") 234 dcache_port = MasterPort("Data Port") 235 _cached_ports = ['icache_port', 'dcache_port'] 236 237 if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 238 _cached_ports += ["itb.walker.port", "dtb.walker.port"] 239 240 _uncached_slave_ports = [] 241 _uncached_master_ports = [] 242 if buildEnv['TARGET_ISA'] == 'x86': 243 _uncached_slave_ports += ["interrupts[0].pio", 244 "interrupts[0].int_slave"] 245 _uncached_master_ports += ["interrupts[0].int_master"] 246 247 def createInterruptController(self): 248 if buildEnv['TARGET_ISA'] == 'sparc': 249 self.interrupts = [SparcInterrupts() for i in xrange(self.numThreads)] 250 elif buildEnv['TARGET_ISA'] == 'alpha': 251 self.interrupts = [AlphaInterrupts() for i in xrange(self.numThreads)] 252 elif buildEnv['TARGET_ISA'] == 'x86': 253 self.apic_clk_domain = DerivedClockDomain(clk_domain = 254 Parent.clk_domain, 255 clk_divider = 16) 256 self.interrupts = [X86LocalApic(clk_domain = self.apic_clk_domain, 257 pio_addr=0x2000000000000000) 258 for i in xrange(self.numThreads)] 259 _localApic = self.interrupts 260 elif buildEnv['TARGET_ISA'] == 'mips': 261 self.interrupts = [MipsInterrupts() for i in xrange(self.numThreads)] 262 elif buildEnv['TARGET_ISA'] == 'arm': 263 self.interrupts = [ArmInterrupts() for i in xrange(self.numThreads)] 264 elif buildEnv['TARGET_ISA'] == 'power': 265 self.interrupts = [PowerInterrupts() for i in xrange(self.numThreads)] 266 elif buildEnv['TARGET_ISA'] == 'riscv': 267 self.interrupts = \ 268 [RiscvInterrupts() for i in xrange(self.numThreads)] 269 else: 270 print "Don't know what Interrupt Controller to use for ISA %s" % \ 271 buildEnv['TARGET_ISA'] 272 sys.exit(1) 273 274 def connectCachedPorts(self, bus): 275 for p in self._cached_ports: 276 exec('self.%s = bus.slave' % p) 277 278 def connectUncachedPorts(self, bus): 279 for p in self._uncached_slave_ports: 280 exec('self.%s = bus.master' % p) 281 for p in self._uncached_master_ports: 282 exec('self.%s = bus.slave' % p) 283 284 def connectAllPorts(self, cached_bus, uncached_bus = None): 285 self.connectCachedPorts(cached_bus) 286 if not uncached_bus: 287 uncached_bus = cached_bus 288 self.connectUncachedPorts(uncached_bus) 289 290 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 291 self.icache = ic 292 self.dcache = dc 293 self.icache_port = ic.cpu_side 294 self.dcache_port = dc.cpu_side 295 self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 296 if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 297 if iwc and dwc: 298 self.itb_walker_cache = iwc 299 self.dtb_walker_cache = dwc 300 self.itb.walker.port = iwc.cpu_side 301 self.dtb.walker.port = dwc.cpu_side 302 self._cached_ports += ["itb_walker_cache.mem_side", \ 303 "dtb_walker_cache.mem_side"] 304 else: 305 self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 306 307 # Checker doesn't need its own tlb caches because it does 308 # functional accesses only 309 if self.checker != NULL: 310 self._cached_ports += ["checker.itb.walker.port", \ 311 "checker.dtb.walker.port"] 312 313 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 314 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 315 self.toL2Bus = L2XBar() 316 self.connectCachedPorts(self.toL2Bus) 317 self.l2cache = l2c 318 self.toL2Bus.master = self.l2cache.cpu_side 319 self._cached_ports = ['l2cache.mem_side'] 320 321 def createThreads(self): 322 self.isa = [ isa_class() for i in xrange(self.numThreads) ] 323 if self.checker != NULL: 324 self.checker.createThreads() 325 326 def addCheckerCpu(self): 327 pass 328