BaseCPU.py revision 11415
110717Sandreas.hansson@arm.com# Copyright (c) 2012-2013, 2015 ARM Limited 28839Sandreas.hansson@arm.com# All rights reserved. 38839Sandreas.hansson@arm.com# 48839Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 58839Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 68839Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 78839Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 88839Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 98839Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 108839Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 118839Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 128839Sandreas.hansson@arm.com# 135335Shines@cs.fsu.edu# Copyright (c) 2005-2008 The Regents of The University of Michigan 147897Shestness@cs.utexas.edu# Copyright (c) 2011 Regents of the University of California 154486Sbinkertn@umich.edu# All rights reserved. 164486Sbinkertn@umich.edu# 174486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 184486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 194486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 204486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 214486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 224486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 234486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 244486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 254486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 264486Sbinkertn@umich.edu# this software without specific prior written permission. 274486Sbinkertn@umich.edu# 284486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 324486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 364486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 384486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394486Sbinkertn@umich.edu# 404486Sbinkertn@umich.edu# Authors: Nathan Binkert 417897Shestness@cs.utexas.edu# Rick Strong 428839Sandreas.hansson@arm.com# Andreas Hansson 434486Sbinkertn@umich.edu 446654Snate@binkert.orgimport sys 456654Snate@binkert.org 466654Snate@binkert.orgfrom m5.defines import buildEnv 473102SN/Afrom m5.params import * 483102SN/Afrom m5.proxy import * 496654Snate@binkert.org 5010720Sandreas.hansson@arm.comfrom XBar import L2XBar 514776Sgblack@eecs.umich.edufrom InstTracer import InstTracer 5210663SAli.Saidi@ARM.comfrom CPUTracers import ExeTracer 536654Snate@binkert.orgfrom MemObject import MemObject 549793Sakash.bagdia@arm.comfrom ClockDomain import * 552667SN/A 564776Sgblack@eecs.umich.edudefault_tracer = ExeTracer() 574776Sgblack@eecs.umich.edu 586654Snate@binkert.orgif buildEnv['TARGET_ISA'] == 'alpha': 596023Snate@binkert.org from AlphaTLB import AlphaDTB, AlphaITB 608745Sgblack@eecs.umich.edu from AlphaInterrupts import AlphaInterrupts 619384SAndreas.Sandberg@arm.com from AlphaISA import AlphaISA 629384SAndreas.Sandberg@arm.com isa_class = AlphaISA 636654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'sparc': 646022Sgblack@eecs.umich.edu from SparcTLB import SparcTLB 658745Sgblack@eecs.umich.edu from SparcInterrupts import SparcInterrupts 669384SAndreas.Sandberg@arm.com from SparcISA import SparcISA 679384SAndreas.Sandberg@arm.com isa_class = SparcISA 686654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'x86': 696022Sgblack@eecs.umich.edu from X86TLB import X86TLB 708745Sgblack@eecs.umich.edu from X86LocalApic import X86LocalApic 719384SAndreas.Sandberg@arm.com from X86ISA import X86ISA 729384SAndreas.Sandberg@arm.com isa_class = X86ISA 736654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'mips': 746022Sgblack@eecs.umich.edu from MipsTLB import MipsTLB 758745Sgblack@eecs.umich.edu from MipsInterrupts import MipsInterrupts 769384SAndreas.Sandberg@arm.com from MipsISA import MipsISA 779384SAndreas.Sandberg@arm.com isa_class = MipsISA 786654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == 'arm': 7910037SARM gem5 Developers from ArmTLB import ArmTLB, ArmStage2IMMU, ArmStage2DMMU 808745Sgblack@eecs.umich.edu from ArmInterrupts import ArmInterrupts 819384SAndreas.Sandberg@arm.com from ArmISA import ArmISA 829384SAndreas.Sandberg@arm.com isa_class = ArmISA 836691Stjones1@inf.ed.ac.ukelif buildEnv['TARGET_ISA'] == 'power': 846691Stjones1@inf.ed.ac.uk from PowerTLB import PowerTLB 858745Sgblack@eecs.umich.edu from PowerInterrupts import PowerInterrupts 869384SAndreas.Sandberg@arm.com from PowerISA import PowerISA 879384SAndreas.Sandberg@arm.com isa_class = PowerISA 884486Sbinkertn@umich.edu 895529Snate@binkert.orgclass BaseCPU(MemObject): 901366SN/A type = 'BaseCPU' 911310SN/A abstract = True 929338SAndreas.Sandberg@arm.com cxx_header = "cpu/base.hh" 939254SAndreas.Sandberg@arm.com 949254SAndreas.Sandberg@arm.com @classmethod 959254SAndreas.Sandberg@arm.com def export_methods(cls, code): 969254SAndreas.Sandberg@arm.com code(''' 979254SAndreas.Sandberg@arm.com void switchOut(); 989254SAndreas.Sandberg@arm.com void takeOverFrom(BaseCPU *cpu); 999430SAndreas.Sandberg@ARM.com bool switchedOut(); 1009446SAndreas.Sandberg@ARM.com void flushTLBs(); 1019650Stimothy.jones@arm.com Counter totalInsts(); 1029749Sandreas@sandberg.pp.se void scheduleInstStop(ThreadID tid, Counter insts, const char *cause); 1039749Sandreas@sandberg.pp.se void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause); 10411415SGeoffrey.Blake@arm.com uint64_t getCurrentInstCount(ThreadID tid); 1059254SAndreas.Sandberg@arm.com''') 1069254SAndreas.Sandberg@arm.com 1079518SAndreas.Sandberg@ARM.com @classmethod 1089518SAndreas.Sandberg@ARM.com def memory_mode(cls): 1099518SAndreas.Sandberg@ARM.com """Which memory mode does this CPU require?""" 1109518SAndreas.Sandberg@ARM.com return 'invalid' 1119518SAndreas.Sandberg@ARM.com 1129518SAndreas.Sandberg@ARM.com @classmethod 1139518SAndreas.Sandberg@ARM.com def require_caches(cls): 1149518SAndreas.Sandberg@ARM.com """Does the CPU model require caches? 1159518SAndreas.Sandberg@ARM.com 1169518SAndreas.Sandberg@ARM.com Some CPU models might make assumptions that require them to 1179518SAndreas.Sandberg@ARM.com have caches. 1189518SAndreas.Sandberg@ARM.com """ 1199518SAndreas.Sandberg@ARM.com return False 1209518SAndreas.Sandberg@ARM.com 1219518SAndreas.Sandberg@ARM.com @classmethod 1229518SAndreas.Sandberg@ARM.com def support_take_over(cls): 1239518SAndreas.Sandberg@ARM.com """Does the CPU model support CPU takeOverFrom?""" 1249518SAndreas.Sandberg@ARM.com return False 1259518SAndreas.Sandberg@ARM.com 1269254SAndreas.Sandberg@arm.com def takeOverFrom(self, old_cpu): 1279254SAndreas.Sandberg@arm.com self._ccObject.takeOverFrom(old_cpu._ccObject) 1289254SAndreas.Sandberg@arm.com 1299254SAndreas.Sandberg@arm.com 1302901SN/A system = Param.System(Parent.any, "system object") 1315712Shsul@eecs.umich.edu cpu_id = Param.Int(-1, "CPU identifier") 13210190Sakash.bagdia@arm.com socket_id = Param.Unsigned(0, "Physical Socket identifier") 1335529Snate@binkert.org numThreads = Param.Unsigned(1, "number of HW thread contexts") 1345529Snate@binkert.org 1355529Snate@binkert.org function_trace = Param.Bool(False, "Enable function trace") 1369161Sandreas.hansson@arm.com function_trace_start = Param.Tick(0, "Tick to start function trace") 1375529Snate@binkert.org 1385821Ssaidi@eecs.umich.edu checker = Param.BaseCPU(NULL, "checker CPU") 1393170SN/A 1405780Ssteve.reinhardt@amd.com do_checkpoint_insts = Param.Bool(True, 1415780Ssteve.reinhardt@amd.com "enable checkpoint pseudo instructions") 1425780Ssteve.reinhardt@amd.com do_statistics_insts = Param.Bool(True, 1435780Ssteve.reinhardt@amd.com "enable statistics pseudo instructions") 1445780Ssteve.reinhardt@amd.com 1458784Sgblack@eecs.umich.edu profile = Param.Latency('0ns', "trace the kernel stack") 1468784Sgblack@eecs.umich.edu do_quiesce = Param.Bool(True, "enable quiesce instructions") 1478784Sgblack@eecs.umich.edu 1488793Sgblack@eecs.umich.edu workload = VectorParam.Process([], "processes to run") 1491310SN/A 1506654Snate@binkert.org if buildEnv['TARGET_ISA'] == 'sparc': 1516022Sgblack@eecs.umich.edu dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 1526022Sgblack@eecs.umich.edu itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") 15311150Smitch.hayenga@arm.com interrupts = VectorParam.SparcInterrupts( 15411150Smitch.hayenga@arm.com [], "Interrupt Controller") 1559384SAndreas.Sandberg@arm.com isa = VectorParam.SparcISA([ isa_class() ], "ISA instance") 1566654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'alpha': 1576023Snate@binkert.org dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 1586023Snate@binkert.org itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") 15911150Smitch.hayenga@arm.com interrupts = VectorParam.AlphaInterrupts( 16011150Smitch.hayenga@arm.com [], "Interrupt Controller") 1619384SAndreas.Sandberg@arm.com isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance") 1626654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'x86': 1636022Sgblack@eecs.umich.edu dtb = Param.X86TLB(X86TLB(), "Data TLB") 1646022Sgblack@eecs.umich.edu itb = Param.X86TLB(X86TLB(), "Instruction TLB") 16511150Smitch.hayenga@arm.com interrupts = VectorParam.X86LocalApic([], "Interrupt Controller") 1669384SAndreas.Sandberg@arm.com isa = VectorParam.X86ISA([ isa_class() ], "ISA instance") 1676654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'mips': 1686022Sgblack@eecs.umich.edu dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 1696022Sgblack@eecs.umich.edu itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") 17011150Smitch.hayenga@arm.com interrupts = VectorParam.MipsInterrupts( 17111150Smitch.hayenga@arm.com [], "Interrupt Controller") 1729384SAndreas.Sandberg@arm.com isa = VectorParam.MipsISA([ isa_class() ], "ISA instance") 1736654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'arm': 1746116Snate@binkert.org dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 1756116Snate@binkert.org itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") 17610037SARM gem5 Developers istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans") 17710037SARM gem5 Developers dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans") 17811150Smitch.hayenga@arm.com interrupts = VectorParam.ArmInterrupts( 17911150Smitch.hayenga@arm.com [], "Interrupt Controller") 1809384SAndreas.Sandberg@arm.com isa = VectorParam.ArmISA([ isa_class() ], "ISA instance") 1816691Stjones1@inf.ed.ac.uk elif buildEnv['TARGET_ISA'] == 'power': 1826691Stjones1@inf.ed.ac.uk UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 1836691Stjones1@inf.ed.ac.uk dtb = Param.PowerTLB(PowerTLB(), "Data TLB") 1846691Stjones1@inf.ed.ac.uk itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") 18511150Smitch.hayenga@arm.com interrupts = VectorParam.PowerInterrupts( 18611150Smitch.hayenga@arm.com [], "Interrupt Controller") 1879384SAndreas.Sandberg@arm.com isa = VectorParam.PowerISA([ isa_class() ], "ISA instance") 1884997Sgblack@eecs.umich.edu else: 1894997Sgblack@eecs.umich.edu print "Don't know what TLB to use for ISA %s" % \ 1906654Snate@binkert.org buildEnv['TARGET_ISA'] 1914997Sgblack@eecs.umich.edu sys.exit(1) 1924997Sgblack@eecs.umich.edu 1931310SN/A max_insts_all_threads = Param.Counter(0, 1941310SN/A "terminate when all threads have reached this inst count") 1951310SN/A max_insts_any_thread = Param.Counter(0, 1961310SN/A "terminate when any thread reaches this inst count") 1979647Sdam.sunwoo@arm.com simpoint_start_insts = VectorParam.Counter([], 1989647Sdam.sunwoo@arm.com "starting instruction counts of simpoints") 1991310SN/A max_loads_all_threads = Param.Counter(0, 2001310SN/A "terminate when all threads have reached this load count") 2011310SN/A max_loads_any_thread = Param.Counter(0, 2021310SN/A "terminate when any thread reaches this load count") 2039180Sandreas.hansson@arm.com progress_interval = Param.Frequency('0Hz', 2049180Sandreas.hansson@arm.com "frequency to print out the progress message") 2051310SN/A 2069433SAndreas.Sandberg@ARM.com switched_out = Param.Bool(False, 2079433SAndreas.Sandberg@ARM.com "Leave the CPU switched out after startup (used when switching " \ 2089433SAndreas.Sandberg@ARM.com "between CPU models)") 2091634SN/A 2104776Sgblack@eecs.umich.edu tracer = Param.InstTracer(default_tracer, "Instruction tracer") 2114776Sgblack@eecs.umich.edu 2128839Sandreas.hansson@arm.com icache_port = MasterPort("Instruction Port") 2138839Sandreas.hansson@arm.com dcache_port = MasterPort("Data Port") 2148707Sandreas.hansson@arm.com _cached_ports = ['icache_port', 'dcache_port'] 2158707Sandreas.hansson@arm.com 2168756Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 2178707Sandreas.hansson@arm.com _cached_ports += ["itb.walker.port", "dtb.walker.port"] 2187876Sgblack@eecs.umich.edu 2198839Sandreas.hansson@arm.com _uncached_slave_ports = [] 2208839Sandreas.hansson@arm.com _uncached_master_ports = [] 2218745Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'x86': 22211150Smitch.hayenga@arm.com _uncached_slave_ports += ["interrupts[0].pio", 22311150Smitch.hayenga@arm.com "interrupts[0].int_slave"] 22411150Smitch.hayenga@arm.com _uncached_master_ports += ["interrupts[0].int_master"] 2252998SN/A 2268863Snilay@cs.wisc.edu def createInterruptController(self): 2278863Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] == 'sparc': 22811150Smitch.hayenga@arm.com self.interrupts = [SparcInterrupts() for i in xrange(self.numThreads)] 2298863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'alpha': 23011150Smitch.hayenga@arm.com self.interrupts = [AlphaInterrupts() for i in xrange(self.numThreads)] 2318863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'x86': 2329793Sakash.bagdia@arm.com self.apic_clk_domain = DerivedClockDomain(clk_domain = 2339793Sakash.bagdia@arm.com Parent.clk_domain, 2349793Sakash.bagdia@arm.com clk_divider = 16) 23511150Smitch.hayenga@arm.com self.interrupts = [X86LocalApic(clk_domain = self.apic_clk_domain, 2369544Sandreas.hansson@arm.com pio_addr=0x2000000000000000) 23711150Smitch.hayenga@arm.com for i in xrange(self.numThreads)] 2389544Sandreas.hansson@arm.com _localApic = self.interrupts 2398863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'mips': 24011150Smitch.hayenga@arm.com self.interrupts = [MipsInterrupts() for i in xrange(self.numThreads)] 2418863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'arm': 24211150Smitch.hayenga@arm.com self.interrupts = [ArmInterrupts() for i in xrange(self.numThreads)] 2438863Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'power': 24411150Smitch.hayenga@arm.com self.interrupts = [PowerInterrupts() for i in xrange(self.numThreads)] 2458863Snilay@cs.wisc.edu else: 2468863Snilay@cs.wisc.edu print "Don't know what Interrupt Controller to use for ISA %s" % \ 2478863Snilay@cs.wisc.edu buildEnv['TARGET_ISA'] 2488863Snilay@cs.wisc.edu sys.exit(1) 2498863Snilay@cs.wisc.edu 2507876Sgblack@eecs.umich.edu def connectCachedPorts(self, bus): 2517876Sgblack@eecs.umich.edu for p in self._cached_ports: 2528839Sandreas.hansson@arm.com exec('self.%s = bus.slave' % p) 2537404SAli.Saidi@ARM.com 2547876Sgblack@eecs.umich.edu def connectUncachedPorts(self, bus): 2558839Sandreas.hansson@arm.com for p in self._uncached_slave_ports: 2568839Sandreas.hansson@arm.com exec('self.%s = bus.master' % p) 2578839Sandreas.hansson@arm.com for p in self._uncached_master_ports: 2588839Sandreas.hansson@arm.com exec('self.%s = bus.slave' % p) 2597876Sgblack@eecs.umich.edu 2607876Sgblack@eecs.umich.edu def connectAllPorts(self, cached_bus, uncached_bus = None): 2617876Sgblack@eecs.umich.edu self.connectCachedPorts(cached_bus) 2627876Sgblack@eecs.umich.edu if not uncached_bus: 2637876Sgblack@eecs.umich.edu uncached_bus = cached_bus 2647876Sgblack@eecs.umich.edu self.connectUncachedPorts(uncached_bus) 2652998SN/A 2667868Sgblack@eecs.umich.edu def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 2672998SN/A self.icache = ic 2682998SN/A self.dcache = dc 2692998SN/A self.icache_port = ic.cpu_side 2702998SN/A self.dcache_port = dc.cpu_side 2717876Sgblack@eecs.umich.edu self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 2728796Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 2738796Sgblack@eecs.umich.edu if iwc and dwc: 2748796Sgblack@eecs.umich.edu self.itb_walker_cache = iwc 2758796Sgblack@eecs.umich.edu self.dtb_walker_cache = dwc 27610717Sandreas.hansson@arm.com self.itb.walker.port = iwc.cpu_side 27710717Sandreas.hansson@arm.com self.dtb.walker.port = dwc.cpu_side 2788796Sgblack@eecs.umich.edu self._cached_ports += ["itb_walker_cache.mem_side", \ 2798796Sgblack@eecs.umich.edu "dtb_walker_cache.mem_side"] 2808796Sgblack@eecs.umich.edu else: 2818796Sgblack@eecs.umich.edu self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 2828887Sgeoffrey.blake@arm.com 2838809Sgblack@eecs.umich.edu # Checker doesn't need its own tlb caches because it does 2848809Sgblack@eecs.umich.edu # functional accesses only 2858887Sgeoffrey.blake@arm.com if self.checker != NULL: 2868809Sgblack@eecs.umich.edu self._cached_ports += ["checker.itb.walker.port", \ 2878809Sgblack@eecs.umich.edu "checker.dtb.walker.port"] 2882998SN/A 2897868Sgblack@eecs.umich.edu def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 2907868Sgblack@eecs.umich.edu self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 29110720Sandreas.hansson@arm.com self.toL2Bus = L2XBar() 2927876Sgblack@eecs.umich.edu self.connectCachedPorts(self.toL2Bus) 2932998SN/A self.l2cache = l2c 2948839Sandreas.hansson@arm.com self.toL2Bus.master = self.l2cache.cpu_side 2957876Sgblack@eecs.umich.edu self._cached_ports = ['l2cache.mem_side'] 2968887Sgeoffrey.blake@arm.com 2979384SAndreas.Sandberg@arm.com def createThreads(self): 2989384SAndreas.Sandberg@arm.com self.isa = [ isa_class() for i in xrange(self.numThreads) ] 2999384SAndreas.Sandberg@arm.com if self.checker != NULL: 3009384SAndreas.Sandberg@arm.com self.checker.createThreads() 3019384SAndreas.Sandberg@arm.com 3028887Sgeoffrey.blake@arm.com def addCheckerCpu(self): 3038887Sgeoffrey.blake@arm.com pass 304