utility.hh revision 9889:2dbc34e3b922
15882Snate@binkert.org/* 25882Snate@binkert.org * Copyright (c) 2007 The Hewlett-Packard Development Company 35882Snate@binkert.org * All rights reserved. 45882Snate@binkert.org * 55882Snate@binkert.org * The license below extends only to copyright in the software and shall 65882Snate@binkert.org * not be construed as granting a license to any other intellectual 75882Snate@binkert.org * property including but not limited to intellectual property relating 85882Snate@binkert.org * to a hardware implementation of the functionality of the software 95882Snate@binkert.org * licensed hereunder. You may use the software subject to the license 105882Snate@binkert.org * terms below provided that you ensure that this notice is replicated 115882Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 125882Snate@binkert.org * modified or unmodified, in source code or in binary form. 135882Snate@binkert.org * 145882Snate@binkert.org * Redistribution and use in source and binary forms, with or without 155882Snate@binkert.org * modification, are permitted provided that the following conditions are 165882Snate@binkert.org * met: redistributions of source code must retain the above copyright 175882Snate@binkert.org * notice, this list of conditions and the following disclaimer; 185882Snate@binkert.org * redistributions in binary form must reproduce the above copyright 195882Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 205882Snate@binkert.org * documentation and/or other materials provided with the distribution; 215882Snate@binkert.org * neither the name of the copyright holders nor the names of its 225882Snate@binkert.org * contributors may be used to endorse or promote products derived from 235882Snate@binkert.org * this software without specific prior written permission. 245882Snate@binkert.org * 255882Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 265882Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 275882Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 285882Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 295882Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 305882Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 315882Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 325882Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 335882Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 348232Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 358229Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 368232Snate@binkert.org * 378232Snate@binkert.org * Authors: Gabe Black 388229Snate@binkert.org */ 395882Snate@binkert.org 408232Snate@binkert.org#ifndef __ARCH_X86_UTILITY_HH__ 418232Snate@binkert.org#define __ARCH_X86_UTILITY_HH__ 428232Snate@binkert.org 438232Snate@binkert.org#include "arch/x86/regs/misc.hh" 445882Snate@binkert.org#include "arch/x86/types.hh" 458231Snate@binkert.org#include "base/hashmap.hh" 468231Snate@binkert.org#include "base/misc.hh" 478232Snate@binkert.org#include "base/types.hh" 488232Snate@binkert.org#include "cpu/static_inst.hh" 498232Snate@binkert.org#include "cpu/thread_context.hh" 508232Snate@binkert.org#include "sim/full_system.hh" 518232Snate@binkert.org 525882Snate@binkert.orgclass ThreadContext; 538231Snate@binkert.org 545882Snate@binkert.orgnamespace X86ISA 555882Snate@binkert.org{ 565882Snate@binkert.org 575882Snate@binkert.org inline PCState 588231Snate@binkert.org buildRetPC(const PCState &curPC, const PCState &callPC) 595882Snate@binkert.org { 605882Snate@binkert.org PCState retPC = callPC; 618231Snate@binkert.org retPC.uEnd(); 628232Snate@binkert.org return retPC; 638232Snate@binkert.org } 648232Snate@binkert.org 658232Snate@binkert.org uint64_t 668232Snate@binkert.org getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp); 678232Snate@binkert.org 688232Snate@binkert.org static inline bool 698232Snate@binkert.org inUserMode(ThreadContext *tc) 708232Snate@binkert.org { 718232Snate@binkert.org if (!FullSystem) { 728232Snate@binkert.org return true; 738232Snate@binkert.org } else { 748232Snate@binkert.org HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); 758232Snate@binkert.org return m5reg.cpl == 3; 768232Snate@binkert.org } 778232Snate@binkert.org } 788232Snate@binkert.org 798232Snate@binkert.org /** 808232Snate@binkert.org * Function to insure ISA semantics about 0 registers. 818232Snate@binkert.org * @param tc The thread context. 828232Snate@binkert.org */ 838232Snate@binkert.org template <class TC> 848232Snate@binkert.org void zeroRegisters(TC *tc); 858232Snate@binkert.org 868232Snate@binkert.org void initCPU(ThreadContext *tc, int cpuId); 878232Snate@binkert.org 888232Snate@binkert.org void startupCPU(ThreadContext *tc, int cpuId); 898232Snate@binkert.org 908232Snate@binkert.org void copyRegs(ThreadContext *src, ThreadContext *dest); 918232Snate@binkert.org 928232Snate@binkert.org void copyMiscRegs(ThreadContext *src, ThreadContext *dest); 938232Snate@binkert.org 948232Snate@binkert.org void skipFunction(ThreadContext *tc); 958232Snate@binkert.org 968232Snate@binkert.org inline void 978232Snate@binkert.org advancePC(PCState &pc, const StaticInstPtr inst) 988232Snate@binkert.org { 998232Snate@binkert.org inst->advancePC(pc); 1008232Snate@binkert.org } 1018232Snate@binkert.org 1028232Snate@binkert.org inline uint64_t 1038232Snate@binkert.org getExecutingAsid(ThreadContext *tc) 1048269Snate@binkert.org { 1058232Snate@binkert.org return 0; 1068232Snate@binkert.org } 1078232Snate@binkert.org 1088232Snate@binkert.org 1098232Snate@binkert.org /** 1108232Snate@binkert.org * Reconstruct the rflags register from the internal gem5 register 1118269Snate@binkert.org * state. 1128232Snate@binkert.org * 1138232Snate@binkert.org * gem5 stores rflags in several different registers to avoid 1148232Snate@binkert.org * pipeline dependencies. In order to get the true rflags value, 1158232Snate@binkert.org * we can't simply read the value of MISCREG_RFLAGS. Instead, we 1168232Snate@binkert.org * need to read out various state from microcode registers and 1178232Snate@binkert.org * merge that with MISCREG_RFLAGS. 1188232Snate@binkert.org * 1198232Snate@binkert.org * @param tc Thread context to read rflags from. 1208232Snate@binkert.org * @return rflags as seen by the guest. 1218232Snate@binkert.org */ 1228232Snate@binkert.org uint64_t getRFlags(ThreadContext *tc); 1238232Snate@binkert.org 1248232Snate@binkert.org /** 1258232Snate@binkert.org * Set update the rflags register and internal gem5 state. 1268232Snate@binkert.org * 1278232Snate@binkert.org * @note This function does not update MISCREG_M5_REG. You might 1288232Snate@binkert.org * need to update this register by writing anything to 1298232Snate@binkert.org * MISCREG_M5_REG with side-effects. 1308232Snate@binkert.org * 1318232Snate@binkert.org * @see X86ISA::getRFlags() 1328232Snate@binkert.org * 1338232Snate@binkert.org * @param tc Thread context to update 1348232Snate@binkert.org * @param val New rflags value to store in TC 1358232Snate@binkert.org */ 1368232Snate@binkert.org void setRFlags(ThreadContext *tc, uint64_t val); 1378699Ssteve.reinhardt@amd.com 1388232Snate@binkert.org /** 1398232Snate@binkert.org * Extract the bit string representing a double value. 1408232Snate@binkert.org */ 1418232Snate@binkert.org inline uint64_t getDoubleBits(double val) { 1428232Snate@binkert.org return *(uint64_t *)(&val); 1438232Snate@binkert.org } 1448232Snate@binkert.org 1458232Snate@binkert.org /** 1468232Snate@binkert.org * Convert an x87 tag word to abridged tag format. 1478232Snate@binkert.org * 1488232Snate@binkert.org * Convert from the x87 tag representation to the tag abridged 1498232Snate@binkert.org * representation used in the FXSAVE area. The classic format uses 1508232Snate@binkert.org * 2 bits per stack position to indicate if a position is valid, 1518232Snate@binkert.org * zero, special, or empty. The abridged format only stores 1528232Snate@binkert.org * whether a position is empty or not. 1538232Snate@binkert.org * 1548232Snate@binkert.org * @param ftw Tag word in classic x87 format. 1558232Snate@binkert.org * @return Tag word in the abridged format. 1568232Snate@binkert.org */ 1578232Snate@binkert.org uint8_t convX87TagsToXTags(uint16_t ftw); 1588232Snate@binkert.org 1598231Snate@binkert.org /** 1608232Snate@binkert.org * Convert an x87 xtag word to normal tags format. 1618232Snate@binkert.org * 1628232Snate@binkert.org * Convert from the abridged x87 tag representation used in the 1638232Snate@binkert.org * FXSAVE area to a full x87 tag. The classic format uses 2 bits 1648232Snate@binkert.org * per stack position to indicate if a position is valid, zero, 1658232Snate@binkert.org * special, or empty. The abridged format only stores whether a 1668232Snate@binkert.org * position is empty or not. 1678232Snate@binkert.org * 1688232Snate@binkert.org * @todo Reconstruct the correct state of stack positions instead 1698232Snate@binkert.org * of just valid/invalid. 1708232Snate@binkert.org * 1718232Snate@binkert.org * @param ftwx Tag word in the abridged format. 1728232Snate@binkert.org * @return Tag word in classic x87 format. 1738232Snate@binkert.org */ 1748232Snate@binkert.org uint16_t convX87XTagsToTags(uint8_t ftwx); 1758232Snate@binkert.org 1768232Snate@binkert.org /** 1778232Snate@binkert.org * Generate and updated x87 tag register after a push/pop 1788232Snate@binkert.org * operation. 1798232Snate@binkert.org * 1808232Snate@binkert.org * @note There is currently no support for setting other tags than 1818232Snate@binkert.org * valid and invalid. A real x87 will set the tag value to zero or 1828232Snate@binkert.org * special for some special floating point values. 1838232Snate@binkert.org * 1848232Snate@binkert.org * @param ftw Current value of the FTW register. 1858232Snate@binkert.org * @param top Current x87 TOP value. 186 * @param spm Stack displacement. 187 * @return New value of the FTW register. 188 */ 189 uint16_t genX87Tags(uint16_t ftw, uint8_t top, int8_t spm); 190 191 /** 192 * Load an 80-bit float from memory and convert it to double. 193 * 194 * @param mem Pointer to an 80-bit float. 195 * @return double representation of the 80-bit float. 196 */ 197 double loadFloat80(const void *mem); 198 199 /** 200 * Convert and store a double as an 80-bit float. 201 * 202 * @param mem Pointer to destination for the 80-bit float. 203 * @param value Double precision float to store. 204 */ 205 void storeFloat80(void *mem, double value); 206} 207 208#endif // __ARCH_X86_UTILITY_HH__ 209