utility.hh revision 9765:da0e0df0ba97 
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#ifndef __ARCH_X86_UTILITY_HH__
41#define __ARCH_X86_UTILITY_HH__
42
43#include "arch/x86/regs/misc.hh"
44#include "arch/x86/types.hh"
45#include "base/hashmap.hh"
46#include "base/misc.hh"
47#include "base/types.hh"
48#include "cpu/static_inst.hh"
49#include "cpu/thread_context.hh"
50#include "sim/full_system.hh"
51
52class ThreadContext;
53
54namespace X86ISA
55{
56
57    inline PCState
58    buildRetPC(const PCState &curPC, const PCState &callPC)
59    {
60        PCState retPC = callPC;
61        retPC.uEnd();
62        return retPC;
63    }
64
65    uint64_t
66    getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
67
68    static inline bool
69    inUserMode(ThreadContext *tc)
70    {
71        if (!FullSystem) {
72            return true;
73        } else {
74            HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
75            return m5reg.cpl == 3;
76        }
77    }
78
79    /**
80     * Function to insure ISA semantics about 0 registers.
81     * @param tc The thread context.
82     */
83    template <class TC>
84    void zeroRegisters(TC *tc);
85
86    void initCPU(ThreadContext *tc, int cpuId);
87
88    void startupCPU(ThreadContext *tc, int cpuId);
89
90    void copyRegs(ThreadContext *src, ThreadContext *dest);
91
92    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
93
94    void skipFunction(ThreadContext *tc);
95
96    inline void
97    advancePC(PCState &pc, const StaticInstPtr inst)
98    {
99        inst->advancePC(pc);
100    }
101
102    inline uint64_t
103    getExecutingAsid(ThreadContext *tc)
104    {
105        return 0;
106    }
107
108
109    /**
110     * Reconstruct the rflags register from the internal gem5 register
111     * state.
112     *
113     * gem5 stores rflags in several different registers to avoid
114     * pipeline dependencies. In order to get the true rflags value,
115     * we can't simply read the value of MISCREG_RFLAGS. Instead, we
116     * need to read out various state from microcode registers and
117     * merge that with MISCREG_RFLAGS.
118     *
119     * @param tc Thread context to read rflags from.
120     * @return rflags as seen by the guest.
121     */
122    uint64_t getRFlags(ThreadContext *tc);
123
124    /**
125     * Set update the rflags register and internal gem5 state.
126     *
127     * @note This function does not update MISCREG_M5_REG. You might
128     * need to update this register by writing anything to
129     * MISCREG_M5_REG with side-effects.
130     *
131     * @see X86ISA::getRFlags()
132     *
133     * @param tc Thread context to update
134     * @param val New rflags value to store in TC
135     */
136    void setRFlags(ThreadContext *tc, uint64_t val);
137
138    /**
139     * Extract the bit string representing a double value.
140     */
141    inline uint64_t getDoubleBits(double val) {
142        return *(uint64_t *)(&val);
143    }
144
145    /**
146     * Generate and updated x87 tag register after a push/pop
147     * operation.
148     *
149     * @note There is currently no support for setting other tags than
150     * valid and invalid. A real x87 will set the tag value to zero or
151     * special for some special floating point values.
152     *
153     * @param ftw Current value of the FTW register.
154     * @param top Current x87 TOP value.
155     * @param spm Stack displacement.
156     * @return New value of the FTW register.
157     */
158    uint16_t genX87Tags(uint16_t ftw, uint8_t top, int8_t spm);
159}
160
161#endif // __ARCH_X86_UTILITY_HH__
162