utility.hh revision 9765
14120Sgblack@eecs.umich.edu/* 24120Sgblack@eecs.umich.edu * Copyright (c) 2007 The Hewlett-Packard Development Company 34120Sgblack@eecs.umich.edu * All rights reserved. 44120Sgblack@eecs.umich.edu * 57087Snate@binkert.org * The license below extends only to copyright in the software and shall 67087Snate@binkert.org * not be construed as granting a license to any other intellectual 77087Snate@binkert.org * property including but not limited to intellectual property relating 87087Snate@binkert.org * to a hardware implementation of the functionality of the software 97087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 107087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 117087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 127087Snate@binkert.org * modified or unmodified, in source code or in binary form. 134120Sgblack@eecs.umich.edu * 147087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 157087Snate@binkert.org * modification, are permitted provided that the following conditions are 167087Snate@binkert.org * met: redistributions of source code must retain the above copyright 177087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 187087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 197087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 207087Snate@binkert.org * documentation and/or other materials provided with the distribution; 217087Snate@binkert.org * neither the name of the copyright holders nor the names of its 224120Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 237087Snate@binkert.org * this software without specific prior written permission. 244120Sgblack@eecs.umich.edu * 254120Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 264120Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 274120Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 284120Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 294120Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 304120Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 314120Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 324120Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 334120Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 344120Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 354120Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 364120Sgblack@eecs.umich.edu * 374120Sgblack@eecs.umich.edu * Authors: Gabe Black 384120Sgblack@eecs.umich.edu */ 394120Sgblack@eecs.umich.edu 404120Sgblack@eecs.umich.edu#ifndef __ARCH_X86_UTILITY_HH__ 414120Sgblack@eecs.umich.edu#define __ARCH_X86_UTILITY_HH__ 424120Sgblack@eecs.umich.edu 437629Sgblack@eecs.umich.edu#include "arch/x86/regs/misc.hh" 444148Sgblack@eecs.umich.edu#include "arch/x86/types.hh" 454182Sgblack@eecs.umich.edu#include "base/hashmap.hh" 464148Sgblack@eecs.umich.edu#include "base/misc.hh" 476216Snate@binkert.org#include "base/types.hh" 487720Sgblack@eecs.umich.edu#include "cpu/static_inst.hh" 494241Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 508768Sgblack@eecs.umich.edu#include "sim/full_system.hh" 514148Sgblack@eecs.umich.edu 524148Sgblack@eecs.umich.educlass ThreadContext; 534120Sgblack@eecs.umich.edu 544120Sgblack@eecs.umich.edunamespace X86ISA 554120Sgblack@eecs.umich.edu{ 567720Sgblack@eecs.umich.edu 577720Sgblack@eecs.umich.edu inline PCState 587720Sgblack@eecs.umich.edu buildRetPC(const PCState &curPC, const PCState &callPC) 597720Sgblack@eecs.umich.edu { 607720Sgblack@eecs.umich.edu PCState retPC = callPC; 617720Sgblack@eecs.umich.edu retPC.uEnd(); 627720Sgblack@eecs.umich.edu return retPC; 637720Sgblack@eecs.umich.edu } 647720Sgblack@eecs.umich.edu 657707Sgblack@eecs.umich.edu uint64_t 667707Sgblack@eecs.umich.edu getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp); 675086Sgblack@eecs.umich.edu 684148Sgblack@eecs.umich.edu static inline bool 694148Sgblack@eecs.umich.edu inUserMode(ThreadContext *tc) 704148Sgblack@eecs.umich.edu { 718768Sgblack@eecs.umich.edu if (!FullSystem) { 728768Sgblack@eecs.umich.edu return true; 738768Sgblack@eecs.umich.edu } else { 748768Sgblack@eecs.umich.edu HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); 758768Sgblack@eecs.umich.edu return m5reg.cpl == 3; 768768Sgblack@eecs.umich.edu } 774148Sgblack@eecs.umich.edu } 784148Sgblack@eecs.umich.edu 794148Sgblack@eecs.umich.edu /** 804148Sgblack@eecs.umich.edu * Function to insure ISA semantics about 0 registers. 814148Sgblack@eecs.umich.edu * @param tc The thread context. 824148Sgblack@eecs.umich.edu */ 834148Sgblack@eecs.umich.edu template <class TC> 844148Sgblack@eecs.umich.edu void zeroRegisters(TC *tc); 854148Sgblack@eecs.umich.edu 865135Sgblack@eecs.umich.edu void initCPU(ThreadContext *tc, int cpuId); 875135Sgblack@eecs.umich.edu 885135Sgblack@eecs.umich.edu void startupCPU(ThreadContext *tc, int cpuId); 896329Sgblack@eecs.umich.edu 906329Sgblack@eecs.umich.edu void copyRegs(ThreadContext *src, ThreadContext *dest); 916329Sgblack@eecs.umich.edu 926329Sgblack@eecs.umich.edu void copyMiscRegs(ThreadContext *src, ThreadContext *dest); 937693SAli.Saidi@ARM.com 947693SAli.Saidi@ARM.com void skipFunction(ThreadContext *tc); 957720Sgblack@eecs.umich.edu 967720Sgblack@eecs.umich.edu inline void 977720Sgblack@eecs.umich.edu advancePC(PCState &pc, const StaticInstPtr inst) 987720Sgblack@eecs.umich.edu { 997720Sgblack@eecs.umich.edu inst->advancePC(pc); 1007720Sgblack@eecs.umich.edu } 1018300Schander.sudanthi@arm.com 1028300Schander.sudanthi@arm.com inline uint64_t 1038300Schander.sudanthi@arm.com getExecutingAsid(ThreadContext *tc) 1048300Schander.sudanthi@arm.com { 1058300Schander.sudanthi@arm.com return 0; 1068300Schander.sudanthi@arm.com } 1078300Schander.sudanthi@arm.com 1089759Sandreas@sandberg.pp.se 1099759Sandreas@sandberg.pp.se /** 1109759Sandreas@sandberg.pp.se * Reconstruct the rflags register from the internal gem5 register 1119759Sandreas@sandberg.pp.se * state. 1129759Sandreas@sandberg.pp.se * 1139759Sandreas@sandberg.pp.se * gem5 stores rflags in several different registers to avoid 1149759Sandreas@sandberg.pp.se * pipeline dependencies. In order to get the true rflags value, 1159759Sandreas@sandberg.pp.se * we can't simply read the value of MISCREG_RFLAGS. Instead, we 1169759Sandreas@sandberg.pp.se * need to read out various state from microcode registers and 1179759Sandreas@sandberg.pp.se * merge that with MISCREG_RFLAGS. 1189759Sandreas@sandberg.pp.se * 1199759Sandreas@sandberg.pp.se * @param tc Thread context to read rflags from. 1209759Sandreas@sandberg.pp.se * @return rflags as seen by the guest. 1219759Sandreas@sandberg.pp.se */ 1229759Sandreas@sandberg.pp.se uint64_t getRFlags(ThreadContext *tc); 1239759Sandreas@sandberg.pp.se 1249759Sandreas@sandberg.pp.se /** 1259759Sandreas@sandberg.pp.se * Set update the rflags register and internal gem5 state. 1269759Sandreas@sandberg.pp.se * 1279759Sandreas@sandberg.pp.se * @note This function does not update MISCREG_M5_REG. You might 1289759Sandreas@sandberg.pp.se * need to update this register by writing anything to 1299759Sandreas@sandberg.pp.se * MISCREG_M5_REG with side-effects. 1309759Sandreas@sandberg.pp.se * 1319759Sandreas@sandberg.pp.se * @see X86ISA::getRFlags() 1329759Sandreas@sandberg.pp.se * 1339759Sandreas@sandberg.pp.se * @param tc Thread context to update 1349759Sandreas@sandberg.pp.se * @param val New rflags value to store in TC 1359759Sandreas@sandberg.pp.se */ 1369759Sandreas@sandberg.pp.se void setRFlags(ThreadContext *tc, uint64_t val); 1379764Sandreas@sandberg.pp.se 1389764Sandreas@sandberg.pp.se /** 1399764Sandreas@sandberg.pp.se * Extract the bit string representing a double value. 1409764Sandreas@sandberg.pp.se */ 1419764Sandreas@sandberg.pp.se inline uint64_t getDoubleBits(double val) { 1429764Sandreas@sandberg.pp.se return *(uint64_t *)(&val); 1439764Sandreas@sandberg.pp.se } 1449765Sandreas@sandberg.pp.se 1459765Sandreas@sandberg.pp.se /** 1469765Sandreas@sandberg.pp.se * Generate and updated x87 tag register after a push/pop 1479765Sandreas@sandberg.pp.se * operation. 1489765Sandreas@sandberg.pp.se * 1499765Sandreas@sandberg.pp.se * @note There is currently no support for setting other tags than 1509765Sandreas@sandberg.pp.se * valid and invalid. A real x87 will set the tag value to zero or 1519765Sandreas@sandberg.pp.se * special for some special floating point values. 1529765Sandreas@sandberg.pp.se * 1539765Sandreas@sandberg.pp.se * @param ftw Current value of the FTW register. 1549765Sandreas@sandberg.pp.se * @param top Current x87 TOP value. 1559765Sandreas@sandberg.pp.se * @param spm Stack displacement. 1569765Sandreas@sandberg.pp.se * @return New value of the FTW register. 1579765Sandreas@sandberg.pp.se */ 1589765Sandreas@sandberg.pp.se uint16_t genX87Tags(uint16_t ftw, uint8_t top, int8_t spm); 1598902Sandreas.hansson@arm.com} 1604120Sgblack@eecs.umich.edu 1614120Sgblack@eecs.umich.edu#endif // __ARCH_X86_UTILITY_HH__ 162