utility.hh revision 7087
14120Sgblack@eecs.umich.edu/* 24120Sgblack@eecs.umich.edu * Copyright (c) 2007 The Hewlett-Packard Development Company 34120Sgblack@eecs.umich.edu * All rights reserved. 44120Sgblack@eecs.umich.edu * 57087Snate@binkert.org * The license below extends only to copyright in the software and shall 67087Snate@binkert.org * not be construed as granting a license to any other intellectual 77087Snate@binkert.org * property including but not limited to intellectual property relating 87087Snate@binkert.org * to a hardware implementation of the functionality of the software 97087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 107087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 117087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 127087Snate@binkert.org * modified or unmodified, in source code or in binary form. 134120Sgblack@eecs.umich.edu * 147087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 157087Snate@binkert.org * modification, are permitted provided that the following conditions are 167087Snate@binkert.org * met: redistributions of source code must retain the above copyright 177087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 187087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 197087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 207087Snate@binkert.org * documentation and/or other materials provided with the distribution; 217087Snate@binkert.org * neither the name of the copyright holders nor the names of its 224120Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 237087Snate@binkert.org * this software without specific prior written permission. 244120Sgblack@eecs.umich.edu * 254120Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 264120Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 274120Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 284120Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 294120Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 304120Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 314120Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 324120Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 334120Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 344120Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 354120Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 364120Sgblack@eecs.umich.edu * 374120Sgblack@eecs.umich.edu * Authors: Gabe Black 384120Sgblack@eecs.umich.edu */ 394120Sgblack@eecs.umich.edu 404120Sgblack@eecs.umich.edu#ifndef __ARCH_X86_UTILITY_HH__ 414120Sgblack@eecs.umich.edu#define __ARCH_X86_UTILITY_HH__ 424120Sgblack@eecs.umich.edu 436313Sgblack@eecs.umich.edu#include "arch/x86/miscregs.hh" 444148Sgblack@eecs.umich.edu#include "arch/x86/types.hh" 454182Sgblack@eecs.umich.edu#include "base/hashmap.hh" 464148Sgblack@eecs.umich.edu#include "base/misc.hh" 476216Snate@binkert.org#include "base/types.hh" 485135Sgblack@eecs.umich.edu#include "config/full_system.hh" 494241Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 504148Sgblack@eecs.umich.edu 514148Sgblack@eecs.umich.educlass ThreadContext; 524120Sgblack@eecs.umich.edu 534182Sgblack@eecs.umich.edunamespace __hash_namespace { 544182Sgblack@eecs.umich.edu template<> 554182Sgblack@eecs.umich.edu struct hash<X86ISA::ExtMachInst> { 564182Sgblack@eecs.umich.edu size_t operator()(const X86ISA::ExtMachInst &emi) const { 574334Sgblack@eecs.umich.edu return (((uint64_t)emi.legacy << 56) | 584334Sgblack@eecs.umich.edu ((uint64_t)emi.rex << 48) | 594334Sgblack@eecs.umich.edu ((uint64_t)emi.modRM << 40) | 604334Sgblack@eecs.umich.edu ((uint64_t)emi.sib << 32) | 614334Sgblack@eecs.umich.edu ((uint64_t)emi.opcode.num << 24) | 624334Sgblack@eecs.umich.edu ((uint64_t)emi.opcode.prefixA << 16) | 634334Sgblack@eecs.umich.edu ((uint64_t)emi.opcode.prefixB << 8) | 644334Sgblack@eecs.umich.edu ((uint64_t)emi.opcode.op)) ^ 654342Sgblack@eecs.umich.edu emi.immediate ^ emi.displacement ^ 664587Sgblack@eecs.umich.edu emi.mode ^ 676437Sgblack@eecs.umich.edu emi.opSize ^ emi.addrSize ^ 686437Sgblack@eecs.umich.edu emi.stackSize ^ emi.dispSize; 694182Sgblack@eecs.umich.edu }; 704182Sgblack@eecs.umich.edu }; 714182Sgblack@eecs.umich.edu} 724182Sgblack@eecs.umich.edu 734120Sgblack@eecs.umich.edunamespace X86ISA 744120Sgblack@eecs.umich.edu{ 755086Sgblack@eecs.umich.edu uint64_t getArgument(ThreadContext *tc, int number, bool fp); 765086Sgblack@eecs.umich.edu 774148Sgblack@eecs.umich.edu static inline bool 784148Sgblack@eecs.umich.edu inUserMode(ThreadContext *tc) 794148Sgblack@eecs.umich.edu { 805910Sgblack@eecs.umich.edu#if FULL_SYSTEM 815910Sgblack@eecs.umich.edu HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); 825910Sgblack@eecs.umich.edu return m5reg.cpl == 3; 835910Sgblack@eecs.umich.edu#else 845910Sgblack@eecs.umich.edu return true; 855910Sgblack@eecs.umich.edu#endif 864148Sgblack@eecs.umich.edu } 874148Sgblack@eecs.umich.edu 884148Sgblack@eecs.umich.edu inline bool isCallerSaveIntegerRegister(unsigned int reg) { 894148Sgblack@eecs.umich.edu panic("register classification not implemented"); 904148Sgblack@eecs.umich.edu return false; 914148Sgblack@eecs.umich.edu } 924148Sgblack@eecs.umich.edu 934148Sgblack@eecs.umich.edu inline bool isCalleeSaveIntegerRegister(unsigned int reg) { 944148Sgblack@eecs.umich.edu panic("register classification not implemented"); 954148Sgblack@eecs.umich.edu return false; 964148Sgblack@eecs.umich.edu } 974148Sgblack@eecs.umich.edu 984148Sgblack@eecs.umich.edu inline bool isCallerSaveFloatRegister(unsigned int reg) { 994148Sgblack@eecs.umich.edu panic("register classification not implemented"); 1004148Sgblack@eecs.umich.edu return false; 1014148Sgblack@eecs.umich.edu } 1024148Sgblack@eecs.umich.edu 1034148Sgblack@eecs.umich.edu inline bool isCalleeSaveFloatRegister(unsigned int reg) { 1044148Sgblack@eecs.umich.edu panic("register classification not implemented"); 1054148Sgblack@eecs.umich.edu return false; 1064148Sgblack@eecs.umich.edu } 1074148Sgblack@eecs.umich.edu 1084148Sgblack@eecs.umich.edu // Instruction address compression hooks 1094148Sgblack@eecs.umich.edu inline Addr realPCToFetchPC(const Addr &addr) 1104148Sgblack@eecs.umich.edu { 1114148Sgblack@eecs.umich.edu return addr; 1124148Sgblack@eecs.umich.edu } 1134148Sgblack@eecs.umich.edu 1144148Sgblack@eecs.umich.edu inline Addr fetchPCToRealPC(const Addr &addr) 1154148Sgblack@eecs.umich.edu { 1164148Sgblack@eecs.umich.edu return addr; 1174148Sgblack@eecs.umich.edu } 1184148Sgblack@eecs.umich.edu 1194148Sgblack@eecs.umich.edu // the size of "fetched" instructions (not necessarily the size 1204148Sgblack@eecs.umich.edu // of real instructions for PISA) 1214148Sgblack@eecs.umich.edu inline size_t fetchInstSize() 1224148Sgblack@eecs.umich.edu { 1234148Sgblack@eecs.umich.edu return sizeof(MachInst); 1244148Sgblack@eecs.umich.edu } 1254148Sgblack@eecs.umich.edu 1264148Sgblack@eecs.umich.edu /** 1274148Sgblack@eecs.umich.edu * Function to insure ISA semantics about 0 registers. 1284148Sgblack@eecs.umich.edu * @param tc The thread context. 1294148Sgblack@eecs.umich.edu */ 1304148Sgblack@eecs.umich.edu template <class TC> 1314148Sgblack@eecs.umich.edu void zeroRegisters(TC *tc); 1324148Sgblack@eecs.umich.edu 1335135Sgblack@eecs.umich.edu#if FULL_SYSTEM 1344194Ssaidi@eecs.umich.edu 1355135Sgblack@eecs.umich.edu void initCPU(ThreadContext *tc, int cpuId); 1365135Sgblack@eecs.umich.edu 1375135Sgblack@eecs.umich.edu#endif 1385135Sgblack@eecs.umich.edu 1395135Sgblack@eecs.umich.edu void startupCPU(ThreadContext *tc, int cpuId); 1406329Sgblack@eecs.umich.edu 1416329Sgblack@eecs.umich.edu void copyRegs(ThreadContext *src, ThreadContext *dest); 1426329Sgblack@eecs.umich.edu 1436329Sgblack@eecs.umich.edu void copyMiscRegs(ThreadContext *src, ThreadContext *dest); 1444120Sgblack@eecs.umich.edu}; 1454120Sgblack@eecs.umich.edu 1464120Sgblack@eecs.umich.edu#endif // __ARCH_X86_UTILITY_HH__ 147