utility.hh revision 4194
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IN NO EVENT SHALL THE COPYRIGHT 474120Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 484120Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 494120Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 504120Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 514120Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 524120Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 534120Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 544120Sgblack@eecs.umich.edu * 554120Sgblack@eecs.umich.edu * Authors: Gabe Black 564120Sgblack@eecs.umich.edu */ 574120Sgblack@eecs.umich.edu 584120Sgblack@eecs.umich.edu#ifndef __ARCH_X86_UTILITY_HH__ 594120Sgblack@eecs.umich.edu#define __ARCH_X86_UTILITY_HH__ 604120Sgblack@eecs.umich.edu 614148Sgblack@eecs.umich.edu#include "arch/x86/types.hh" 624148Sgblack@eecs.umich.edu#include "base/misc.hh" 634154Sgblack@eecs.umich.edu#include "sim/host.hh" 644148Sgblack@eecs.umich.edu 654148Sgblack@eecs.umich.educlass ThreadContext; 664120Sgblack@eecs.umich.edu 674120Sgblack@eecs.umich.edunamespace X86ISA 684120Sgblack@eecs.umich.edu{ 694148Sgblack@eecs.umich.edu static inline bool 704148Sgblack@eecs.umich.edu inUserMode(ThreadContext *tc) 714148Sgblack@eecs.umich.edu { 724148Sgblack@eecs.umich.edu return false; 734148Sgblack@eecs.umich.edu } 744148Sgblack@eecs.umich.edu 754148Sgblack@eecs.umich.edu inline ExtMachInst 764148Sgblack@eecs.umich.edu makeExtMI(MachInst inst, ThreadContext * xc) { 774148Sgblack@eecs.umich.edu return inst; 784148Sgblack@eecs.umich.edu } 794148Sgblack@eecs.umich.edu 804148Sgblack@eecs.umich.edu inline bool isCallerSaveIntegerRegister(unsigned int reg) { 814148Sgblack@eecs.umich.edu panic("register classification not implemented"); 824148Sgblack@eecs.umich.edu return false; 834148Sgblack@eecs.umich.edu } 844148Sgblack@eecs.umich.edu 854148Sgblack@eecs.umich.edu inline bool isCalleeSaveIntegerRegister(unsigned int reg) { 864148Sgblack@eecs.umich.edu panic("register classification not implemented"); 874148Sgblack@eecs.umich.edu return false; 884148Sgblack@eecs.umich.edu } 894148Sgblack@eecs.umich.edu 904148Sgblack@eecs.umich.edu inline bool isCallerSaveFloatRegister(unsigned int reg) { 914148Sgblack@eecs.umich.edu panic("register classification not implemented"); 924148Sgblack@eecs.umich.edu return false; 934148Sgblack@eecs.umich.edu } 944148Sgblack@eecs.umich.edu 954148Sgblack@eecs.umich.edu inline bool isCalleeSaveFloatRegister(unsigned int reg) { 964148Sgblack@eecs.umich.edu panic("register classification not implemented"); 974148Sgblack@eecs.umich.edu return false; 984148Sgblack@eecs.umich.edu } 994148Sgblack@eecs.umich.edu 1004148Sgblack@eecs.umich.edu // Instruction address compression hooks 1014148Sgblack@eecs.umich.edu inline Addr realPCToFetchPC(const Addr &addr) 1024148Sgblack@eecs.umich.edu { 1034148Sgblack@eecs.umich.edu return addr; 1044148Sgblack@eecs.umich.edu } 1054148Sgblack@eecs.umich.edu 1064148Sgblack@eecs.umich.edu inline Addr fetchPCToRealPC(const Addr &addr) 1074148Sgblack@eecs.umich.edu { 1084148Sgblack@eecs.umich.edu return addr; 1094148Sgblack@eecs.umich.edu } 1104148Sgblack@eecs.umich.edu 1114148Sgblack@eecs.umich.edu // the size of "fetched" instructions (not necessarily the size 1124148Sgblack@eecs.umich.edu // of real instructions for PISA) 1134148Sgblack@eecs.umich.edu inline size_t fetchInstSize() 1144148Sgblack@eecs.umich.edu { 1154148Sgblack@eecs.umich.edu return sizeof(MachInst); 1164148Sgblack@eecs.umich.edu } 1174148Sgblack@eecs.umich.edu 1184148Sgblack@eecs.umich.edu /** 1194148Sgblack@eecs.umich.edu * Function to insure ISA semantics about 0 registers. 1204148Sgblack@eecs.umich.edu * @param tc The thread context. 1214148Sgblack@eecs.umich.edu */ 1224148Sgblack@eecs.umich.edu template <class TC> 1234148Sgblack@eecs.umich.edu void zeroRegisters(TC *tc); 1244148Sgblack@eecs.umich.edu 1254148Sgblack@eecs.umich.edu inline void initCPU(ThreadContext *tc, int cpuId) 1264148Sgblack@eecs.umich.edu { 1274148Sgblack@eecs.umich.edu panic("initCPU not implemented!\n"); 1284148Sgblack@eecs.umich.edu } 1294194Ssaidi@eecs.umich.edu 1304194Ssaidi@eecs.umich.edu inline void startupCPU(ThreadContext *tc, int cpuId) 1314194Ssaidi@eecs.umich.edu { 1324194Ssaidi@eecs.umich.edu tc->activate(0); 1334194Ssaidi@eecs.umich.edu } 1344120Sgblack@eecs.umich.edu}; 1354120Sgblack@eecs.umich.edu 1364120Sgblack@eecs.umich.edu#endif // __ARCH_X86_UTILITY_HH__ 137