utility.hh revision 4182
14120Sgblack@eecs.umich.edu/* 24120Sgblack@eecs.umich.edu * Copyright (c) 2007 The Hewlett-Packard Development Company 34120Sgblack@eecs.umich.edu * All rights reserved. 44120Sgblack@eecs.umich.edu * 54120Sgblack@eecs.umich.edu * Redistribution and use of this software in source and binary forms, 64120Sgblack@eecs.umich.edu * with or without modification, are permitted provided that the 74120Sgblack@eecs.umich.edu * following conditions are met: 84120Sgblack@eecs.umich.edu * 94120Sgblack@eecs.umich.edu * The software must be used only for Non-Commercial Use which means any 104120Sgblack@eecs.umich.edu * use which is NOT directed to receiving any direct monetary 114120Sgblack@eecs.umich.edu * compensation for, or commercial advantage from such use. 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IN NO EVENT SHALL THE COPYRIGHT 474120Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 484120Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 494120Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 504120Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 514120Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 524120Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 534120Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 544120Sgblack@eecs.umich.edu * 554120Sgblack@eecs.umich.edu * Authors: Gabe Black 564120Sgblack@eecs.umich.edu */ 574120Sgblack@eecs.umich.edu 584120Sgblack@eecs.umich.edu#ifndef __ARCH_X86_UTILITY_HH__ 594120Sgblack@eecs.umich.edu#define __ARCH_X86_UTILITY_HH__ 604120Sgblack@eecs.umich.edu 614148Sgblack@eecs.umich.edu#include "arch/x86/types.hh" 624182Sgblack@eecs.umich.edu#include "base/hashmap.hh" 634148Sgblack@eecs.umich.edu#include "base/misc.hh" 644154Sgblack@eecs.umich.edu#include "sim/host.hh" 654148Sgblack@eecs.umich.edu 664148Sgblack@eecs.umich.educlass ThreadContext; 674120Sgblack@eecs.umich.edu 684182Sgblack@eecs.umich.edunamespace __hash_namespace { 694182Sgblack@eecs.umich.edu template<> 704182Sgblack@eecs.umich.edu struct hash<X86ISA::ExtMachInst> { 714182Sgblack@eecs.umich.edu size_t operator()(const X86ISA::ExtMachInst &emi) const { 724182Sgblack@eecs.umich.edu //Because these are all the same, return 0 734182Sgblack@eecs.umich.edu return 0; 744182Sgblack@eecs.umich.edu }; 754182Sgblack@eecs.umich.edu }; 764182Sgblack@eecs.umich.edu} 774182Sgblack@eecs.umich.edu 784120Sgblack@eecs.umich.edunamespace X86ISA 794120Sgblack@eecs.umich.edu{ 804148Sgblack@eecs.umich.edu static inline bool 814148Sgblack@eecs.umich.edu inUserMode(ThreadContext *tc) 824148Sgblack@eecs.umich.edu { 834148Sgblack@eecs.umich.edu return false; 844148Sgblack@eecs.umich.edu } 854148Sgblack@eecs.umich.edu 864148Sgblack@eecs.umich.edu inline bool isCallerSaveIntegerRegister(unsigned int reg) { 874148Sgblack@eecs.umich.edu panic("register classification not implemented"); 884148Sgblack@eecs.umich.edu return false; 894148Sgblack@eecs.umich.edu } 904148Sgblack@eecs.umich.edu 914148Sgblack@eecs.umich.edu inline bool isCalleeSaveIntegerRegister(unsigned int reg) { 924148Sgblack@eecs.umich.edu panic("register classification not implemented"); 934148Sgblack@eecs.umich.edu return false; 944148Sgblack@eecs.umich.edu } 954148Sgblack@eecs.umich.edu 964148Sgblack@eecs.umich.edu inline bool isCallerSaveFloatRegister(unsigned int reg) { 974148Sgblack@eecs.umich.edu panic("register classification not implemented"); 984148Sgblack@eecs.umich.edu return false; 994148Sgblack@eecs.umich.edu } 1004148Sgblack@eecs.umich.edu 1014148Sgblack@eecs.umich.edu inline bool isCalleeSaveFloatRegister(unsigned int reg) { 1024148Sgblack@eecs.umich.edu panic("register classification not implemented"); 1034148Sgblack@eecs.umich.edu return false; 1044148Sgblack@eecs.umich.edu } 1054148Sgblack@eecs.umich.edu 1064148Sgblack@eecs.umich.edu // Instruction address compression hooks 1074148Sgblack@eecs.umich.edu inline Addr realPCToFetchPC(const Addr &addr) 1084148Sgblack@eecs.umich.edu { 1094148Sgblack@eecs.umich.edu return addr; 1104148Sgblack@eecs.umich.edu } 1114148Sgblack@eecs.umich.edu 1124148Sgblack@eecs.umich.edu inline Addr fetchPCToRealPC(const Addr &addr) 1134148Sgblack@eecs.umich.edu { 1144148Sgblack@eecs.umich.edu return addr; 1154148Sgblack@eecs.umich.edu } 1164148Sgblack@eecs.umich.edu 1174148Sgblack@eecs.umich.edu // the size of "fetched" instructions (not necessarily the size 1184148Sgblack@eecs.umich.edu // of real instructions for PISA) 1194148Sgblack@eecs.umich.edu inline size_t fetchInstSize() 1204148Sgblack@eecs.umich.edu { 1214148Sgblack@eecs.umich.edu return sizeof(MachInst); 1224148Sgblack@eecs.umich.edu } 1234148Sgblack@eecs.umich.edu 1244148Sgblack@eecs.umich.edu /** 1254148Sgblack@eecs.umich.edu * Function to insure ISA semantics about 0 registers. 1264148Sgblack@eecs.umich.edu * @param tc The thread context. 1274148Sgblack@eecs.umich.edu */ 1284148Sgblack@eecs.umich.edu template <class TC> 1294148Sgblack@eecs.umich.edu void zeroRegisters(TC *tc); 1304148Sgblack@eecs.umich.edu 1314148Sgblack@eecs.umich.edu inline void initCPU(ThreadContext *tc, int cpuId) 1324148Sgblack@eecs.umich.edu { 1334148Sgblack@eecs.umich.edu panic("initCPU not implemented!\n"); 1344148Sgblack@eecs.umich.edu } 1354120Sgblack@eecs.umich.edu}; 1364120Sgblack@eecs.umich.edu 1374120Sgblack@eecs.umich.edu#endif // __ARCH_X86_UTILITY_HH__ 138