utility.cc revision 7720:65d338a8dba4 
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include "config/full_system.hh"
41
42#if FULL_SYSTEM
43#include "arch/x86/interrupts.hh"
44#endif
45#include "arch/x86/regs/int.hh"
46#include "arch/x86/regs/misc.hh"
47#include "arch/x86/regs/segment.hh"
48#include "arch/x86/utility.hh"
49#include "arch/x86/x86_traits.hh"
50#include "cpu/base.hh"
51#include "sim/system.hh"
52
53namespace X86ISA {
54
55uint64_t
56getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
57{
58#if FULL_SYSTEM
59    panic("getArgument() not implemented for x86!\n");
60#else
61    panic("getArgument() only implemented for FULL_SYSTEM\n");
62    M5_DUMMY_RETURN
63#endif
64}
65
66# if FULL_SYSTEM
67void initCPU(ThreadContext *tc, int cpuId)
68{
69    // This function is essentially performing a reset. The actual INIT
70    // interrupt does a subset of this, so we'll piggyback on some of its
71    // functionality.
72    InitInterrupt init(0);
73    init.invoke(tc);
74
75    PCState pc = tc->pcState();
76    pc.upc(0);
77    pc.nupc(1);
78    tc->pcState(pc);
79
80    // These next two loops zero internal microcode and implicit registers.
81    // They aren't specified by the ISA but are used internally by M5's
82    // implementation.
83    for (int index = 0; index < NumMicroIntRegs; index++) {
84        tc->setIntReg(INTREG_MICRO(index), 0);
85    }
86
87    for (int index = 0; index < NumImplicitIntRegs; index++) {
88        tc->setIntReg(INTREG_IMPLICIT(index), 0);
89    }
90
91    // Set integer register EAX to 0 to indicate that the optional BIST
92    // passed. No BIST actually runs, but software may still check this
93    // register for errors.
94    tc->setIntReg(INTREG_RAX, 0);
95
96    tc->setMiscReg(MISCREG_CR0, 0x0000000060000010ULL);
97    tc->setMiscReg(MISCREG_CR8, 0);
98
99    // TODO initialize x87, 64 bit, and 128 bit media state
100
101    tc->setMiscReg(MISCREG_MTRRCAP, 0x0508);
102    for (int i = 0; i < 8; i++) {
103        tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0);
104        tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0);
105    }
106    tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0);
107    tc->setMiscReg(MISCREG_MTRR_FIX_16K_80000, 0);
108    tc->setMiscReg(MISCREG_MTRR_FIX_16K_A0000, 0);
109    tc->setMiscReg(MISCREG_MTRR_FIX_4K_C0000, 0);
110    tc->setMiscReg(MISCREG_MTRR_FIX_4K_C8000, 0);
111    tc->setMiscReg(MISCREG_MTRR_FIX_4K_D0000, 0);
112    tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0);
113    tc->setMiscReg(MISCREG_MTRR_FIX_4K_E0000, 0);
114    tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0);
115    tc->setMiscReg(MISCREG_MTRR_FIX_4K_F0000, 0);
116    tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0);
117
118    tc->setMiscReg(MISCREG_DEF_TYPE, 0);
119
120    tc->setMiscReg(MISCREG_MCG_CAP, 0x104);
121    tc->setMiscReg(MISCREG_MCG_STATUS, 0);
122    tc->setMiscReg(MISCREG_MCG_CTL, 0);
123
124    for (int i = 0; i < 5; i++) {
125        tc->setMiscReg(MISCREG_MC_CTL(i), 0);
126        tc->setMiscReg(MISCREG_MC_STATUS(i), 0);
127        tc->setMiscReg(MISCREG_MC_ADDR(i), 0);
128        tc->setMiscReg(MISCREG_MC_MISC(i), 0);
129    }
130
131    tc->setMiscReg(MISCREG_TSC, 0);
132    tc->setMiscReg(MISCREG_TSC_AUX, 0);
133
134    for (int i = 0; i < 4; i++) {
135        tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0);
136        tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0);
137    }
138
139    tc->setMiscReg(MISCREG_STAR, 0);
140    tc->setMiscReg(MISCREG_LSTAR, 0);
141    tc->setMiscReg(MISCREG_CSTAR, 0);
142
143    tc->setMiscReg(MISCREG_SF_MASK, 0);
144
145    tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0);
146
147    tc->setMiscReg(MISCREG_SYSENTER_CS, 0);
148    tc->setMiscReg(MISCREG_SYSENTER_ESP, 0);
149    tc->setMiscReg(MISCREG_SYSENTER_EIP, 0);
150
151    tc->setMiscReg(MISCREG_PAT, 0x0007040600070406ULL);
152
153    tc->setMiscReg(MISCREG_SYSCFG, 0x20601);
154
155    tc->setMiscReg(MISCREG_IORR_BASE0, 0);
156    tc->setMiscReg(MISCREG_IORR_BASE1, 0);
157
158    tc->setMiscReg(MISCREG_IORR_MASK0, 0);
159    tc->setMiscReg(MISCREG_IORR_MASK1, 0);
160
161    tc->setMiscReg(MISCREG_TOP_MEM, 0x4000000);
162    tc->setMiscReg(MISCREG_TOP_MEM2, 0x0);
163
164    tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0);
165    tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0);
166    tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0);
167    tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0);
168    tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0);
169
170    // Invalidate the caches (this should already be done for us)
171
172    LocalApicBase lApicBase = 0;
173    lApicBase.base = 0xFEE00000 >> 12;
174    lApicBase.enable = 1;
175    lApicBase.bsp = (cpuId == 0);
176    tc->setMiscReg(MISCREG_APIC_BASE, lApicBase);
177
178    Interrupts * interrupts = dynamic_cast<Interrupts *>(
179            tc->getCpuPtr()->getInterruptController());
180    assert(interrupts);
181
182    interrupts->setRegNoEffect(APIC_ID, cpuId << 24);
183
184    interrupts->setRegNoEffect(APIC_VERSION, (5 << 16) | 0x14);
185
186    interrupts->setClock(tc->getCpuPtr()->ticks(16));
187
188    // TODO Set the SMRAM base address (SMBASE) to 0x00030000
189
190    tc->setMiscReg(MISCREG_VM_CR, 0);
191    tc->setMiscReg(MISCREG_IGNNE, 0);
192    tc->setMiscReg(MISCREG_SMM_CTL, 0);
193    tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0);
194}
195
196#endif
197
198void startupCPU(ThreadContext *tc, int cpuId)
199{
200#if FULL_SYSTEM
201    if (cpuId == 0) {
202        tc->activate(0);
203    } else {
204        // This is an application processor (AP). It should be initialized to
205        // look like only the BIOS POST has run on it and put then put it into
206        // a halted state.
207        tc->suspend(0);
208    }
209#else
210    tc->activate(0);
211#endif
212}
213
214void
215copyMiscRegs(ThreadContext *src, ThreadContext *dest)
216{
217    warn("copyMiscRegs is naively implemented for x86\n");
218    for (int i = 0; i < NUM_MISCREGS; ++i) {
219        if ( ( i != MISCREG_CR1 &&
220             !(i > MISCREG_CR4 && i < MISCREG_CR8) &&
221             !(i > MISCREG_CR8 && i <= MISCREG_CR15) ) == false) {
222             continue;
223        }
224        dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
225    }
226}
227
228void
229copyRegs(ThreadContext *src, ThreadContext *dest)
230{
231    panic("copyRegs not implemented for x86!\n");
232    //copy int regs
233    //copy float regs
234    copyMiscRegs(src, dest);
235
236    dest->pcState(src->pcState());
237}
238
239void
240skipFunction(ThreadContext *tc)
241{
242    panic("Not implemented for x86\n");
243}
244
245
246} //namespace X86_ISA
247