utility.cc revision 5141:a3b0e3a8b83c 
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use.  Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 *     Director of Intellectual Property Licensing
21 *     Office of Strategy and Technology
22 *     Hewlett-Packard Company
23 *     1501 Page Mill Road
24 *     Palo Alto, California  94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer.  Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution.  Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission.  No right of
34 * sublicense is granted herewith.  Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses.  Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include "arch/x86/intregs.hh"
59#include "arch/x86/miscregs.hh"
60#include "arch/x86/segmentregs.hh"
61#include "arch/x86/utility.hh"
62#include "arch/x86/x86_traits.hh"
63
64namespace X86ISA {
65
66uint64_t getArgument(ThreadContext *tc, int number, bool fp) {
67#if FULL_SYSTEM
68    panic("getArgument() not implemented for x86!\n");
69#else
70    panic("getArgument() only implemented for FULL_SYSTEM\n");
71    M5_DUMMY_RETURN
72#endif
73}
74
75# if FULL_SYSTEM
76void initCPU(ThreadContext *tc, int cpuId)
77{
78    // The otherwise unmodified integer registers should be set to 0.
79    for (int index = 0; index < NUM_INTREGS; index++) {
80        tc->setIntReg(index, 0);
81    }
82
83    // These next two loops zero internal microcode and implicit registers.
84    // They aren't specified by the ISA but are used internally by M5's
85    // implementation.
86    for (int index = 0; index < NumMicroIntRegs; index++) {
87        tc->setIntReg(INTREG_MICRO(index), 0);
88    }
89
90    for (int index = 0; index < NumImplicitIntRegs; index++) {
91        tc->setIntReg(INTREG_IMPLICIT(index), 0);
92    }
93
94    // Set integer register EAX to 0 to indicate that the optional BIST
95    // passed. No BIST actually runs, but software may still check this
96    // register for errors.
97    tc->setIntReg(INTREG_RAX, 0);
98
99    //The following values are dictated by the architecture for after a RESET#
100    tc->setMiscReg(MISCREG_CR0, 0x0000000060000010);
101    tc->setMiscReg(MISCREG_CR2, 0);
102    tc->setMiscReg(MISCREG_CR3, 0);
103    tc->setMiscReg(MISCREG_CR4, 0);
104    tc->setMiscReg(MISCREG_CR8, 0);
105
106    tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002);
107
108    tc->setMiscReg(MISCREG_EFER, 0);
109
110    SegAttr dataAttr = 0;
111    dataAttr.writable = 1;
112    dataAttr.readable = 1;
113    dataAttr.expandDown = 0;
114    dataAttr.dpl = 0;
115    dataAttr.defaultSize = 0;
116
117    for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) {
118        tc->setMiscReg(MISCREG_SEG_SEL(seg), 0);
119        tc->setMiscReg(MISCREG_SEG_BASE(seg), 0);
120        tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff);
121        tc->setMiscReg(MISCREG_SEG_ATTR(seg), dataAttr);
122    }
123
124    SegAttr codeAttr = 0;
125    codeAttr.writable = 0;
126    codeAttr.readable = 1;
127    codeAttr.expandDown = 0;
128    codeAttr.dpl = 0;
129    codeAttr.defaultSize = 0;
130
131    tc->setMiscReg(MISCREG_CS, 0xf000);
132    tc->setMiscReg(MISCREG_CS_BASE, 0x00000000ffff0000);
133    // This has the base value pre-added.
134    tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
135    tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
136
137    tc->setPC(0x000000000000fff0 +
138            tc->readMiscReg(MISCREG_CS_BASE));
139    tc->setNextPC(tc->readPC() + sizeof(MachInst));
140
141    tc->setMiscReg(MISCREG_GDTR_BASE, 0);
142    tc->setMiscReg(MISCREG_GDTR_LIMIT, 0xffff);
143
144    tc->setMiscReg(MISCREG_IDTR_BASE, 0);
145    tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
146
147    tc->setMiscReg(MISCREG_LDTR, 0);
148    tc->setMiscReg(MISCREG_LDTR_BASE, 0);
149    tc->setMiscReg(MISCREG_LDTR_LIMIT, 0xffff);
150    tc->setMiscReg(MISCREG_LDTR_ATTR, 0);
151
152    tc->setMiscReg(MISCREG_TR, 0);
153    tc->setMiscReg(MISCREG_TR_BASE, 0);
154    tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff);
155    tc->setMiscReg(MISCREG_TR_ATTR, 0);
156
157    // This value should be the family/model/stepping of the processor.
158    // (page 418). It should be consistent with the value from CPUID, but the
159    // actual value probably doesn't matter much.
160    tc->setIntReg(INTREG_RDX, 0);
161
162    // TODO initialize x87, 64 bit, and 128 bit media state
163
164    tc->setMiscReg(MISCREG_MTRRCAP, 0x0508);
165    for (int i = 0; i < 8; i++) {
166        tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0);
167        tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0);
168    }
169    tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0);
170    tc->setMiscReg(MISCREG_MTRR_FIX_16K_80000, 0);
171    tc->setMiscReg(MISCREG_MTRR_FIX_16K_A0000, 0);
172    tc->setMiscReg(MISCREG_MTRR_FIX_4K_C0000, 0);
173    tc->setMiscReg(MISCREG_MTRR_FIX_4k_C8000, 0);
174    tc->setMiscReg(MISCREG_MTRR_FIX_4K_D0000, 0);
175    tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0);
176    tc->setMiscReg(MISCREG_MTRR_FIX_4K_E0000, 0);
177    tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0);
178    tc->setMiscReg(MISCREG_MTRR_FIX_4K_F0000, 0);
179    tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0);
180
181    tc->setMiscReg(MISCREG_DEF_TYPE, 0);
182
183    tc->setMiscReg(MISCREG_MCG_CAP, 0x104);
184    tc->setMiscReg(MISCREG_MCG_STATUS, 0);
185    tc->setMiscReg(MISCREG_MCG_CTL, 0);
186
187    for (int i = 0; i < 5; i++) {
188        tc->setMiscReg(MISCREG_MC_CTL(i), 0);
189        tc->setMiscReg(MISCREG_MC_STATUS(i), 0);
190        tc->setMiscReg(MISCREG_MC_ADDR(i), 0);
191        tc->setMiscReg(MISCREG_MC_MISC(i), 0);
192    }
193
194    tc->setMiscReg(MISCREG_DR0, 0);
195    tc->setMiscReg(MISCREG_DR1, 0);
196    tc->setMiscReg(MISCREG_DR2, 0);
197    tc->setMiscReg(MISCREG_DR3, 0);
198
199    tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0);
200    tc->setMiscReg(MISCREG_DR7, 0x0000000000000400);
201
202    tc->setMiscReg(MISCREG_TSC, 0);
203    tc->setMiscReg(MISCREG_TSC_AUX, 0);
204
205    for (int i = 0; i < 4; i++) {
206        tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0);
207        tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0);
208    }
209
210    tc->setMiscReg(MISCREG_STAR, 0);
211    tc->setMiscReg(MISCREG_LSTAR, 0);
212    tc->setMiscReg(MISCREG_CSTAR, 0);
213
214    tc->setMiscReg(MISCREG_SF_MASK, 0);
215
216    tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0);
217
218    tc->setMiscReg(MISCREG_SYSENTER_CS, 0);
219    tc->setMiscReg(MISCREG_SYSENTER_ESP, 0);
220    tc->setMiscReg(MISCREG_SYSENTER_EIP, 0);
221
222    tc->setMiscReg(MISCREG_PAT, 0x0007040600070406);
223
224    tc->setMiscReg(MISCREG_SYSCFG, 0x20601);
225
226    tc->setMiscReg(MISCREG_IORR_BASE0, 0);
227    tc->setMiscReg(MISCREG_IORR_BASE1, 0);
228
229    tc->setMiscReg(MISCREG_IORR_MASK0, 0);
230    tc->setMiscReg(MISCREG_IORR_MASK1, 0);
231
232    tc->setMiscReg(MISCREG_TOP_MEM, 0x4000000);
233    tc->setMiscReg(MISCREG_TOP_MEM2, 0x0);
234
235    tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0);
236    tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0);
237    tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0);
238    tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0);
239    tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0);
240
241    // Invalidate the caches (this should already be done for us)
242
243    // TODO Turn on the APIC. This should be handled elsewhere but it isn't
244    // currently being handled at all.
245
246    // TODO Set the SMRAM base address (SMBASE) to 0x00030000
247
248    tc->setMiscReg(MISCREG_VM_CR, 0);
249    tc->setMiscReg(MISCREG_IGNNE, 0);
250    tc->setMiscReg(MISCREG_SMM_CTL, 0);
251    tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0);
252}
253
254#endif
255
256void startupCPU(ThreadContext *tc, int cpuId)
257{
258    if (cpuId == 0) {
259        // This is the boot strap processor (BSP). Initialize it to look like
260        // the boot loader has just turned control over to the 64 bit OS.
261
262        // Enable paging, turn on long mode, etc.
263
264        tc->activate(0);
265    } else {
266        // This is an application processor (AP). It should be initialized to
267        // look like only the BIOS POST has run on it and put then put it into
268        // a halted state.
269    }
270}
271
272} //namespace X86_ISA
273