utility.cc revision 11793 
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * Copyright (c) 2011 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are
17 * met: redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer;
19 * redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution;
22 * neither the name of the copyright holders nor the names of its
23 * contributors may be used to endorse or promote products derived from
24 * this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * Authors: Gabe Black
39 */
40
41#include "arch/x86/utility.hh"
42
43#include "arch/x86/interrupts.hh"
44#include "arch/x86/registers.hh"
45#include "arch/x86/tlb.hh"
46#include "arch/x86/x86_traits.hh"
47#include "cpu/base.hh"
48#include "fputils/fp80.h"
49#include "sim/system.hh"
50
51namespace X86ISA {
52
53uint64_t
54getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
55{
56    if (fp) {
57        panic("getArgument(): Floating point arguments not implemented\n");
58    } else if (size != 8) {
59        panic("getArgument(): Can only handle 64-bit arguments.\n");
60    }
61
62    // The first 6 integer arguments are passed in registers, the rest
63    // are passed on the stack.
64    const int int_reg_map[] = {
65        INTREG_RDI, INTREG_RSI, INTREG_RDX,
66        INTREG_RCX, INTREG_R8, INTREG_R9
67    };
68    if (number < sizeof(int_reg_map) / sizeof(*int_reg_map)) {
69        return tc->readIntReg(int_reg_map[number]);
70    } else {
71        panic("getArgument(): Don't know how to handle stack arguments.\n");
72    }
73}
74
75void initCPU(ThreadContext *tc, int cpuId)
76{
77    // This function is essentially performing a reset. The actual INIT
78    // interrupt does a subset of this, so we'll piggyback on some of its
79    // functionality.
80    InitInterrupt init(0);
81    init.invoke(tc);
82
83    PCState pc = tc->pcState();
84    pc.upc(0);
85    pc.nupc(1);
86    tc->pcState(pc);
87
88    // These next two loops zero internal microcode and implicit registers.
89    // They aren't specified by the ISA but are used internally by M5's
90    // implementation.
91    for (int index = 0; index < NumMicroIntRegs; index++) {
92        tc->setIntReg(INTREG_MICRO(index), 0);
93    }
94
95    for (int index = 0; index < NumImplicitIntRegs; index++) {
96        tc->setIntReg(INTREG_IMPLICIT(index), 0);
97    }
98
99    // Set integer register EAX to 0 to indicate that the optional BIST
100    // passed. No BIST actually runs, but software may still check this
101    // register for errors.
102    tc->setIntReg(INTREG_RAX, 0);
103
104    tc->setMiscReg(MISCREG_CR0, 0x0000000060000010ULL);
105    tc->setMiscReg(MISCREG_CR8, 0);
106
107    // TODO initialize x87, 64 bit, and 128 bit media state
108
109    tc->setMiscReg(MISCREG_MTRRCAP, 0x0508);
110    for (int i = 0; i < 8; i++) {
111        tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0);
112        tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0);
113    }
114    tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0);
115    tc->setMiscReg(MISCREG_MTRR_FIX_16K_80000, 0);
116    tc->setMiscReg(MISCREG_MTRR_FIX_16K_A0000, 0);
117    tc->setMiscReg(MISCREG_MTRR_FIX_4K_C0000, 0);
118    tc->setMiscReg(MISCREG_MTRR_FIX_4K_C8000, 0);
119    tc->setMiscReg(MISCREG_MTRR_FIX_4K_D0000, 0);
120    tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0);
121    tc->setMiscReg(MISCREG_MTRR_FIX_4K_E0000, 0);
122    tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0);
123    tc->setMiscReg(MISCREG_MTRR_FIX_4K_F0000, 0);
124    tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0);
125
126    tc->setMiscReg(MISCREG_DEF_TYPE, 0);
127
128    tc->setMiscReg(MISCREG_MCG_CAP, 0x104);
129    tc->setMiscReg(MISCREG_MCG_STATUS, 0);
130    tc->setMiscReg(MISCREG_MCG_CTL, 0);
131
132    for (int i = 0; i < 5; i++) {
133        tc->setMiscReg(MISCREG_MC_CTL(i), 0);
134        tc->setMiscReg(MISCREG_MC_STATUS(i), 0);
135        tc->setMiscReg(MISCREG_MC_ADDR(i), 0);
136        tc->setMiscReg(MISCREG_MC_MISC(i), 0);
137    }
138
139    tc->setMiscReg(MISCREG_TSC, 0);
140    tc->setMiscReg(MISCREG_TSC_AUX, 0);
141
142    for (int i = 0; i < 4; i++) {
143        tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0);
144        tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0);
145    }
146
147    tc->setMiscReg(MISCREG_STAR, 0);
148    tc->setMiscReg(MISCREG_LSTAR, 0);
149    tc->setMiscReg(MISCREG_CSTAR, 0);
150
151    tc->setMiscReg(MISCREG_SF_MASK, 0);
152
153    tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0);
154
155    tc->setMiscReg(MISCREG_SYSENTER_CS, 0);
156    tc->setMiscReg(MISCREG_SYSENTER_ESP, 0);
157    tc->setMiscReg(MISCREG_SYSENTER_EIP, 0);
158
159    tc->setMiscReg(MISCREG_PAT, 0x0007040600070406ULL);
160
161    tc->setMiscReg(MISCREG_SYSCFG, 0x20601);
162
163    tc->setMiscReg(MISCREG_IORR_BASE0, 0);
164    tc->setMiscReg(MISCREG_IORR_BASE1, 0);
165
166    tc->setMiscReg(MISCREG_IORR_MASK0, 0);
167    tc->setMiscReg(MISCREG_IORR_MASK1, 0);
168
169    tc->setMiscReg(MISCREG_TOP_MEM, 0x4000000);
170    tc->setMiscReg(MISCREG_TOP_MEM2, 0x0);
171
172    tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0);
173    tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0);
174    tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0);
175    tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0);
176    tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0);
177
178    // Invalidate the caches (this should already be done for us)
179
180    LocalApicBase lApicBase = 0;
181    lApicBase.base = 0xFEE00000 >> 12;
182    lApicBase.enable = 1;
183    lApicBase.bsp = (cpuId == 0);
184    tc->setMiscReg(MISCREG_APIC_BASE, lApicBase);
185
186    Interrupts * interrupts = dynamic_cast<Interrupts *>(
187            tc->getCpuPtr()->getInterruptController(0));
188    assert(interrupts);
189
190    interrupts->setRegNoEffect(APIC_ID, cpuId << 24);
191
192    interrupts->setRegNoEffect(APIC_VERSION, (5 << 16) | 0x14);
193
194    // TODO Set the SMRAM base address (SMBASE) to 0x00030000
195
196    tc->setMiscReg(MISCREG_VM_CR, 0);
197    tc->setMiscReg(MISCREG_IGNNE, 0);
198    tc->setMiscReg(MISCREG_SMM_CTL, 0);
199    tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0);
200}
201
202void startupCPU(ThreadContext *tc, int cpuId)
203{
204    if (cpuId == 0 || !FullSystem) {
205        tc->activate();
206    } else {
207        // This is an application processor (AP). It should be initialized to
208        // look like only the BIOS POST has run on it and put then put it into
209        // a halted state.
210        tc->suspend();
211    }
212}
213
214void
215copyMiscRegs(ThreadContext *src, ThreadContext *dest)
216{
217    // This function assumes no side effects other than TLB invalidation
218    // need to be considered while copying state. That will likely not be
219    // true in the future.
220    for (int i = 0; i < NUM_MISCREGS; ++i) {
221        if (!isValidMiscReg(i))
222             continue;
223
224        dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
225    }
226
227    // The TSC has to be updated with side-effects if the CPUs in a
228    // CPU switch have different frequencies.
229    dest->setMiscReg(MISCREG_TSC, src->readMiscReg(MISCREG_TSC));
230
231    dest->getITBPtr()->flushAll();
232    dest->getDTBPtr()->flushAll();
233}
234
235void
236copyRegs(ThreadContext *src, ThreadContext *dest)
237{
238    //copy int regs
239    for (int i = 0; i < NumIntRegs; ++i)
240         dest->setIntRegFlat(i, src->readIntRegFlat(i));
241    //copy float regs
242    for (int i = 0; i < NumFloatRegs; ++i)
243         dest->setFloatRegBitsFlat(i, src->readFloatRegBitsFlat(i));
244    //copy condition-code regs
245    for (int i = 0; i < NumCCRegs; ++i)
246         dest->setCCRegFlat(i, src->readCCRegFlat(i));
247    copyMiscRegs(src, dest);
248    dest->pcState(src->pcState());
249}
250
251void
252skipFunction(ThreadContext *tc)
253{
254    panic("Not implemented for x86\n");
255}
256
257uint64_t
258getRFlags(ThreadContext *tc)
259{
260    const uint64_t ncc_flags(tc->readMiscRegNoEffect(MISCREG_RFLAGS));
261    const uint64_t cc_flags(tc->readCCReg(X86ISA::CCREG_ZAPS));
262    const uint64_t cfof_bits(tc->readCCReg(X86ISA::CCREG_CFOF));
263    const uint64_t df_bit(tc->readCCReg(X86ISA::CCREG_DF));
264    // ecf (PSEUDO(3)) & ezf (PSEUDO(4)) are only visible to
265    // microcode, so we can safely ignore them.
266
267    // Reconstruct the real rflags state, mask out internal flags, and
268    // make sure reserved bits have the expected values.
269    return ((ncc_flags | cc_flags | cfof_bits | df_bit) & 0x3F7FD5)
270        | 0x2;
271}
272
273void
274setRFlags(ThreadContext *tc, uint64_t val)
275{
276    tc->setCCReg(X86ISA::CCREG_ZAPS, val & ccFlagMask);
277    tc->setCCReg(X86ISA::CCREG_CFOF, val & cfofMask);
278    tc->setCCReg(X86ISA::CCREG_DF, val & DFBit);
279
280    // Internal microcode registers (ECF & EZF)
281    tc->setCCReg(X86ISA::CCREG_ECF, 0);
282    tc->setCCReg(X86ISA::CCREG_EZF, 0);
283
284    // Update the RFLAGS misc reg with whatever didn't go into the
285    // magic registers.
286    tc->setMiscReg(MISCREG_RFLAGS, val & ~(ccFlagMask | cfofMask | DFBit));
287}
288
289uint8_t
290convX87TagsToXTags(uint16_t ftw)
291{
292    uint8_t ftwx(0);
293    for (int i = 0; i < 8; ++i) {
294        // Extract the tag for the current element on the FP stack
295        const unsigned tag((ftw >> (2 * i)) & 0x3);
296
297        /*
298         * Check the type of the current FP element. Valid values are:
299         * 0 == Valid
300         * 1 == Zero
301         * 2 == Special (Nan, unsupported, infinity, denormal)
302         * 3 == Empty
303         */
304        // The xsave version of the tag word only keeps track of
305        // whether the element is empty or not. Set the corresponding
306        // bit in the ftwx if it's not empty,
307        if (tag != 0x3)
308            ftwx |= 1 << i;
309    }
310
311    return ftwx;
312}
313
314uint16_t
315convX87XTagsToTags(uint8_t ftwx)
316{
317    uint16_t ftw(0);
318    for (int i = 0; i < 8; ++i) {
319        const unsigned xtag(((ftwx >> i) & 0x1));
320
321        // The xtag for an x87 stack position is 0 for empty stack positions.
322        if (!xtag) {
323            // Set the tag word to 3 (empty) for the current element.
324            ftw |= 0x3 << (2 * i);
325        } else {
326            // TODO: We currently assume that non-empty elements are
327            // valid (0x0), but we should ideally reconstruct the full
328            // state (valid/zero/special).
329        }
330    }
331
332    return ftw;
333}
334
335uint16_t
336genX87Tags(uint16_t ftw, uint8_t top, int8_t spm)
337{
338    const uint8_t new_top((top + spm + 8) % 8);
339
340    if (spm > 0) {
341        // Removing elements from the stack. Flag the elements as empty.
342        for (int i = top; i != new_top; i = (i + 1 + 8) % 8)
343            ftw |= 0x3 << (2 * i);
344    } else if (spm < 0) {
345        // Adding elements to the stack. Flag the new elements as
346        // valid. We should ideally decode them and "do the right
347        // thing".
348        for (int i = new_top; i != top; i = (i + 1 + 8) % 8)
349            ftw &= ~(0x3 << (2 * i));
350    }
351
352    return ftw;
353}
354
355double
356loadFloat80(const void *_mem)
357{
358    fp80_t fp80;
359    memcpy(fp80.bits, _mem, 10);
360
361    return fp80_cvtd(fp80);
362}
363
364void
365storeFloat80(void *_mem, double value)
366{
367    fp80_t fp80 = fp80_cvfd(value);
368    memcpy(_mem, fp80.bits, 10);
369}
370
371} // namespace X86_ISA
372