utility.cc revision 10057 
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * Copyright (c) 2011 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are
17 * met: redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer;
19 * redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution;
22 * neither the name of the copyright holders nor the names of its
23 * contributors may be used to endorse or promote products derived from
24 * this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * Authors: Gabe Black
39 */
40
41#include "arch/x86/interrupts.hh"
42#include "arch/x86/registers.hh"
43#include "arch/x86/tlb.hh"
44#include "arch/x86/utility.hh"
45#include "arch/x86/x86_traits.hh"
46#include "cpu/base.hh"
47#include "fputils/fp80.h"
48#include "sim/system.hh"
49
50namespace X86ISA {
51
52uint64_t
53getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
54{
55    if (!FullSystem) {
56        panic("getArgument() only implemented for full system mode.\n");
57    } else if (fp) {
58        panic("getArgument(): Floating point arguments not implemented\n");
59    } else if (size != 8) {
60        panic("getArgument(): Can only handle 64-bit arguments.\n");
61    }
62
63    // The first 6 integer arguments are passed in registers, the rest
64    // are passed on the stack.
65    const int int_reg_map[] = {
66        INTREG_RDI, INTREG_RSI, INTREG_RDX,
67        INTREG_RCX, INTREG_R8, INTREG_R9
68    };
69    if (number < sizeof(int_reg_map) / sizeof(*int_reg_map)) {
70        return tc->readIntReg(int_reg_map[number]);
71    } else {
72        panic("getArgument(): Don't know how to handle stack arguments.\n");
73    }
74}
75
76void initCPU(ThreadContext *tc, int cpuId)
77{
78    // This function is essentially performing a reset. The actual INIT
79    // interrupt does a subset of this, so we'll piggyback on some of its
80    // functionality.
81    InitInterrupt init(0);
82    init.invoke(tc);
83
84    PCState pc = tc->pcState();
85    pc.upc(0);
86    pc.nupc(1);
87    tc->pcState(pc);
88
89    // These next two loops zero internal microcode and implicit registers.
90    // They aren't specified by the ISA but are used internally by M5's
91    // implementation.
92    for (int index = 0; index < NumMicroIntRegs; index++) {
93        tc->setIntReg(INTREG_MICRO(index), 0);
94    }
95
96    for (int index = 0; index < NumImplicitIntRegs; index++) {
97        tc->setIntReg(INTREG_IMPLICIT(index), 0);
98    }
99
100    // Set integer register EAX to 0 to indicate that the optional BIST
101    // passed. No BIST actually runs, but software may still check this
102    // register for errors.
103    tc->setIntReg(INTREG_RAX, 0);
104
105    tc->setMiscReg(MISCREG_CR0, 0x0000000060000010ULL);
106    tc->setMiscReg(MISCREG_CR8, 0);
107
108    // TODO initialize x87, 64 bit, and 128 bit media state
109
110    tc->setMiscReg(MISCREG_MTRRCAP, 0x0508);
111    for (int i = 0; i < 8; i++) {
112        tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0);
113        tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0);
114    }
115    tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0);
116    tc->setMiscReg(MISCREG_MTRR_FIX_16K_80000, 0);
117    tc->setMiscReg(MISCREG_MTRR_FIX_16K_A0000, 0);
118    tc->setMiscReg(MISCREG_MTRR_FIX_4K_C0000, 0);
119    tc->setMiscReg(MISCREG_MTRR_FIX_4K_C8000, 0);
120    tc->setMiscReg(MISCREG_MTRR_FIX_4K_D0000, 0);
121    tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0);
122    tc->setMiscReg(MISCREG_MTRR_FIX_4K_E0000, 0);
123    tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0);
124    tc->setMiscReg(MISCREG_MTRR_FIX_4K_F0000, 0);
125    tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0);
126
127    tc->setMiscReg(MISCREG_DEF_TYPE, 0);
128
129    tc->setMiscReg(MISCREG_MCG_CAP, 0x104);
130    tc->setMiscReg(MISCREG_MCG_STATUS, 0);
131    tc->setMiscReg(MISCREG_MCG_CTL, 0);
132
133    for (int i = 0; i < 5; i++) {
134        tc->setMiscReg(MISCREG_MC_CTL(i), 0);
135        tc->setMiscReg(MISCREG_MC_STATUS(i), 0);
136        tc->setMiscReg(MISCREG_MC_ADDR(i), 0);
137        tc->setMiscReg(MISCREG_MC_MISC(i), 0);
138    }
139
140    tc->setMiscReg(MISCREG_TSC, 0);
141    tc->setMiscReg(MISCREG_TSC_AUX, 0);
142
143    for (int i = 0; i < 4; i++) {
144        tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0);
145        tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0);
146    }
147
148    tc->setMiscReg(MISCREG_STAR, 0);
149    tc->setMiscReg(MISCREG_LSTAR, 0);
150    tc->setMiscReg(MISCREG_CSTAR, 0);
151
152    tc->setMiscReg(MISCREG_SF_MASK, 0);
153
154    tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0);
155
156    tc->setMiscReg(MISCREG_SYSENTER_CS, 0);
157    tc->setMiscReg(MISCREG_SYSENTER_ESP, 0);
158    tc->setMiscReg(MISCREG_SYSENTER_EIP, 0);
159
160    tc->setMiscReg(MISCREG_PAT, 0x0007040600070406ULL);
161
162    tc->setMiscReg(MISCREG_SYSCFG, 0x20601);
163
164    tc->setMiscReg(MISCREG_IORR_BASE0, 0);
165    tc->setMiscReg(MISCREG_IORR_BASE1, 0);
166
167    tc->setMiscReg(MISCREG_IORR_MASK0, 0);
168    tc->setMiscReg(MISCREG_IORR_MASK1, 0);
169
170    tc->setMiscReg(MISCREG_TOP_MEM, 0x4000000);
171    tc->setMiscReg(MISCREG_TOP_MEM2, 0x0);
172
173    tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0);
174    tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0);
175    tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0);
176    tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0);
177    tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0);
178
179    // Invalidate the caches (this should already be done for us)
180
181    LocalApicBase lApicBase = 0;
182    lApicBase.base = 0xFEE00000 >> 12;
183    lApicBase.enable = 1;
184    lApicBase.bsp = (cpuId == 0);
185    tc->setMiscReg(MISCREG_APIC_BASE, lApicBase);
186
187    Interrupts * interrupts = dynamic_cast<Interrupts *>(
188            tc->getCpuPtr()->getInterruptController());
189    assert(interrupts);
190
191    interrupts->setRegNoEffect(APIC_ID, cpuId << 24);
192
193    interrupts->setRegNoEffect(APIC_VERSION, (5 << 16) | 0x14);
194
195    // TODO Set the SMRAM base address (SMBASE) to 0x00030000
196
197    tc->setMiscReg(MISCREG_VM_CR, 0);
198    tc->setMiscReg(MISCREG_IGNNE, 0);
199    tc->setMiscReg(MISCREG_SMM_CTL, 0);
200    tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0);
201}
202
203void startupCPU(ThreadContext *tc, int cpuId)
204{
205    if (cpuId == 0 || !FullSystem) {
206        tc->activate(Cycles(0));
207    } else {
208        // This is an application processor (AP). It should be initialized to
209        // look like only the BIOS POST has run on it and put then put it into
210        // a halted state.
211        tc->suspend(Cycles(0));
212    }
213}
214
215void
216copyMiscRegs(ThreadContext *src, ThreadContext *dest)
217{
218    // This function assumes no side effects other than TLB invalidation
219    // need to be considered while copying state. That will likely not be
220    // true in the future.
221    for (int i = 0; i < NUM_MISCREGS; ++i) {
222        if ( ( i != MISCREG_CR1 &&
223             !(i > MISCREG_CR4 && i < MISCREG_CR8) &&
224             !(i > MISCREG_CR8 && i <= MISCREG_CR15) ) == false) {
225             continue;
226        }
227        dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
228    }
229
230    // The TSC has to be updated with side-effects if the CPUs in a
231    // CPU switch have different frequencies.
232    dest->setMiscReg(MISCREG_TSC, src->readMiscReg(MISCREG_TSC));
233
234    dest->getITBPtr()->flushAll();
235    dest->getDTBPtr()->flushAll();
236}
237
238void
239copyRegs(ThreadContext *src, ThreadContext *dest)
240{
241    //copy int regs
242    for (int i = 0; i < NumIntRegs; ++i)
243         dest->setIntReg(i, src->readIntReg(i));
244    //copy float regs
245    for (int i = 0; i < NumFloatRegs; ++i)
246         dest->setFloatRegBits(i, src->readFloatRegBits(i));
247    //copy condition-code regs
248    for (int i = 0; i < NumCCRegs; ++i)
249         dest->setCCReg(i, src->readCCReg(i));
250    copyMiscRegs(src, dest);
251    dest->pcState(src->pcState());
252}
253
254void
255skipFunction(ThreadContext *tc)
256{
257    panic("Not implemented for x86\n");
258}
259
260uint64_t
261getRFlags(ThreadContext *tc)
262{
263    const uint64_t ncc_flags(tc->readMiscRegNoEffect(MISCREG_RFLAGS));
264    const uint64_t cc_flags(tc->readCCReg(X86ISA::CCREG_ZAPS));
265    const uint64_t cfof_bits(tc->readCCReg(X86ISA::CCREG_CFOF));
266    const uint64_t df_bit(tc->readCCReg(X86ISA::CCREG_DF));
267    // ecf (PSEUDO(3)) & ezf (PSEUDO(4)) are only visible to
268    // microcode, so we can safely ignore them.
269
270    // Reconstruct the real rflags state, mask out internal flags, and
271    // make sure reserved bits have the expected values.
272    return ((ncc_flags | cc_flags | cfof_bits | df_bit) & 0x3F7FD5)
273        | 0x2;
274}
275
276void
277setRFlags(ThreadContext *tc, uint64_t val)
278{
279    tc->setCCReg(X86ISA::CCREG_ZAPS, val & ccFlagMask);
280    tc->setCCReg(X86ISA::CCREG_CFOF, val & cfofMask);
281    tc->setCCReg(X86ISA::CCREG_DF, val & DFBit);
282
283    // Internal microcode registers (ECF & EZF)
284    tc->setCCReg(X86ISA::CCREG_ECF, 0);
285    tc->setCCReg(X86ISA::CCREG_EZF, 0);
286
287    // Update the RFLAGS misc reg with whatever didn't go into the
288    // magic registers.
289    tc->setMiscReg(MISCREG_RFLAGS, val & ~(ccFlagMask | cfofMask | DFBit));
290}
291
292uint8_t
293convX87TagsToXTags(uint16_t ftw)
294{
295    uint8_t ftwx(0);
296    for (int i = 0; i < 8; ++i) {
297        // Extract the tag for the current element on the FP stack
298        const unsigned tag((ftw >> (2 * i)) & 0x3);
299
300        /*
301         * Check the type of the current FP element. Valid values are:
302         * 0 == Valid
303         * 1 == Zero
304         * 2 == Special (Nan, unsupported, infinity, denormal)
305         * 3 == Empty
306         */
307        // The xsave version of the tag word only keeps track of
308        // whether the element is empty or not. Set the corresponding
309        // bit in the ftwx if it's not empty,
310        if (tag != 0x3)
311            ftwx |= 1 << i;
312    }
313
314    return ftwx;
315}
316
317uint16_t
318convX87XTagsToTags(uint8_t ftwx)
319{
320    uint16_t ftw(0);
321    for (int i = 0; i < 8; ++i) {
322        const unsigned xtag(((ftwx >> i) & 0x1));
323
324        // The xtag for an x87 stack position is 0 for empty stack positions.
325        if (!xtag) {
326            // Set the tag word to 3 (empty) for the current element.
327            ftw |= 0x3 << (2 * i);
328        } else {
329            // TODO: We currently assume that non-empty elements are
330            // valid (0x0), but we should ideally reconstruct the full
331            // state (valid/zero/special).
332        }
333    }
334
335    return ftw;
336}
337
338uint16_t
339genX87Tags(uint16_t ftw, uint8_t top, int8_t spm)
340{
341    const uint8_t new_top((top + spm + 8) % 8);
342
343    if (spm > 0) {
344        // Removing elements from the stack. Flag the elements as empty.
345        for (int i = top; i != new_top; i = (i + 1 + 8) % 8)
346            ftw |= 0x3 << (2 * i);
347    } else if (spm < 0) {
348        // Adding elements to the stack. Flag the new elements as
349        // valid. We should ideally decode them and "do the right
350        // thing".
351        for (int i = new_top; i != top; i = (i + 1 + 8) % 8)
352            ftw &= ~(0x3 << (2 * i));
353    }
354
355    return ftw;
356}
357
358double
359loadFloat80(const void *_mem)
360{
361    const fp80_t *fp80((const fp80_t *)_mem);
362
363    return fp80_cvtd(*fp80);
364}
365
366void
367storeFloat80(void *_mem, double value)
368{
369    fp80_t *fp80((fp80_t *)_mem);
370
371    *fp80 = fp80_cvfd(value);
372}
373
374} // namespace X86_ISA
375