utility.cc revision 9180
15086Sgblack@eecs.umich.edu/*
25086Sgblack@eecs.umich.edu * Copyright (c) 2007 The Hewlett-Packard Development Company
38466Snilay@cs.wisc.edu * Copyright (c) 2011 Advanced Micro Devices, Inc.
45086Sgblack@eecs.umich.edu * All rights reserved.
55086Sgblack@eecs.umich.edu *
67087Snate@binkert.org * The license below extends only to copyright in the software and shall
77087Snate@binkert.org * not be construed as granting a license to any other intellectual
87087Snate@binkert.org * property including but not limited to intellectual property relating
97087Snate@binkert.org * to a hardware implementation of the functionality of the software
107087Snate@binkert.org * licensed hereunder.  You may use the software subject to the license
117087Snate@binkert.org * terms below provided that you ensure that this notice is replicated
127087Snate@binkert.org * unmodified and in its entirety in all distributions of the software,
137087Snate@binkert.org * modified or unmodified, in source code or in binary form.
145086Sgblack@eecs.umich.edu *
157087Snate@binkert.org * Redistribution and use in source and binary forms, with or without
167087Snate@binkert.org * modification, are permitted provided that the following conditions are
177087Snate@binkert.org * met: redistributions of source code must retain the above copyright
187087Snate@binkert.org * notice, this list of conditions and the following disclaimer;
197087Snate@binkert.org * redistributions in binary form must reproduce the above copyright
207087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the
217087Snate@binkert.org * documentation and/or other materials provided with the distribution;
227087Snate@binkert.org * neither the name of the copyright holders nor the names of its
235086Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from
247087Snate@binkert.org * this software without specific prior written permission.
255086Sgblack@eecs.umich.edu *
265086Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
275086Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
285086Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
295086Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
305086Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
315086Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
325086Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
335086Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
345086Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
355086Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
365086Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
375086Sgblack@eecs.umich.edu *
385086Sgblack@eecs.umich.edu * Authors: Gabe Black
395086Sgblack@eecs.umich.edu */
405086Sgblack@eecs.umich.edu
415647Sgblack@eecs.umich.edu#include "arch/x86/interrupts.hh"
428466Snilay@cs.wisc.edu#include "arch/x86/registers.hh"
438466Snilay@cs.wisc.edu#include "arch/x86/tlb.hh"
445086Sgblack@eecs.umich.edu#include "arch/x86/utility.hh"
455135Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh"
465647Sgblack@eecs.umich.edu#include "cpu/base.hh"
475234Sgblack@eecs.umich.edu#include "sim/system.hh"
485086Sgblack@eecs.umich.edu
495086Sgblack@eecs.umich.edunamespace X86ISA {
505086Sgblack@eecs.umich.edu
517707Sgblack@eecs.umich.eduuint64_t
527707Sgblack@eecs.umich.edugetArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
537707Sgblack@eecs.umich.edu{
545086Sgblack@eecs.umich.edu    panic("getArgument() not implemented for x86!\n");
555086Sgblack@eecs.umich.edu    M5_DUMMY_RETURN
565086Sgblack@eecs.umich.edu}
575135Sgblack@eecs.umich.edu
585135Sgblack@eecs.umich.eduvoid initCPU(ThreadContext *tc, int cpuId)
595135Sgblack@eecs.umich.edu{
606048Sgblack@eecs.umich.edu    // This function is essentially performing a reset. The actual INIT
616048Sgblack@eecs.umich.edu    // interrupt does a subset of this, so we'll piggyback on some of its
626048Sgblack@eecs.umich.edu    // functionality.
636048Sgblack@eecs.umich.edu    InitInterrupt init(0);
646048Sgblack@eecs.umich.edu    init.invoke(tc);
656048Sgblack@eecs.umich.edu
667720Sgblack@eecs.umich.edu    PCState pc = tc->pcState();
677720Sgblack@eecs.umich.edu    pc.upc(0);
687720Sgblack@eecs.umich.edu    pc.nupc(1);
697720Sgblack@eecs.umich.edu    tc->pcState(pc);
705135Sgblack@eecs.umich.edu
715135Sgblack@eecs.umich.edu    // These next two loops zero internal microcode and implicit registers.
725135Sgblack@eecs.umich.edu    // They aren't specified by the ISA but are used internally by M5's
735135Sgblack@eecs.umich.edu    // implementation.
745135Sgblack@eecs.umich.edu    for (int index = 0; index < NumMicroIntRegs; index++) {
755135Sgblack@eecs.umich.edu        tc->setIntReg(INTREG_MICRO(index), 0);
765135Sgblack@eecs.umich.edu    }
775135Sgblack@eecs.umich.edu
785135Sgblack@eecs.umich.edu    for (int index = 0; index < NumImplicitIntRegs; index++) {
795135Sgblack@eecs.umich.edu        tc->setIntReg(INTREG_IMPLICIT(index), 0);
805135Sgblack@eecs.umich.edu    }
815135Sgblack@eecs.umich.edu
825135Sgblack@eecs.umich.edu    // Set integer register EAX to 0 to indicate that the optional BIST
835135Sgblack@eecs.umich.edu    // passed. No BIST actually runs, but software may still check this
845135Sgblack@eecs.umich.edu    // register for errors.
855135Sgblack@eecs.umich.edu    tc->setIntReg(INTREG_RAX, 0);
865135Sgblack@eecs.umich.edu
875264Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_CR0, 0x0000000060000010ULL);
885135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_CR8, 0);
895135Sgblack@eecs.umich.edu
905135Sgblack@eecs.umich.edu    // TODO initialize x87, 64 bit, and 128 bit media state
915135Sgblack@eecs.umich.edu
925141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRRCAP, 0x0508);
935141Sgblack@eecs.umich.edu    for (int i = 0; i < 8; i++) {
945141Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0);
955141Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0);
965141Sgblack@eecs.umich.edu    }
975141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0);
985141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_16K_80000, 0);
995141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_16K_A0000, 0);
1005141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_4K_C0000, 0);
1015182Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_4K_C8000, 0);
1025141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_4K_D0000, 0);
1035141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0);
1045141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_4K_E0000, 0);
1055141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0);
1065141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_4K_F0000, 0);
1075141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0);
1085135Sgblack@eecs.umich.edu
1095141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_DEF_TYPE, 0);
1105141Sgblack@eecs.umich.edu
1115141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MCG_CAP, 0x104);
1125141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MCG_STATUS, 0);
1135141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MCG_CTL, 0);
1145141Sgblack@eecs.umich.edu
1155141Sgblack@eecs.umich.edu    for (int i = 0; i < 5; i++) {
1165141Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_MC_CTL(i), 0);
1175141Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_MC_STATUS(i), 0);
1185141Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_MC_ADDR(i), 0);
1195141Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_MC_MISC(i), 0);
1205141Sgblack@eecs.umich.edu    }
1215135Sgblack@eecs.umich.edu
1225141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TSC, 0);
1235141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TSC_AUX, 0);
1245135Sgblack@eecs.umich.edu
1255141Sgblack@eecs.umich.edu    for (int i = 0; i < 4; i++) {
1265141Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0);
1275141Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0);
1285141Sgblack@eecs.umich.edu    }
1295135Sgblack@eecs.umich.edu
1305141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_STAR, 0);
1315141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_LSTAR, 0);
1325141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_CSTAR, 0);
1335141Sgblack@eecs.umich.edu
1345141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_SF_MASK, 0);
1355141Sgblack@eecs.umich.edu
1365141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0);
1375141Sgblack@eecs.umich.edu
1385141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_SYSENTER_CS, 0);
1395141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_SYSENTER_ESP, 0);
1405141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_SYSENTER_EIP, 0);
1415141Sgblack@eecs.umich.edu
1425264Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_PAT, 0x0007040600070406ULL);
1435141Sgblack@eecs.umich.edu
1445141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_SYSCFG, 0x20601);
1455141Sgblack@eecs.umich.edu
1465141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_IORR_BASE0, 0);
1475141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_IORR_BASE1, 0);
1485141Sgblack@eecs.umich.edu
1495141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_IORR_MASK0, 0);
1505141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_IORR_MASK1, 0);
1515141Sgblack@eecs.umich.edu
1525141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TOP_MEM, 0x4000000);
1535141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TOP_MEM2, 0x0);
1545141Sgblack@eecs.umich.edu
1555141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0);
1565141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0);
1575141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0);
1585141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0);
1595141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0);
1605135Sgblack@eecs.umich.edu
1615135Sgblack@eecs.umich.edu    // Invalidate the caches (this should already be done for us)
1625135Sgblack@eecs.umich.edu
1635360Sgblack@eecs.umich.edu    LocalApicBase lApicBase = 0;
1645360Sgblack@eecs.umich.edu    lApicBase.base = 0xFEE00000 >> 12;
1655360Sgblack@eecs.umich.edu    lApicBase.enable = 1;
1665360Sgblack@eecs.umich.edu    lApicBase.bsp = (cpuId == 0);
1675360Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_APIC_BASE, lApicBase);
1685360Sgblack@eecs.umich.edu
1695647Sgblack@eecs.umich.edu    Interrupts * interrupts = dynamic_cast<Interrupts *>(
1705647Sgblack@eecs.umich.edu            tc->getCpuPtr()->getInterruptController());
1715647Sgblack@eecs.umich.edu    assert(interrupts);
1725360Sgblack@eecs.umich.edu
1735647Sgblack@eecs.umich.edu    interrupts->setRegNoEffect(APIC_ID, cpuId << 24);
1745647Sgblack@eecs.umich.edu
1755647Sgblack@eecs.umich.edu    interrupts->setRegNoEffect(APIC_VERSION, (5 << 16) | 0x14);
1769157Sandreas.hansson@arm.com
1779157Sandreas.hansson@arm.com    // @todo: Control the relative frequency, in this case 16:1, of
1789157Sandreas.hansson@arm.com    // the clocks in the Python code
1799180Sandreas.hansson@arm.com    interrupts->setClock(tc->getCpuPtr()->clockPeriod() * 16);
1805360Sgblack@eecs.umich.edu
1815141Sgblack@eecs.umich.edu    // TODO Set the SMRAM base address (SMBASE) to 0x00030000
1825141Sgblack@eecs.umich.edu
1835141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_VM_CR, 0);
1845141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_IGNNE, 0);
1855141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_SMM_CTL, 0);
1865141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0);
1875135Sgblack@eecs.umich.edu}
1885135Sgblack@eecs.umich.edu
1895135Sgblack@eecs.umich.eduvoid startupCPU(ThreadContext *tc, int cpuId)
1905135Sgblack@eecs.umich.edu{
1918768Sgblack@eecs.umich.edu    if (cpuId == 0 || !FullSystem) {
1929180Sandreas.hansson@arm.com        tc->activate(Cycles(0));
1935135Sgblack@eecs.umich.edu    } else {
1945135Sgblack@eecs.umich.edu        // This is an application processor (AP). It should be initialized to
1955135Sgblack@eecs.umich.edu        // look like only the BIOS POST has run on it and put then put it into
1965135Sgblack@eecs.umich.edu        // a halted state.
1979180Sandreas.hansson@arm.com        tc->suspend(Cycles(0));
1985135Sgblack@eecs.umich.edu    }
1995135Sgblack@eecs.umich.edu}
2005135Sgblack@eecs.umich.edu
2016329Sgblack@eecs.umich.eduvoid
2026329Sgblack@eecs.umich.educopyMiscRegs(ThreadContext *src, ThreadContext *dest)
2036329Sgblack@eecs.umich.edu{
2048466Snilay@cs.wisc.edu    // This function assumes no side effects other than TLB invalidation
2058466Snilay@cs.wisc.edu    // need to be considered while copying state. That will likely not be
2068466Snilay@cs.wisc.edu    // true in the future.
2076329Sgblack@eecs.umich.edu    for (int i = 0; i < NUM_MISCREGS; ++i) {
2086329Sgblack@eecs.umich.edu        if ( ( i != MISCREG_CR1 &&
2096329Sgblack@eecs.umich.edu             !(i > MISCREG_CR4 && i < MISCREG_CR8) &&
2106329Sgblack@eecs.umich.edu             !(i > MISCREG_CR8 && i <= MISCREG_CR15) ) == false) {
2116329Sgblack@eecs.umich.edu             continue;
2126329Sgblack@eecs.umich.edu        }
2136329Sgblack@eecs.umich.edu        dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
2146329Sgblack@eecs.umich.edu    }
2158466Snilay@cs.wisc.edu
2168466Snilay@cs.wisc.edu    dest->getITBPtr()->invalidateAll();
2178466Snilay@cs.wisc.edu    dest->getDTBPtr()->invalidateAll();
2186329Sgblack@eecs.umich.edu}
2196329Sgblack@eecs.umich.edu
2206329Sgblack@eecs.umich.eduvoid
2216329Sgblack@eecs.umich.educopyRegs(ThreadContext *src, ThreadContext *dest)
2226329Sgblack@eecs.umich.edu{
2236329Sgblack@eecs.umich.edu    //copy int regs
2248466Snilay@cs.wisc.edu    for (int i = 0; i < NumIntRegs; ++i)
2258466Snilay@cs.wisc.edu         dest->setIntReg(i, src->readIntReg(i));
2266329Sgblack@eecs.umich.edu    //copy float regs
2278466Snilay@cs.wisc.edu    for (int i = 0; i < NumFloatRegs; ++i)
2288466Snilay@cs.wisc.edu         dest->setFloatRegBits(i, src->readFloatRegBits(i));
2296329Sgblack@eecs.umich.edu    copyMiscRegs(src, dest);
2307720Sgblack@eecs.umich.edu    dest->pcState(src->pcState());
2316329Sgblack@eecs.umich.edu}
2326329Sgblack@eecs.umich.edu
2337693SAli.Saidi@ARM.comvoid
2347693SAli.Saidi@ARM.comskipFunction(ThreadContext *tc)
2357693SAli.Saidi@ARM.com{
2367693SAli.Saidi@ARM.com    panic("Not implemented for x86\n");
2377693SAli.Saidi@ARM.com}
2387693SAli.Saidi@ARM.com
2397693SAli.Saidi@ARM.com
2407811Ssteve.reinhardt@amd.com} // namespace X86_ISA
241