utility.cc revision 7629
15086Sgblack@eecs.umich.edu/*
25086Sgblack@eecs.umich.edu * Copyright (c) 2007 The Hewlett-Packard Development Company
35086Sgblack@eecs.umich.edu * All rights reserved.
45086Sgblack@eecs.umich.edu *
57087Snate@binkert.org * The license below extends only to copyright in the software and shall
67087Snate@binkert.org * not be construed as granting a license to any other intellectual
77087Snate@binkert.org * property including but not limited to intellectual property relating
87087Snate@binkert.org * to a hardware implementation of the functionality of the software
97087Snate@binkert.org * licensed hereunder.  You may use the software subject to the license
107087Snate@binkert.org * terms below provided that you ensure that this notice is replicated
117087Snate@binkert.org * unmodified and in its entirety in all distributions of the software,
127087Snate@binkert.org * modified or unmodified, in source code or in binary form.
135086Sgblack@eecs.umich.edu *
147087Snate@binkert.org * Redistribution and use in source and binary forms, with or without
157087Snate@binkert.org * modification, are permitted provided that the following conditions are
167087Snate@binkert.org * met: redistributions of source code must retain the above copyright
177087Snate@binkert.org * notice, this list of conditions and the following disclaimer;
187087Snate@binkert.org * redistributions in binary form must reproduce the above copyright
197087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the
207087Snate@binkert.org * documentation and/or other materials provided with the distribution;
217087Snate@binkert.org * neither the name of the copyright holders nor the names of its
225086Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from
237087Snate@binkert.org * this software without specific prior written permission.
245086Sgblack@eecs.umich.edu *
255086Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
265086Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
275086Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
285086Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
295086Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
305086Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
315086Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
325086Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
335086Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
345086Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
355086Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
365086Sgblack@eecs.umich.edu *
375086Sgblack@eecs.umich.edu * Authors: Gabe Black
385086Sgblack@eecs.umich.edu */
395086Sgblack@eecs.umich.edu
405647Sgblack@eecs.umich.edu#include "config/full_system.hh"
415647Sgblack@eecs.umich.edu
425647Sgblack@eecs.umich.edu#if FULL_SYSTEM
435647Sgblack@eecs.umich.edu#include "arch/x86/interrupts.hh"
445647Sgblack@eecs.umich.edu#endif
457629Sgblack@eecs.umich.edu#include "arch/x86/regs/int.hh"
467629Sgblack@eecs.umich.edu#include "arch/x86/regs/misc.hh"
477629Sgblack@eecs.umich.edu#include "arch/x86/regs/segment.hh"
485086Sgblack@eecs.umich.edu#include "arch/x86/utility.hh"
495135Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh"
505647Sgblack@eecs.umich.edu#include "cpu/base.hh"
515234Sgblack@eecs.umich.edu#include "sim/system.hh"
525086Sgblack@eecs.umich.edu
535086Sgblack@eecs.umich.edunamespace X86ISA {
545086Sgblack@eecs.umich.edu
555086Sgblack@eecs.umich.eduuint64_t getArgument(ThreadContext *tc, int number, bool fp) {
565086Sgblack@eecs.umich.edu#if FULL_SYSTEM
575086Sgblack@eecs.umich.edu    panic("getArgument() not implemented for x86!\n");
585086Sgblack@eecs.umich.edu#else
595086Sgblack@eecs.umich.edu    panic("getArgument() only implemented for FULL_SYSTEM\n");
605086Sgblack@eecs.umich.edu    M5_DUMMY_RETURN
615086Sgblack@eecs.umich.edu#endif
625086Sgblack@eecs.umich.edu}
635135Sgblack@eecs.umich.edu
645135Sgblack@eecs.umich.edu# if FULL_SYSTEM
655135Sgblack@eecs.umich.eduvoid initCPU(ThreadContext *tc, int cpuId)
665135Sgblack@eecs.umich.edu{
676048Sgblack@eecs.umich.edu    // This function is essentially performing a reset. The actual INIT
686048Sgblack@eecs.umich.edu    // interrupt does a subset of this, so we'll piggyback on some of its
696048Sgblack@eecs.umich.edu    // functionality.
706048Sgblack@eecs.umich.edu    InitInterrupt init(0);
716048Sgblack@eecs.umich.edu    init.invoke(tc);
726048Sgblack@eecs.umich.edu
736048Sgblack@eecs.umich.edu    tc->setMicroPC(0);
746048Sgblack@eecs.umich.edu    tc->setNextMicroPC(1);
755135Sgblack@eecs.umich.edu
765135Sgblack@eecs.umich.edu    // These next two loops zero internal microcode and implicit registers.
775135Sgblack@eecs.umich.edu    // They aren't specified by the ISA but are used internally by M5's
785135Sgblack@eecs.umich.edu    // implementation.
795135Sgblack@eecs.umich.edu    for (int index = 0; index < NumMicroIntRegs; index++) {
805135Sgblack@eecs.umich.edu        tc->setIntReg(INTREG_MICRO(index), 0);
815135Sgblack@eecs.umich.edu    }
825135Sgblack@eecs.umich.edu
835135Sgblack@eecs.umich.edu    for (int index = 0; index < NumImplicitIntRegs; index++) {
845135Sgblack@eecs.umich.edu        tc->setIntReg(INTREG_IMPLICIT(index), 0);
855135Sgblack@eecs.umich.edu    }
865135Sgblack@eecs.umich.edu
875135Sgblack@eecs.umich.edu    // Set integer register EAX to 0 to indicate that the optional BIST
885135Sgblack@eecs.umich.edu    // passed. No BIST actually runs, but software may still check this
895135Sgblack@eecs.umich.edu    // register for errors.
905135Sgblack@eecs.umich.edu    tc->setIntReg(INTREG_RAX, 0);
915135Sgblack@eecs.umich.edu
925264Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_CR0, 0x0000000060000010ULL);
935135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_CR8, 0);
945135Sgblack@eecs.umich.edu
955135Sgblack@eecs.umich.edu    // TODO initialize x87, 64 bit, and 128 bit media state
965135Sgblack@eecs.umich.edu
975141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRRCAP, 0x0508);
985141Sgblack@eecs.umich.edu    for (int i = 0; i < 8; i++) {
995141Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0);
1005141Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0);
1015141Sgblack@eecs.umich.edu    }
1025141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0);
1035141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_16K_80000, 0);
1045141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_16K_A0000, 0);
1055141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_4K_C0000, 0);
1065182Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_4K_C8000, 0);
1075141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_4K_D0000, 0);
1085141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0);
1095141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_4K_E0000, 0);
1105141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0);
1115141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_4K_F0000, 0);
1125141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0);
1135135Sgblack@eecs.umich.edu
1145141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_DEF_TYPE, 0);
1155141Sgblack@eecs.umich.edu
1165141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MCG_CAP, 0x104);
1175141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MCG_STATUS, 0);
1185141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MCG_CTL, 0);
1195141Sgblack@eecs.umich.edu
1205141Sgblack@eecs.umich.edu    for (int i = 0; i < 5; i++) {
1215141Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_MC_CTL(i), 0);
1225141Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_MC_STATUS(i), 0);
1235141Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_MC_ADDR(i), 0);
1245141Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_MC_MISC(i), 0);
1255141Sgblack@eecs.umich.edu    }
1265135Sgblack@eecs.umich.edu
1275141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TSC, 0);
1285141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TSC_AUX, 0);
1295135Sgblack@eecs.umich.edu
1305141Sgblack@eecs.umich.edu    for (int i = 0; i < 4; i++) {
1315141Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0);
1325141Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0);
1335141Sgblack@eecs.umich.edu    }
1345135Sgblack@eecs.umich.edu
1355141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_STAR, 0);
1365141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_LSTAR, 0);
1375141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_CSTAR, 0);
1385141Sgblack@eecs.umich.edu
1395141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_SF_MASK, 0);
1405141Sgblack@eecs.umich.edu
1415141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0);
1425141Sgblack@eecs.umich.edu
1435141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_SYSENTER_CS, 0);
1445141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_SYSENTER_ESP, 0);
1455141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_SYSENTER_EIP, 0);
1465141Sgblack@eecs.umich.edu
1475264Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_PAT, 0x0007040600070406ULL);
1485141Sgblack@eecs.umich.edu
1495141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_SYSCFG, 0x20601);
1505141Sgblack@eecs.umich.edu
1515141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_IORR_BASE0, 0);
1525141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_IORR_BASE1, 0);
1535141Sgblack@eecs.umich.edu
1545141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_IORR_MASK0, 0);
1555141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_IORR_MASK1, 0);
1565141Sgblack@eecs.umich.edu
1575141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TOP_MEM, 0x4000000);
1585141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TOP_MEM2, 0x0);
1595141Sgblack@eecs.umich.edu
1605141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0);
1615141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0);
1625141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0);
1635141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0);
1645141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0);
1655135Sgblack@eecs.umich.edu
1665135Sgblack@eecs.umich.edu    // Invalidate the caches (this should already be done for us)
1675135Sgblack@eecs.umich.edu
1685360Sgblack@eecs.umich.edu    LocalApicBase lApicBase = 0;
1695360Sgblack@eecs.umich.edu    lApicBase.base = 0xFEE00000 >> 12;
1705360Sgblack@eecs.umich.edu    lApicBase.enable = 1;
1715360Sgblack@eecs.umich.edu    lApicBase.bsp = (cpuId == 0);
1725360Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_APIC_BASE, lApicBase);
1735360Sgblack@eecs.umich.edu
1745647Sgblack@eecs.umich.edu    Interrupts * interrupts = dynamic_cast<Interrupts *>(
1755647Sgblack@eecs.umich.edu            tc->getCpuPtr()->getInterruptController());
1765647Sgblack@eecs.umich.edu    assert(interrupts);
1775360Sgblack@eecs.umich.edu
1785647Sgblack@eecs.umich.edu    interrupts->setRegNoEffect(APIC_ID, cpuId << 24);
1795647Sgblack@eecs.umich.edu
1805647Sgblack@eecs.umich.edu    interrupts->setRegNoEffect(APIC_VERSION, (5 << 16) | 0x14);
1815648Sgblack@eecs.umich.edu
1825648Sgblack@eecs.umich.edu    interrupts->setClock(tc->getCpuPtr()->ticks(16));
1835360Sgblack@eecs.umich.edu
1845141Sgblack@eecs.umich.edu    // TODO Set the SMRAM base address (SMBASE) to 0x00030000
1855141Sgblack@eecs.umich.edu
1865141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_VM_CR, 0);
1875141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_IGNNE, 0);
1885141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_SMM_CTL, 0);
1895141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0);
1905135Sgblack@eecs.umich.edu}
1915135Sgblack@eecs.umich.edu
1925135Sgblack@eecs.umich.edu#endif
1935135Sgblack@eecs.umich.edu
1945135Sgblack@eecs.umich.eduvoid startupCPU(ThreadContext *tc, int cpuId)
1955135Sgblack@eecs.umich.edu{
1966042Sgblack@eecs.umich.edu#if FULL_SYSTEM
1975135Sgblack@eecs.umich.edu    if (cpuId == 0) {
1985135Sgblack@eecs.umich.edu        tc->activate(0);
1995135Sgblack@eecs.umich.edu    } else {
2005135Sgblack@eecs.umich.edu        // This is an application processor (AP). It should be initialized to
2015135Sgblack@eecs.umich.edu        // look like only the BIOS POST has run on it and put then put it into
2025135Sgblack@eecs.umich.edu        // a halted state.
2036042Sgblack@eecs.umich.edu        tc->suspend(0);
2045135Sgblack@eecs.umich.edu    }
2056042Sgblack@eecs.umich.edu#else
2066042Sgblack@eecs.umich.edu    tc->activate(0);
2076042Sgblack@eecs.umich.edu#endif
2085135Sgblack@eecs.umich.edu}
2095135Sgblack@eecs.umich.edu
2106329Sgblack@eecs.umich.eduvoid
2116329Sgblack@eecs.umich.educopyMiscRegs(ThreadContext *src, ThreadContext *dest)
2126329Sgblack@eecs.umich.edu{
2136329Sgblack@eecs.umich.edu    warn("copyMiscRegs is naively implemented for x86\n");
2146329Sgblack@eecs.umich.edu    for (int i = 0; i < NUM_MISCREGS; ++i) {
2156329Sgblack@eecs.umich.edu        if ( ( i != MISCREG_CR1 &&
2166329Sgblack@eecs.umich.edu             !(i > MISCREG_CR4 && i < MISCREG_CR8) &&
2176329Sgblack@eecs.umich.edu             !(i > MISCREG_CR8 && i <= MISCREG_CR15) ) == false) {
2186329Sgblack@eecs.umich.edu             continue;
2196329Sgblack@eecs.umich.edu        }
2206329Sgblack@eecs.umich.edu        dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
2216329Sgblack@eecs.umich.edu    }
2226329Sgblack@eecs.umich.edu}
2236329Sgblack@eecs.umich.edu
2246329Sgblack@eecs.umich.eduvoid
2256329Sgblack@eecs.umich.educopyRegs(ThreadContext *src, ThreadContext *dest)
2266329Sgblack@eecs.umich.edu{
2276329Sgblack@eecs.umich.edu    panic("copyRegs not implemented for x86!\n");
2286329Sgblack@eecs.umich.edu    //copy int regs
2296329Sgblack@eecs.umich.edu    //copy float regs
2306329Sgblack@eecs.umich.edu    copyMiscRegs(src, dest);
2316329Sgblack@eecs.umich.edu
2326329Sgblack@eecs.umich.edu    dest->setPC(src->readPC());
2336329Sgblack@eecs.umich.edu    dest->setNextPC(src->readNextPC());
2346329Sgblack@eecs.umich.edu}
2356329Sgblack@eecs.umich.edu
2365086Sgblack@eecs.umich.edu} //namespace X86_ISA
237