utility.cc revision 5135
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IN NO EVENT SHALL THE COPYRIGHT 475086Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 485086Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 495086Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 505086Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 515086Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 525086Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 535086Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 545086Sgblack@eecs.umich.edu * 555086Sgblack@eecs.umich.edu * Authors: Gabe Black 565086Sgblack@eecs.umich.edu */ 575086Sgblack@eecs.umich.edu 585135Sgblack@eecs.umich.edu#include "arch/x86/intregs.hh" 595135Sgblack@eecs.umich.edu#include "arch/x86/miscregs.hh" 605135Sgblack@eecs.umich.edu#include "arch/x86/segmentregs.hh" 615086Sgblack@eecs.umich.edu#include "arch/x86/utility.hh" 625135Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh" 635086Sgblack@eecs.umich.edu 645086Sgblack@eecs.umich.edunamespace X86ISA { 655086Sgblack@eecs.umich.edu 665086Sgblack@eecs.umich.eduuint64_t getArgument(ThreadContext *tc, int number, bool fp) { 675086Sgblack@eecs.umich.edu#if FULL_SYSTEM 685086Sgblack@eecs.umich.edu panic("getArgument() not implemented for x86!\n"); 695086Sgblack@eecs.umich.edu#else 705086Sgblack@eecs.umich.edu panic("getArgument() only implemented for FULL_SYSTEM\n"); 715086Sgblack@eecs.umich.edu M5_DUMMY_RETURN 725086Sgblack@eecs.umich.edu#endif 735086Sgblack@eecs.umich.edu} 745135Sgblack@eecs.umich.edu 755135Sgblack@eecs.umich.edu# if FULL_SYSTEM 765135Sgblack@eecs.umich.eduvoid initCPU(ThreadContext *tc, int cpuId) 775135Sgblack@eecs.umich.edu{ 785135Sgblack@eecs.umich.edu // TODO Figure out what the attribute registers should be set to. How this 795135Sgblack@eecs.umich.edu // information is stored isn't specified, but it's values are in table 805135Sgblack@eecs.umich.edu // 14.2. 815135Sgblack@eecs.umich.edu 825135Sgblack@eecs.umich.edu // The otherwise unmodified integer registers should be set to 0. 835135Sgblack@eecs.umich.edu for (int index = 0; index < NUM_INTREGS; index++) { 845135Sgblack@eecs.umich.edu tc->setIntReg(index, 0); 855135Sgblack@eecs.umich.edu } 865135Sgblack@eecs.umich.edu 875135Sgblack@eecs.umich.edu // These next two loops zero internal microcode and implicit registers. 885135Sgblack@eecs.umich.edu // They aren't specified by the ISA but are used internally by M5's 895135Sgblack@eecs.umich.edu // implementation. 905135Sgblack@eecs.umich.edu for (int index = 0; index < NumMicroIntRegs; index++) { 915135Sgblack@eecs.umich.edu tc->setIntReg(INTREG_MICRO(index), 0); 925135Sgblack@eecs.umich.edu } 935135Sgblack@eecs.umich.edu 945135Sgblack@eecs.umich.edu for (int index = 0; index < NumImplicitIntRegs; index++) { 955135Sgblack@eecs.umich.edu tc->setIntReg(INTREG_IMPLICIT(index), 0); 965135Sgblack@eecs.umich.edu } 975135Sgblack@eecs.umich.edu 985135Sgblack@eecs.umich.edu // Set integer register EAX to 0 to indicate that the optional BIST 995135Sgblack@eecs.umich.edu // passed. No BIST actually runs, but software may still check this 1005135Sgblack@eecs.umich.edu // register for errors. 1015135Sgblack@eecs.umich.edu tc->setIntReg(INTREG_RAX, 0); 1025135Sgblack@eecs.umich.edu 1035135Sgblack@eecs.umich.edu //The following values are dictated by the architecture for after a RESET# 1045135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR0, 0x0000000060000010); 1055135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR2, 0); 1065135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR3, 0); 1075135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR4, 0); 1085135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR8, 0); 1095135Sgblack@eecs.umich.edu 1105135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002); 1115135Sgblack@eecs.umich.edu 1125135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_EFER, 0); 1135135Sgblack@eecs.umich.edu 1145135Sgblack@eecs.umich.edu for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) { 1155135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SEG_SEL(seg), 0); 1165135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SEG_BASE(seg), 0); 1175135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff); 1185135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SEG_ATTR(seg), 0); 1195135Sgblack@eecs.umich.edu } 1205135Sgblack@eecs.umich.edu 1215135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CS, 0xf000); 1225135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CS_BASE, 0x00000000ffff0000); 1235135Sgblack@eecs.umich.edu // This has the base value pre-added. 1245135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff); 1255135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CS_ATTR, 0); 1265135Sgblack@eecs.umich.edu 1275135Sgblack@eecs.umich.edu tc->setPC(0x000000000000fff0 + 1285135Sgblack@eecs.umich.edu tc->readMiscReg(MISCREG_CS_BASE)); 1295135Sgblack@eecs.umich.edu tc->setNextPC(tc->readPC() + sizeof(MachInst)); 1305135Sgblack@eecs.umich.edu 1315135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_GDTR_BASE, 0); 1325135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_GDTR_LIMIT, 0xffff); 1335135Sgblack@eecs.umich.edu 1345135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IDTR_BASE, 0); 1355135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff); 1365135Sgblack@eecs.umich.edu 1375135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LDTR, 0); 1385135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LDTR_BASE, 0); 1395135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LDTR_LIMIT, 0xffff); 1405135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LDTR_ATTR, 0); 1415135Sgblack@eecs.umich.edu 1425135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TR, 0); 1435135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TR_BASE, 0); 1445135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff); 1455135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TR_ATTR, 0); 1465135Sgblack@eecs.umich.edu 1475135Sgblack@eecs.umich.edu // This value should be the family/model/stepping of the processor. 1485135Sgblack@eecs.umich.edu // (page 418). It should be consistent with the value from CPUID, but the 1495135Sgblack@eecs.umich.edu // actual value probably doesn't matter much. 1505135Sgblack@eecs.umich.edu tc->setIntReg(INTREG_RDX, 0); 1515135Sgblack@eecs.umich.edu 1525135Sgblack@eecs.umich.edu // TODO initialize x87, 64 bit, and 128 bit media state 1535135Sgblack@eecs.umich.edu 1545135Sgblack@eecs.umich.edu // TODO Set up MTRRs (page 512) 1555135Sgblack@eecs.umich.edu 1565135Sgblack@eecs.umich.edu // TODO Set up machine check registers (page 515) 1575135Sgblack@eecs.umich.edu 1585135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DR0, 0); 1595135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DR1, 0); 1605135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DR2, 0); 1615135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DR3, 0); 1625135Sgblack@eecs.umich.edu 1635135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0); 1645135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DR7, 0x0000000000000400); 1655135Sgblack@eecs.umich.edu 1665135Sgblack@eecs.umich.edu // TODO Set time stamp counter to 0 1675135Sgblack@eecs.umich.edu 1685135Sgblack@eecs.umich.edu // TODO Set up performance monitoring registers (page 517) 1695135Sgblack@eecs.umich.edu 1705135Sgblack@eecs.umich.edu // TODO Set up the rest of the MSRs (page 507) 1715135Sgblack@eecs.umich.edu 1725135Sgblack@eecs.umich.edu // Invalidate the caches (this should already be done for us) 1735135Sgblack@eecs.umich.edu 1745135Sgblack@eecs.umich.edu // TODO Turn on the APIC. This should be handled elsewhere but it isn't 1755135Sgblack@eecs.umich.edu // currently being handled at all. 1765135Sgblack@eecs.umich.edu 1775135Sgblack@eecs.umich.edu // Set the SMRAM base address (SMBASE) to 0x00030000 1785135Sgblack@eecs.umich.edu} 1795135Sgblack@eecs.umich.edu 1805135Sgblack@eecs.umich.edu#endif 1815135Sgblack@eecs.umich.edu 1825135Sgblack@eecs.umich.eduvoid startupCPU(ThreadContext *tc, int cpuId) 1835135Sgblack@eecs.umich.edu{ 1845135Sgblack@eecs.umich.edu if (cpuId == 0) { 1855135Sgblack@eecs.umich.edu // This is the boot strap processor (BSP). Initialize it to look like 1865135Sgblack@eecs.umich.edu // the boot loader has just turned control over to the 64 bit OS. 1875135Sgblack@eecs.umich.edu 1885135Sgblack@eecs.umich.edu // Enable paging, turn on long mode, etc. 1895135Sgblack@eecs.umich.edu 1905135Sgblack@eecs.umich.edu tc->activate(0); 1915135Sgblack@eecs.umich.edu } else { 1925135Sgblack@eecs.umich.edu // This is an application processor (AP). It should be initialized to 1935135Sgblack@eecs.umich.edu // look like only the BIOS POST has run on it and put then put it into 1945135Sgblack@eecs.umich.edu // a halted state. 1955135Sgblack@eecs.umich.edu } 1965135Sgblack@eecs.umich.edu} 1975135Sgblack@eecs.umich.edu 1985086Sgblack@eecs.umich.edu} //namespace X86_ISA 199