types.hh revision 4680:09867d787df8
1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * 9 * The software must be used only for Non-Commercial Use which means any 10 * use which is NOT directed to receiving any direct monetary 11 * compensation for, or commercial advantage from such use. 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Derivatives of the software may be shared with 37 * others provided: (i) the others agree to abide by the list of 38 * conditions herein which includes the Non-Commercial Use restrictions; 39 * and (ii) such Derivatives of the software include the above copyright 40 * notice to acknowledge the contribution from this software where 41 * applicable, this list of conditions and the disclaimer below. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * 55 * Authors: Gabe Black 56 */ 57 58#ifndef __ARCH_X86_TYPES_HH__ 59#define __ARCH_X86_TYPES_HH__ 60 61#include <inttypes.h> 62#include <iostream> 63 64#include "base/bitunion.hh" 65#include "base/cprintf.hh" 66 67namespace X86ISA 68{ 69 //This really determines how many bytes are passed to the predecoder. 70 typedef uint64_t MachInst; 71 72 enum Prefixes { 73 NoOverride, 74 CSOverride, 75 DSOverride, 76 ESOverride, 77 FSOverride, 78 GSOverride, 79 SSOverride, 80 RexPrefix, 81 OperandSizeOverride, 82 AddressSizeOverride, 83 Lock, 84 Rep, 85 Repne 86 }; 87 88 BitUnion8(LegacyPrefixVector) 89 Bitfield<7> repne; 90 Bitfield<6> rep; 91 Bitfield<5> lock; 92 Bitfield<4> addr; 93 Bitfield<3> op; 94 //There can be only one segment override, so they share the 95 //first 3 bits in the legacyPrefixes bitfield. 96 Bitfield<2,0> seg; 97 EndBitUnion(LegacyPrefixVector) 98 99 BitUnion8(ModRM) 100 Bitfield<7,6> mod; 101 Bitfield<5,3> reg; 102 Bitfield<2,0> rm; 103 EndBitUnion(ModRM) 104 105 BitUnion8(Sib) 106 Bitfield<7,6> scale; 107 Bitfield<5,3> index; 108 Bitfield<2,0> base; 109 EndBitUnion(Sib) 110 111 BitUnion8(Rex) 112 Bitfield<3> w; 113 Bitfield<2> r; 114 Bitfield<1> x; 115 Bitfield<0> b; 116 EndBitUnion(Rex) 117 118 BitUnion8(Opcode) 119 Bitfield<7,3> top5; 120 Bitfield<2,0> bottom3; 121 EndBitUnion(Opcode) 122 123 BitUnion8(OperatingMode) 124 Bitfield<3> mode; 125 Bitfield<2,0> submode; 126 EndBitUnion(OperatingMode) 127 128 enum X86Mode { 129 LongMode, 130 LegacyMode 131 }; 132 133 enum X86SubMode { 134 SixtyFourBitMode, 135 CompatabilityMode, 136 ProtectedMode, 137 Virtual8086Mode, 138 RealMode 139 }; 140 141 //The intermediate structure the x86 predecoder returns. 142 struct ExtMachInst 143 { 144 //Prefixes 145 LegacyPrefixVector legacy; 146 Rex rex; 147 //This holds all of the bytes of the opcode 148 struct 149 { 150 //The number of bytes in this opcode. Right now, we ignore that 151 //this can be 3 in some cases 152 uint8_t num; 153 //The first byte detected in a 2+ byte opcode. Should be 0xF0. 154 uint8_t prefixA; 155 //The second byte detected in a 3+ byte opcode. Could be 0xF0 for 156 //3dnow instructions, or 0x38-0x3F for some SSE instructions. 157 uint8_t prefixB; 158 //The main opcode byte. The highest addressed byte in the opcode. 159 Opcode op; 160 } opcode; 161 //Modifier bytes 162 ModRM modRM; 163 Sib sib; 164 //Immediate fields 165 uint64_t immediate; 166 uint64_t displacement; 167 168 //The effective operand size. 169 uint8_t opSize; 170 //The effective address size. 171 uint8_t addrSize; 172 //The effective stack size. 173 uint8_t stackSize; 174 175 //Mode information 176 OperatingMode mode; 177 }; 178 179 inline static std::ostream & 180 operator << (std::ostream & os, const ExtMachInst & emi) 181 { 182 ccprintf(os, "\n{\n\tleg = %#x,\n\trex = %#x,\n\t" 183 "op = {\n\t\tnum = %d,\n\t\top = %#x,\n\t\t" 184 "prefixA = %#x,\n\t\tprefixB = %#x\n\t},\n\t" 185 "modRM = %#x,\n\tsib = %#x,\n\t" 186 "immediate = %#x,\n\tdisplacement = %#x\n}\n", 187 emi.legacy, (uint8_t)emi.rex, 188 emi.opcode.num, emi.opcode.op, 189 emi.opcode.prefixA, emi.opcode.prefixB, 190 (uint8_t)emi.modRM, (uint8_t)emi.sib, 191 emi.immediate, emi.displacement); 192 return os; 193 } 194 195 inline static bool 196 operator == (const ExtMachInst &emi1, const ExtMachInst &emi2) 197 { 198 if(emi1.legacy != emi2.legacy) 199 return false; 200 if(emi1.rex != emi2.rex) 201 return false; 202 if(emi1.opcode.num != emi2.opcode.num) 203 return false; 204 if(emi1.opcode.op != emi2.opcode.op) 205 return false; 206 if(emi1.opcode.prefixA != emi2.opcode.prefixA) 207 return false; 208 if(emi1.opcode.prefixB != emi2.opcode.prefixB) 209 return false; 210 if(emi1.modRM != emi2.modRM) 211 return false; 212 if(emi1.sib != emi2.sib) 213 return false; 214 if(emi1.immediate != emi2.immediate) 215 return false; 216 if(emi1.displacement != emi2.displacement) 217 return false; 218 if(emi1.mode != emi2.mode) 219 return false; 220 if(emi1.opSize != emi2.opSize) 221 return false; 222 if(emi1.addrSize != emi2.addrSize) 223 return false; 224 if(emi1.stackSize != emi2.stackSize) 225 return false; 226 return true; 227 } 228 229 typedef uint64_t IntReg; 230 //XXX Should this be a 128 bit structure for XMM memory ops? 231 typedef uint64_t LargestRead; 232 typedef uint64_t MiscReg; 233 234 //These floating point types are correct for mmx, but not 235 //technically for x87 (80 bits) or at all for xmm (128 bits) 236 typedef double FloatReg; 237 typedef uint64_t FloatRegBits; 238 typedef union 239 { 240 IntReg intReg; 241 FloatReg fpReg; 242 MiscReg ctrlReg; 243 } AnyReg; 244 245 //XXX This is very hypothetical. X87 instructions would need to 246 //change their "context" constantly. It's also not clear how 247 //this would be handled as far as out of order execution. 248 //Maybe x87 instructions are in order? 249 enum RegContextParam 250 { 251 CONTEXT_X87_TOP 252 }; 253 254 typedef int RegContextVal; 255 256 typedef uint8_t RegIndex; 257}; 258 259#endif // __ARCH_X86_TYPES_HH__ 260