xref: /gem5/src/arch/x86/types.cc

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 * notice to acknowledge the contribution from this software where
 * applicable, this list of conditions and the disclaimer below.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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 * Authors: Gabe Black
 */

#ifndef __ARCH_X86_TYPES_HH__
#define __ARCH_X86_TYPES_HH__

#include <inttypes.h>
#include <iostream>

namespace X86ISA
{
    //This really determines how many bytes are passed to the predecoder.
    typedef uint64_t MachInst;

    enum Prefixes {
        NoOverride = 0,
        CSOverride = 1,
        DSOverride = 2,
        ESOverride = 3,
        FSOverride = 4,
        GSOverride = 5,
        SSOverride = 6,
        //The Rex prefix obviously doesn't fit in with the above, but putting
        //it here lets us save double the space the enums take up.
        Rex = 7,
        //There can be only one segment override, so they share the
        //first 3 bits in the legacyPrefixes bitfield.
        SegmentOverride = 0x7,
        OperandSizeOverride = 8,
        AddressSizeOverride = 16,
        Lock = 32,
        Rep = 64,
        Repne = 128
    };

    //The intermediate structure the x86 predecoder returns.
    struct ExtMachInst
    {
      public: //XXX These should be hidden in the future

        uint8_t legacyPrefixes;
        uint8_t rexPrefix;
        bool twoByteOpcode;
        uint8_t opcode;
        uint64_t immediate;
        uint64_t displacement;

      public:

        //These are to pacify the decoder for now. This will go away once
        //it can handle non integer inputs, and in the mean time allow me to
        //excercise the predecoder a little.
        operator unsigned int()
        {
            return 0;
        }

        ExtMachInst(unsigned int)
        {;}

        ExtMachInst()
        {;}
    };

    inline static std::ostream &
        operator << (std::ostream & os, const ExtMachInst & emi)
    {
        os << "{X86 ExtMachInst}";
        return os;
    }

    inline static bool
        operator == (const ExtMachInst &emi1, const ExtMachInst &emi2)
    {
        //Since this is empty, it's always equal
        return true;
    }

    typedef uint64_t IntReg;
    //XXX Should this be a 128 bit structure for XMM memory ops?
    typedef uint64_t LargestRead;
    typedef uint64_t MiscReg;

    //These floating point types are correct for mmx, but not
    //technically for x87 (80 bits) or at all for xmm (128 bits)
    typedef double FloatReg;
    typedef uint64_t FloatRegBits;
    typedef union
    {
        IntReg intReg;
        FloatReg fpReg;
        MiscReg ctrlReg;
    } AnyReg;

    //XXX This is very hypothetical. X87 instructions would need to
    //change their "context" constantly. It's also not clear how
    //this would be handled as far as out of order execution.
    //Maybe x87 instructions are in order?
    enum RegContextParam
    {
        CONTEXT_X87_TOP
    };

    typedef int RegContextVal;

    typedef uint8_t RegIndex;
};

#endif // __ARCH_X86_TYPES_HH__