types.cc revision 4276 
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
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34 * sublicense is granted herewith.  Derivatives of the software and
35 * output created using the software may be prepared, but only for
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39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#ifndef __ARCH_X86_TYPES_HH__
59#define __ARCH_X86_TYPES_HH__
60
61#include <inttypes.h>
62#include <iostream>
63
64#include "base/bitfield.hh"
65#include "base/cprintf.hh"
66
67namespace X86ISA
68{
69    //This really determines how many bytes are passed to the predecoder.
70    typedef uint64_t MachInst;
71
72    enum Prefixes {
73        NoOverride = 0,
74        CSOverride = 1,
75        DSOverride = 2,
76        ESOverride = 3,
77        FSOverride = 4,
78        GSOverride = 5,
79        SSOverride = 6,
80        //The Rex prefix obviously doesn't fit in with the above, but putting
81        //it here lets us save double the space the enums take up.
82        RexPrefix = 7,
83        //There can be only one segment override, so they share the
84        //first 3 bits in the legacyPrefixes bitfield.
85        SegmentOverride = 0x7,
86        OperandSizeOverride = 8,
87        AddressSizeOverride = 16,
88        Lock = 32,
89        Rep = 64,
90        Repne = 128
91    };
92
93    BitUnion8(ModRM)
94        Bitfield<7,6> mod;
95        Bitfield<5,3> reg;
96        Bitfield<2,0> rm;
97    EndBitUnion(ModRM)
98
99    BitUnion8(Sib)
100        Bitfield<7,6> scale;
101        Bitfield<5,3> index;
102        Bitfield<2,0> base;
103    EndBitUnion(Sib)
104
105    BitUnion8(Rex)
106        Bitfield<3> w;
107        Bitfield<2> r;
108        Bitfield<1> x;
109        Bitfield<0> b;
110    EndBitUnion(Rex)
111
112    BitUnion8(Opcode)
113        Bitfield<7,3> top5;
114        Bitfield<2,0> bottom3;
115    EndBitUnion(Opcode)
116
117    //The intermediate structure the x86 predecoder returns.
118    struct ExtMachInst
119    {
120        //Prefixes
121        uint8_t legacy;
122        Rex rex;
123        //This holds all of the bytes of the opcode
124        struct
125        {
126            //The number of bytes in this opcode. Right now, we ignore that
127            //this can be 3 in some cases
128            uint8_t num;
129            //The first byte detected in a 2+ byte opcode. Should be 0xF0.
130            uint8_t prefixA;
131            //The second byte detected in a 3+ byte opcode. Could be 0xF0 for
132            //3dnow instructions, or 0x38-0x3F for some SSE instructions.
133            uint8_t prefixB;
134            //The main opcode byte. The highest addressed byte in the opcode.
135            Opcode op;
136        } opcode;
137        //Modifier bytes
138        ModRM modRM;
139        uint8_t sib;
140        //Immediate fields
141        uint64_t immediate;
142        uint64_t displacement;
143    };
144
145    inline static std::ostream &
146        operator << (std::ostream & os, const ExtMachInst & emi)
147    {
148        ccprintf(os, "\n{\n\tleg = %#x,\n\trex = %#x,\n\t"
149                     "op = {\n\t\tnum = %d,\n\t\top = %#x,\n\t\t"
150                           "prefixA = %#x,\n\t\tprefixB = %#x\n\t},\n\t"
151                     "modRM = %#x,\n\tsib = %#x,\n\t"
152                     "immediate = %#x,\n\tdisplacement = %#x\n}\n",
153                     emi.legacy, (uint8_t)emi.rex,
154                     emi.opcode.num, emi.opcode.op,
155                     emi.opcode.prefixA, emi.opcode.prefixB,
156                     (uint8_t)emi.modRM, (uint8_t)emi.sib,
157                     emi.immediate, emi.displacement);
158        return os;
159    }
160
161    inline static bool
162        operator == (const ExtMachInst &emi1, const ExtMachInst &emi2)
163    {
164        //Since this is empty, it's always equal
165        return true;
166    }
167
168    typedef uint64_t IntReg;
169    //XXX Should this be a 128 bit structure for XMM memory ops?
170    typedef uint64_t LargestRead;
171    typedef uint64_t MiscReg;
172
173    //These floating point types are correct for mmx, but not
174    //technically for x87 (80 bits) or at all for xmm (128 bits)
175    typedef double FloatReg;
176    typedef uint64_t FloatRegBits;
177    typedef union
178    {
179        IntReg intReg;
180        FloatReg fpReg;
181        MiscReg ctrlReg;
182    } AnyReg;
183
184    //XXX This is very hypothetical. X87 instructions would need to
185    //change their "context" constantly. It's also not clear how
186    //this would be handled as far as out of order execution.
187    //Maybe x87 instructions are in order?
188    enum RegContextParam
189    {
190        CONTEXT_X87_TOP
191    };
192
193    typedef int RegContextVal;
194
195    typedef uint8_t RegIndex;
196};
197
198#endif // __ARCH_X86_TYPES_HH__
199