tlb.hh revision 9818:ebd7d3e04b5f 
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#ifndef __ARCH_X86_TLB_HH__
41#define __ARCH_X86_TLB_HH__
42
43#include <list>
44#include <string>
45#include <vector>
46
47#include "arch/x86/regs/segment.hh"
48#include "arch/x86/pagetable.hh"
49#include "base/trie.hh"
50#include "mem/mem_object.hh"
51#include "mem/request.hh"
52#include "params/X86TLB.hh"
53#include "sim/fault_fwd.hh"
54#include "sim/sim_object.hh"
55#include "sim/tlb.hh"
56
57class ThreadContext;
58class Packet;
59
60namespace X86ISA
61{
62    class Walker;
63
64    class TLB : public BaseTLB
65    {
66      protected:
67        friend class Walker;
68
69        typedef std::list<TlbEntry *> EntryList;
70
71        uint32_t configAddress;
72
73      public:
74
75        typedef X86TLBParams Params;
76        TLB(const Params *p);
77
78        TlbEntry *lookup(Addr va, bool update_lru = true);
79
80        void setConfigAddress(uint32_t addr);
81
82      protected:
83
84        EntryList::iterator lookupIt(Addr va, bool update_lru = true);
85
86        Walker * walker;
87
88      public:
89        Walker *getWalker();
90
91        void flushAll();
92
93        void flushNonGlobal();
94
95        void demapPage(Addr va, uint64_t asn);
96
97      protected:
98        uint32_t size;
99
100        TlbEntry * tlb;
101
102        EntryList freeList;
103
104        TlbEntryTrie trie;
105        uint64_t lruSeq;
106
107        Fault translateInt(RequestPtr req, ThreadContext *tc);
108
109        Fault translate(RequestPtr req, ThreadContext *tc,
110                Translation *translation, Mode mode,
111                bool &delayedResponse, bool timing);
112
113      public:
114
115        void evictLRU();
116
117        uint64_t
118        nextSeq()
119        {
120            return ++lruSeq;
121        }
122
123        Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
124        void translateTiming(RequestPtr req, ThreadContext *tc,
125                Translation *translation, Mode mode);
126        /** Stub function for compilation support of CheckerCPU. x86 ISA does
127         *  not support Checker model at the moment
128         */
129        Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
130
131        /**
132         * Do post-translation physical address finalization.
133         *
134         * Some addresses, for example requests going to the APIC,
135         * need post-translation updates. Such physical addresses are
136         * remapped into a "magic" part of the physical address space
137         * by this method.
138         *
139         * @param req Request to updated in-place.
140         * @param tc Thread context that created the request.
141         * @param mode Request type (read/write/execute).
142         * @return A fault on failure, NoFault otherwise.
143         */
144        Fault finalizePhysical(RequestPtr req, ThreadContext *tc,
145                               Mode mode) const;
146
147        TlbEntry * insert(Addr vpn, TlbEntry &entry);
148
149        // Checkpointing
150        virtual void serialize(std::ostream &os);
151        virtual void unserialize(Checkpoint *cp, const std::string &section);
152
153        /**
154         * Get the table walker master port. This is used for
155         * migrating port connections during a CPU takeOverFrom()
156         * call. For architectures that do not have a table walker,
157         * NULL is returned, hence the use of a pointer rather than a
158         * reference. For X86 this method will always return a valid
159         * port pointer.
160         *
161         * @return A pointer to the walker master port
162         */
163        virtual BaseMasterPort *getMasterPort();
164    };
165}
166
167#endif // __ARCH_X86_TLB_HH__
168