tlb.hh revision 12455:c88f0b37f433
11817SN/A/* 21817SN/A * Copyright (c) 2007 The Hewlett-Packard Development Company 31817SN/A * All rights reserved. 41817SN/A * 51817SN/A * The license below extends only to copyright in the software and shall 61817SN/A * not be construed as granting a license to any other intellectual 71817SN/A * property including but not limited to intellectual property relating 81817SN/A * to a hardware implementation of the functionality of the software 91817SN/A * licensed hereunder. You may use the software subject to the license 101817SN/A * terms below provided that you ensure that this notice is replicated 111817SN/A * unmodified and in its entirety in all distributions of the software, 121817SN/A * modified or unmodified, in source code or in binary form. 131817SN/A * 141817SN/A * Redistribution and use in source and binary forms, with or without 151817SN/A * modification, are permitted provided that the following conditions are 161817SN/A * met: redistributions of source code must retain the above copyright 171817SN/A * notice, this list of conditions and the following disclaimer; 181817SN/A * redistributions in binary form must reproduce the above copyright 191817SN/A * notice, this list of conditions and the following disclaimer in the 201817SN/A * documentation and/or other materials provided with the distribution; 211817SN/A * neither the name of the copyright holders nor the names of its 221817SN/A * contributors may be used to endorse or promote products derived from 231817SN/A * this software without specific prior written permission. 241817SN/A * 251817SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 261817SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272665Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 283499Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 291817SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 301817SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 311817SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 321817SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 331817SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 341817SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3511793Sbrandon.potter@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3611793Sbrandon.potter@amd.com * 371817SN/A * Authors: Gabe Black 388232Snate@binkert.org */ 392542SN/A 403348Sbinkertn@umich.edu#ifndef __ARCH_X86_TLB_HH__ 411817SN/A#define __ARCH_X86_TLB_HH__ 421817SN/A 431817SN/A#include <list> 441817SN/A#include <vector> 452539SN/A 469808Sstever@gmail.com#include "arch/generic/tlb.hh" 471817SN/A#include "arch/x86/pagetable.hh" 484762Snate@binkert.org#include "base/trie.hh" 494762Snate@binkert.org#include "mem/request.hh" 504762Snate@binkert.org#include "params/X86TLB.hh" 514762Snate@binkert.org 522539SN/Aclass ThreadContext; 531817SN/A 542539SN/Anamespace X86ISA 553349Sbinkertn@umich.edu{ 562539SN/A class Walker; 578461SAli.Saidi@ARM.com 582539SN/A class TLB : public BaseTLB 594762Snate@binkert.org { 603814Ssaidi@eecs.umich.edu protected: 613814Ssaidi@eecs.umich.edu friend class Walker; 624762Snate@binkert.org 635192Ssaidi@eecs.umich.edu typedef std::list<TlbEntry *> EntryList; 643499Ssaidi@eecs.umich.edu 654870Sstever@eecs.umich.edu uint32_t configAddress; 663499Ssaidi@eecs.umich.edu 673499Ssaidi@eecs.umich.edu public: 685192Ssaidi@eecs.umich.edu 693499Ssaidi@eecs.umich.edu typedef X86TLBParams Params; 703499Ssaidi@eecs.umich.edu TLB(const Params *p); 713499Ssaidi@eecs.umich.edu 723814Ssaidi@eecs.umich.edu void takeOverFrom(BaseTLB *otlb) override {} 733499Ssaidi@eecs.umich.edu 743499Ssaidi@eecs.umich.edu TlbEntry *lookup(Addr va, bool update_lru = true); 753814Ssaidi@eecs.umich.edu 763499Ssaidi@eecs.umich.edu void setConfigAddress(uint32_t addr); 773499Ssaidi@eecs.umich.edu 783814Ssaidi@eecs.umich.edu protected: 793499Ssaidi@eecs.umich.edu 803499Ssaidi@eecs.umich.edu EntryList::iterator lookupIt(Addr va, bool update_lru = true); 813814Ssaidi@eecs.umich.edu 823499Ssaidi@eecs.umich.edu Walker * walker; 833499Ssaidi@eecs.umich.edu 848461SAli.Saidi@ARM.com public: 858461SAli.Saidi@ARM.com Walker *getWalker(); 868461SAli.Saidi@ARM.com 878461SAli.Saidi@ARM.com void flushAll() override; 883499Ssaidi@eecs.umich.edu 891817SN/A void flushNonGlobal(); 902539SN/A 911817SN/A void demapPage(Addr va, uint64_t asn) override; 921817SN/A 932542SN/A protected: 943349Sbinkertn@umich.edu uint32_t size; 951817SN/A 964986Ssaidi@eecs.umich.edu std::vector<TlbEntry> tlb; 974762Snate@binkert.org 983814Ssaidi@eecs.umich.edu EntryList freeList; 993814Ssaidi@eecs.umich.edu 1003814Ssaidi@eecs.umich.edu TlbEntryTrie trie; 1013814Ssaidi@eecs.umich.edu uint64_t lruSeq; 1023814Ssaidi@eecs.umich.edu 1033814Ssaidi@eecs.umich.edu // Statistics 1043814Ssaidi@eecs.umich.edu Stats::Scalar rdAccesses; 1053814Ssaidi@eecs.umich.edu Stats::Scalar wrAccesses; 1063814Ssaidi@eecs.umich.edu Stats::Scalar rdMisses; 1073814Ssaidi@eecs.umich.edu Stats::Scalar wrMisses; 1083814Ssaidi@eecs.umich.edu 1093814Ssaidi@eecs.umich.edu Fault translateInt(RequestPtr req, ThreadContext *tc); 1103814Ssaidi@eecs.umich.edu 1113814Ssaidi@eecs.umich.edu Fault translate(RequestPtr req, ThreadContext *tc, 1123814Ssaidi@eecs.umich.edu Translation *translation, Mode mode, 11310415SCurtis.Dunham@arm.com bool &delayedResponse, bool timing); 1143814Ssaidi@eecs.umich.edu 1153814Ssaidi@eecs.umich.edu public: 1163814Ssaidi@eecs.umich.edu 1173814Ssaidi@eecs.umich.edu void evictLRU(); 1184762Snate@binkert.org 1195192Ssaidi@eecs.umich.edu uint64_t 1203499Ssaidi@eecs.umich.edu nextSeq() 1214870Sstever@eecs.umich.edu { 1223499Ssaidi@eecs.umich.edu return ++lruSeq; 1235192Ssaidi@eecs.umich.edu } 1243499Ssaidi@eecs.umich.edu 1253814Ssaidi@eecs.umich.edu Fault translateAtomic( 1264762Snate@binkert.org RequestPtr req, ThreadContext *tc, Mode mode) override; 1273814Ssaidi@eecs.umich.edu void translateTiming( 1283814Ssaidi@eecs.umich.edu RequestPtr req, ThreadContext *tc, 1293814Ssaidi@eecs.umich.edu Translation *translation, Mode mode) override; 1303814Ssaidi@eecs.umich.edu 1313814Ssaidi@eecs.umich.edu /** 1323814Ssaidi@eecs.umich.edu * Do post-translation physical address finalization. 1333814Ssaidi@eecs.umich.edu * 1343814Ssaidi@eecs.umich.edu * Some addresses, for example requests going to the APIC, 1353814Ssaidi@eecs.umich.edu * need post-translation updates. Such physical addresses are 1363814Ssaidi@eecs.umich.edu * remapped into a "magic" part of the physical address space 1373814Ssaidi@eecs.umich.edu * by this method. 1383814Ssaidi@eecs.umich.edu * 1393814Ssaidi@eecs.umich.edu * @param req Request to updated in-place. 1403814Ssaidi@eecs.umich.edu * @param tc Thread context that created the request. 1413814Ssaidi@eecs.umich.edu * @param mode Request type (read/write/execute). 1423814Ssaidi@eecs.umich.edu * @return A fault on failure, NoFault otherwise. 1433814Ssaidi@eecs.umich.edu */ 1443499Ssaidi@eecs.umich.edu Fault finalizePhysical(RequestPtr req, ThreadContext *tc, 1453488Sktlim@umich.edu Mode mode) const override; 1463488Sktlim@umich.edu 1473488Sktlim@umich.edu TlbEntry *insert(Addr vpn, const TlbEntry &entry); 1484762Snate@binkert.org 1494762Snate@binkert.org /* 1501817SN/A * Function to register Stats 1514762Snate@binkert.org */ 1521817SN/A void regStats() override; 153 154 // Checkpointing 155 void serialize(CheckpointOut &cp) const override; 156 void unserialize(CheckpointIn &cp) override; 157 158 /** 159 * Get the table walker master port. This is used for 160 * migrating port connections during a CPU takeOverFrom() 161 * call. For architectures that do not have a table walker, 162 * NULL is returned, hence the use of a pointer rather than a 163 * reference. For X86 this method will always return a valid 164 * port pointer. 165 * 166 * @return A pointer to the walker master port 167 */ 168 BaseMasterPort *getMasterPort() override; 169 }; 170} 171 172#endif // __ARCH_X86_TLB_HH__ 173