tlb.hh revision 12140
19259SAli.Saidi@ARM.com/* 29259SAli.Saidi@ARM.com * Copyright (c) 2007 The Hewlett-Packard Development Company 39259SAli.Saidi@ARM.com * All rights reserved. 49259SAli.Saidi@ARM.com * 59259SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 69259SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 79259SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 89259SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 99259SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 109259SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 119259SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 129259SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 139259SAli.Saidi@ARM.com * 149259SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 159259SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 169259SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 179259SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 189259SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 199259SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 209259SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 219259SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 229259SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 239259SAli.Saidi@ARM.com * this software without specific prior written permission. 249259SAli.Saidi@ARM.com * 259259SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 269259SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 279259SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 289259SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 299259SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 309259SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 319259SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 329259SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 339259SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 349259SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 359259SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 369259SAli.Saidi@ARM.com * 379259SAli.Saidi@ARM.com * Authors: Gabe Black 389259SAli.Saidi@ARM.com */ 399259SAli.Saidi@ARM.com 409259SAli.Saidi@ARM.com#ifndef __ARCH_X86_TLB_HH__ 419259SAli.Saidi@ARM.com#define __ARCH_X86_TLB_HH__ 429259SAli.Saidi@ARM.com 439259SAli.Saidi@ARM.com#include <list> 449259SAli.Saidi@ARM.com#include <vector> 459259SAli.Saidi@ARM.com 469259SAli.Saidi@ARM.com#include "arch/generic/tlb.hh" 479259SAli.Saidi@ARM.com#include "arch/x86/pagetable.hh" 489259SAli.Saidi@ARM.com#include "base/trie.hh" 499259SAli.Saidi@ARM.com#include "mem/request.hh" 509259SAli.Saidi@ARM.com#include "params/X86TLB.hh" 519259SAli.Saidi@ARM.com 529259SAli.Saidi@ARM.comclass ThreadContext; 539259SAli.Saidi@ARM.com 549259SAli.Saidi@ARM.comnamespace X86ISA 559259SAli.Saidi@ARM.com{ 569259SAli.Saidi@ARM.com class Walker; 579259SAli.Saidi@ARM.com 589259SAli.Saidi@ARM.com class TLB : public BaseTLB 599259SAli.Saidi@ARM.com { 609259SAli.Saidi@ARM.com protected: 619259SAli.Saidi@ARM.com friend class Walker; 629294Sandreas.hansson@arm.com 639294Sandreas.hansson@arm.com typedef std::list<TlbEntry *> EntryList; 649259SAli.Saidi@ARM.com 659259SAli.Saidi@ARM.com uint32_t configAddress; 669259SAli.Saidi@ARM.com 679259SAli.Saidi@ARM.com public: 689259SAli.Saidi@ARM.com 699259SAli.Saidi@ARM.com typedef X86TLBParams Params; 709259SAli.Saidi@ARM.com TLB(const Params *p); 719259SAli.Saidi@ARM.com 729294Sandreas.hansson@arm.com void takeOverFrom(BaseTLB *otlb) override {} 739294Sandreas.hansson@arm.com 749259SAli.Saidi@ARM.com TlbEntry *lookup(Addr va, bool update_lru = true); 759259SAli.Saidi@ARM.com 769259SAli.Saidi@ARM.com void setConfigAddress(uint32_t addr); 779259SAli.Saidi@ARM.com 789259SAli.Saidi@ARM.com protected: 799259SAli.Saidi@ARM.com 809259SAli.Saidi@ARM.com EntryList::iterator lookupIt(Addr va, bool update_lru = true); 819259SAli.Saidi@ARM.com 829259SAli.Saidi@ARM.com Walker * walker; 839259SAli.Saidi@ARM.com 849259SAli.Saidi@ARM.com public: 859259SAli.Saidi@ARM.com Walker *getWalker(); 869259SAli.Saidi@ARM.com 879259SAli.Saidi@ARM.com void flushAll() override; 889259SAli.Saidi@ARM.com 899259SAli.Saidi@ARM.com void flushNonGlobal(); 909259SAli.Saidi@ARM.com 919259SAli.Saidi@ARM.com void demapPage(Addr va, uint64_t asn) override; 929259SAli.Saidi@ARM.com 939259SAli.Saidi@ARM.com protected: 949259SAli.Saidi@ARM.com uint32_t size; 959259SAli.Saidi@ARM.com 969259SAli.Saidi@ARM.com std::vector<TlbEntry> tlb; 979259SAli.Saidi@ARM.com 989259SAli.Saidi@ARM.com EntryList freeList; 999259SAli.Saidi@ARM.com 1009259SAli.Saidi@ARM.com TlbEntryTrie trie; 1019259SAli.Saidi@ARM.com uint64_t lruSeq; 1029259SAli.Saidi@ARM.com 1039259SAli.Saidi@ARM.com // Statistics 1049259SAli.Saidi@ARM.com Stats::Scalar rdAccesses; 1059259SAli.Saidi@ARM.com Stats::Scalar wrAccesses; 1069259SAli.Saidi@ARM.com Stats::Scalar rdMisses; 1079259SAli.Saidi@ARM.com Stats::Scalar wrMisses; 1089259SAli.Saidi@ARM.com 1099259SAli.Saidi@ARM.com Fault translateInt(RequestPtr req, ThreadContext *tc); 1109259SAli.Saidi@ARM.com 1119259SAli.Saidi@ARM.com Fault translate(RequestPtr req, ThreadContext *tc, 1129259SAli.Saidi@ARM.com Translation *translation, Mode mode, 1139259SAli.Saidi@ARM.com bool &delayedResponse, bool timing); 1149259SAli.Saidi@ARM.com 1159259SAli.Saidi@ARM.com public: 1169259SAli.Saidi@ARM.com 1179259SAli.Saidi@ARM.com void evictLRU(); 1189259SAli.Saidi@ARM.com 1199259SAli.Saidi@ARM.com uint64_t 1209259SAli.Saidi@ARM.com nextSeq() 1219259SAli.Saidi@ARM.com { 1229259SAli.Saidi@ARM.com return ++lruSeq; 1239259SAli.Saidi@ARM.com } 1249259SAli.Saidi@ARM.com 1259259SAli.Saidi@ARM.com Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); 1269259SAli.Saidi@ARM.com void translateTiming(RequestPtr req, ThreadContext *tc, 1279259SAli.Saidi@ARM.com Translation *translation, Mode mode); 1289259SAli.Saidi@ARM.com /** Stub function for compilation support of CheckerCPU. x86 ISA does 1299259SAli.Saidi@ARM.com * not support Checker model at the moment 1309259SAli.Saidi@ARM.com */ 1319259SAli.Saidi@ARM.com Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode); 1329259SAli.Saidi@ARM.com 1339259SAli.Saidi@ARM.com /** 1349259SAli.Saidi@ARM.com * Do post-translation physical address finalization. 1359259SAli.Saidi@ARM.com * 1369259SAli.Saidi@ARM.com * Some addresses, for example requests going to the APIC, 1379259SAli.Saidi@ARM.com * need post-translation updates. Such physical addresses are 1389259SAli.Saidi@ARM.com * remapped into a "magic" part of the physical address space 1399259SAli.Saidi@ARM.com * by this method. 1409259SAli.Saidi@ARM.com * 1419259SAli.Saidi@ARM.com * @param req Request to updated in-place. 1429259SAli.Saidi@ARM.com * @param tc Thread context that created the request. 1439259SAli.Saidi@ARM.com * @param mode Request type (read/write/execute). 1449259SAli.Saidi@ARM.com * @return A fault on failure, NoFault otherwise. 1459259SAli.Saidi@ARM.com */ 1469259SAli.Saidi@ARM.com Fault finalizePhysical(RequestPtr req, ThreadContext *tc, 1479259SAli.Saidi@ARM.com Mode mode) const; 1489259SAli.Saidi@ARM.com 1499259SAli.Saidi@ARM.com TlbEntry * insert(Addr vpn, TlbEntry &entry); 1509259SAli.Saidi@ARM.com 1519259SAli.Saidi@ARM.com /* 1529259SAli.Saidi@ARM.com * Function to register Stats 1539259SAli.Saidi@ARM.com */ 1549259SAli.Saidi@ARM.com void regStats(); 1559259SAli.Saidi@ARM.com 1569259SAli.Saidi@ARM.com // Checkpointing 1579259SAli.Saidi@ARM.com void serialize(CheckpointOut &cp) const override; 1589259SAli.Saidi@ARM.com void unserialize(CheckpointIn &cp) override; 1599259SAli.Saidi@ARM.com 1609259SAli.Saidi@ARM.com /** 1619259SAli.Saidi@ARM.com * Get the table walker master port. This is used for 1629259SAli.Saidi@ARM.com * migrating port connections during a CPU takeOverFrom() 1639259SAli.Saidi@ARM.com * call. For architectures that do not have a table walker, 1649259SAli.Saidi@ARM.com * NULL is returned, hence the use of a pointer rather than a 1659259SAli.Saidi@ARM.com * reference. For X86 this method will always return a valid 1669259SAli.Saidi@ARM.com * port pointer. 1679259SAli.Saidi@ARM.com * 1689259SAli.Saidi@ARM.com * @return A pointer to the walker master port 1699259SAli.Saidi@ARM.com */ 1709259SAli.Saidi@ARM.com BaseMasterPort *getMasterPort() override; 1719259SAli.Saidi@ARM.com }; 1729259SAli.Saidi@ARM.com} 1739259SAli.Saidi@ARM.com 1749259SAli.Saidi@ARM.com#endif // __ARCH_X86_TLB_HH__ 1759259SAli.Saidi@ARM.com