tlb.cc revision 13937
112752Sodanrc@yahoo.com.br/* 212752Sodanrc@yahoo.com.br * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 312752Sodanrc@yahoo.com.br * All rights reserved. 412752Sodanrc@yahoo.com.br * 512752Sodanrc@yahoo.com.br * The license below extends only to copyright in the software and shall 612752Sodanrc@yahoo.com.br * not be construed as granting a license to any other intellectual 712752Sodanrc@yahoo.com.br * property including but not limited to intellectual property relating 812752Sodanrc@yahoo.com.br * to a hardware implementation of the functionality of the software 912752Sodanrc@yahoo.com.br * licensed hereunder. You may use the software subject to the license 1012752Sodanrc@yahoo.com.br * terms below provided that you ensure that this notice is replicated 1112752Sodanrc@yahoo.com.br * unmodified and in its entirety in all distributions of the software, 1212752Sodanrc@yahoo.com.br * modified or unmodified, in source code or in binary form. 1312752Sodanrc@yahoo.com.br * 1412752Sodanrc@yahoo.com.br * Redistribution and use in source and binary forms, with or without 1512752Sodanrc@yahoo.com.br * modification, are permitted provided that the following conditions are 1612752Sodanrc@yahoo.com.br * met: redistributions of source code must retain the above copyright 1712752Sodanrc@yahoo.com.br * notice, this list of conditions and the following disclaimer; 1812752Sodanrc@yahoo.com.br * redistributions in binary form must reproduce the above copyright 1912752Sodanrc@yahoo.com.br * notice, this list of conditions and the following disclaimer in the 2012752Sodanrc@yahoo.com.br * documentation and/or other materials provided with the distribution; 2112752Sodanrc@yahoo.com.br * neither the name of the copyright holders nor the names of its 2212752Sodanrc@yahoo.com.br * contributors may be used to endorse or promote products derived from 2312752Sodanrc@yahoo.com.br * this software without specific prior written permission. 2412752Sodanrc@yahoo.com.br * 2512752Sodanrc@yahoo.com.br * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2612752Sodanrc@yahoo.com.br * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2712752Sodanrc@yahoo.com.br * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2812752Sodanrc@yahoo.com.br * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2912752Sodanrc@yahoo.com.br * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3012752Sodanrc@yahoo.com.br * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3112752Sodanrc@yahoo.com.br * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3212752Sodanrc@yahoo.com.br * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3312752Sodanrc@yahoo.com.br * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3412752Sodanrc@yahoo.com.br * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3512752Sodanrc@yahoo.com.br * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3612752Sodanrc@yahoo.com.br * 3712752Sodanrc@yahoo.com.br * Authors: Gabe Black 3812752Sodanrc@yahoo.com.br */ 3912752Sodanrc@yahoo.com.br 4012752Sodanrc@yahoo.com.br#include "arch/x86/tlb.hh" 4112752Sodanrc@yahoo.com.br 4212752Sodanrc@yahoo.com.br#include <cstring> 4312752Sodanrc@yahoo.com.br#include <memory> 4412752Sodanrc@yahoo.com.br 4512752Sodanrc@yahoo.com.br#include "arch/generic/mmapped_ipr.hh" 4612752Sodanrc@yahoo.com.br#include "arch/x86/faults.hh" 4712773Sodanrc@yahoo.com.br#include "arch/x86/insts/microldstop.hh" 4812752Sodanrc@yahoo.com.br#include "arch/x86/pagetable_walker.hh" 4912752Sodanrc@yahoo.com.br#include "arch/x86/regs/misc.hh" 5012752Sodanrc@yahoo.com.br#include "arch/x86/regs/msr.hh" 5112752Sodanrc@yahoo.com.br#include "arch/x86/x86_traits.hh" 5212752Sodanrc@yahoo.com.br#include "base/trace.hh" 5312752Sodanrc@yahoo.com.br#include "cpu/thread_context.hh" 5412752Sodanrc@yahoo.com.br#include "debug/TLB.hh" 5512752Sodanrc@yahoo.com.br#include "mem/page_table.hh" 5612752Sodanrc@yahoo.com.br#include "mem/request.hh" 5712752Sodanrc@yahoo.com.br#include "sim/full_system.hh" 5812752Sodanrc@yahoo.com.br#include "sim/process.hh" 5912752Sodanrc@yahoo.com.br 6012752Sodanrc@yahoo.com.brnamespace X86ISA { 6112752Sodanrc@yahoo.com.br 6212752Sodanrc@yahoo.com.brTLB::TLB(const Params *p) 6312752Sodanrc@yahoo.com.br : BaseTLB(p), configAddress(0), size(p->size), 6412752Sodanrc@yahoo.com.br tlb(size), lruSeq(0) 6512752Sodanrc@yahoo.com.br{ 6612752Sodanrc@yahoo.com.br if (!size) 6712752Sodanrc@yahoo.com.br fatal("TLBs must have a non-zero size.\n"); 6812752Sodanrc@yahoo.com.br 6912752Sodanrc@yahoo.com.br for (int x = 0; x < size; x++) { 7012752Sodanrc@yahoo.com.br tlb[x].trieHandle = NULL; 7112752Sodanrc@yahoo.com.br freeList.push_back(&tlb[x]); 7212752Sodanrc@yahoo.com.br } 7312752Sodanrc@yahoo.com.br 7412752Sodanrc@yahoo.com.br walker = p->walker; 7512752Sodanrc@yahoo.com.br walker->setTLB(this); 7612752Sodanrc@yahoo.com.br} 7712752Sodanrc@yahoo.com.br 7812752Sodanrc@yahoo.com.brvoid 7912752Sodanrc@yahoo.com.brTLB::evictLRU() 8012752Sodanrc@yahoo.com.br{ 8112752Sodanrc@yahoo.com.br // Find the entry with the lowest (and hence least recently updated) 8212752Sodanrc@yahoo.com.br // sequence number. 8312752Sodanrc@yahoo.com.br 8412752Sodanrc@yahoo.com.br unsigned lru = 0; 8512752Sodanrc@yahoo.com.br for (unsigned i = 1; i < size; i++) { 8612752Sodanrc@yahoo.com.br if (tlb[i].lruSeq < tlb[lru].lruSeq) 8712752Sodanrc@yahoo.com.br lru = i; 8812752Sodanrc@yahoo.com.br } 8912752Sodanrc@yahoo.com.br 9012752Sodanrc@yahoo.com.br assert(tlb[lru].trieHandle); 9112752Sodanrc@yahoo.com.br trie.remove(tlb[lru].trieHandle); 9212752Sodanrc@yahoo.com.br tlb[lru].trieHandle = NULL; 9312752Sodanrc@yahoo.com.br freeList.push_back(&tlb[lru]); 9412752Sodanrc@yahoo.com.br} 9512752Sodanrc@yahoo.com.br 9612752Sodanrc@yahoo.com.brTlbEntry * 9712752Sodanrc@yahoo.com.brTLB::insert(Addr vpn, const TlbEntry &entry) 9812752Sodanrc@yahoo.com.br{ 9912752Sodanrc@yahoo.com.br // If somebody beat us to it, just use that existing entry. 10012752Sodanrc@yahoo.com.br TlbEntry *newEntry = trie.lookup(vpn); 10112752Sodanrc@yahoo.com.br if (newEntry) { 10212752Sodanrc@yahoo.com.br assert(newEntry->vaddr == vpn); 10312752Sodanrc@yahoo.com.br return newEntry; 10412752Sodanrc@yahoo.com.br } 10512752Sodanrc@yahoo.com.br 10612752Sodanrc@yahoo.com.br if (freeList.empty()) 10712752Sodanrc@yahoo.com.br evictLRU(); 10812752Sodanrc@yahoo.com.br 10912752Sodanrc@yahoo.com.br newEntry = freeList.front(); 11012752Sodanrc@yahoo.com.br freeList.pop_front(); 11112752Sodanrc@yahoo.com.br 11212752Sodanrc@yahoo.com.br *newEntry = entry; 11312752Sodanrc@yahoo.com.br newEntry->lruSeq = nextSeq(); 11412752Sodanrc@yahoo.com.br newEntry->vaddr = vpn; 11512752Sodanrc@yahoo.com.br newEntry->trieHandle = 11612752Sodanrc@yahoo.com.br trie.insert(vpn, TlbEntryTrie::MaxBits - entry.logBytes, newEntry); 11712752Sodanrc@yahoo.com.br return newEntry; 11812752Sodanrc@yahoo.com.br} 11912752Sodanrc@yahoo.com.br 12012752Sodanrc@yahoo.com.brTlbEntry * 12112752Sodanrc@yahoo.com.brTLB::lookup(Addr va, bool update_lru) 12212752Sodanrc@yahoo.com.br{ 12312752Sodanrc@yahoo.com.br TlbEntry *entry = trie.lookup(va); 12412752Sodanrc@yahoo.com.br if (entry && update_lru) 12512752Sodanrc@yahoo.com.br entry->lruSeq = nextSeq(); 12612752Sodanrc@yahoo.com.br return entry; 12712752Sodanrc@yahoo.com.br} 12812752Sodanrc@yahoo.com.br 12912752Sodanrc@yahoo.com.brvoid 13012752Sodanrc@yahoo.com.brTLB::flushAll() 13112752Sodanrc@yahoo.com.br{ 13212752Sodanrc@yahoo.com.br DPRINTF(TLB, "Invalidating all entries.\n"); 13312752Sodanrc@yahoo.com.br for (unsigned i = 0; i < size; i++) { 13412752Sodanrc@yahoo.com.br if (tlb[i].trieHandle) { 13512752Sodanrc@yahoo.com.br trie.remove(tlb[i].trieHandle); 13612752Sodanrc@yahoo.com.br tlb[i].trieHandle = NULL; 13712752Sodanrc@yahoo.com.br freeList.push_back(&tlb[i]); 13812752Sodanrc@yahoo.com.br } 13912752Sodanrc@yahoo.com.br } 14012752Sodanrc@yahoo.com.br} 14112752Sodanrc@yahoo.com.br 14212752Sodanrc@yahoo.com.brvoid 14312752Sodanrc@yahoo.com.brTLB::setConfigAddress(uint32_t addr) 14412752Sodanrc@yahoo.com.br{ 14512752Sodanrc@yahoo.com.br configAddress = addr; 14612752Sodanrc@yahoo.com.br} 14712752Sodanrc@yahoo.com.br 14812752Sodanrc@yahoo.com.brvoid 14912752Sodanrc@yahoo.com.brTLB::flushNonGlobal() 15012752Sodanrc@yahoo.com.br{ 15112752Sodanrc@yahoo.com.br DPRINTF(TLB, "Invalidating all non global entries.\n"); 15213215Sodanrc@yahoo.com.br for (unsigned i = 0; i < size; i++) { 15313215Sodanrc@yahoo.com.br if (tlb[i].trieHandle && !tlb[i].global) { 15413215Sodanrc@yahoo.com.br trie.remove(tlb[i].trieHandle); 15513215Sodanrc@yahoo.com.br tlb[i].trieHandle = NULL; 15612752Sodanrc@yahoo.com.br freeList.push_back(&tlb[i]); 15712752Sodanrc@yahoo.com.br } 15813215Sodanrc@yahoo.com.br } 15913215Sodanrc@yahoo.com.br} 16013215Sodanrc@yahoo.com.br 16112752Sodanrc@yahoo.com.brvoid 16212752Sodanrc@yahoo.com.brTLB::demapPage(Addr va, uint64_t asn) 16312752Sodanrc@yahoo.com.br{ 16412752Sodanrc@yahoo.com.br TlbEntry *entry = trie.lookup(va); 16512752Sodanrc@yahoo.com.br if (entry) { 16612752Sodanrc@yahoo.com.br trie.remove(entry->trieHandle); 16712752Sodanrc@yahoo.com.br entry->trieHandle = NULL; 16812752Sodanrc@yahoo.com.br freeList.push_back(entry); 16912752Sodanrc@yahoo.com.br } 17012752Sodanrc@yahoo.com.br} 17112752Sodanrc@yahoo.com.br 17212752Sodanrc@yahoo.com.brFault 17312752Sodanrc@yahoo.com.brTLB::translateInt(const RequestPtr &req, ThreadContext *tc) 17412752Sodanrc@yahoo.com.br{ 17512752Sodanrc@yahoo.com.br DPRINTF(TLB, "Addresses references internal memory.\n"); 17612752Sodanrc@yahoo.com.br Addr vaddr = req->getVaddr(); 17712752Sodanrc@yahoo.com.br Addr prefix = (vaddr >> 3) & IntAddrPrefixMask; 17812752Sodanrc@yahoo.com.br if (prefix == IntAddrPrefixCPUID) { 17912752Sodanrc@yahoo.com.br panic("CPUID memory space not yet implemented!\n"); 18012752Sodanrc@yahoo.com.br } else if (prefix == IntAddrPrefixMSR) { 18112752Sodanrc@yahoo.com.br vaddr = (vaddr >> 3) & ~IntAddrPrefixMask; 18212752Sodanrc@yahoo.com.br req->setFlags(Request::MMAPPED_IPR); 18312752Sodanrc@yahoo.com.br 18412752Sodanrc@yahoo.com.br MiscRegIndex regNum; 18512752Sodanrc@yahoo.com.br if (!msrAddrToIndex(regNum, vaddr)) 18612752Sodanrc@yahoo.com.br return std::make_shared<GeneralProtection>(0); 18712752Sodanrc@yahoo.com.br 18812752Sodanrc@yahoo.com.br //The index is multiplied by the size of a RegVal so that 18912752Sodanrc@yahoo.com.br //any memory dependence calculations will not see these as 19012752Sodanrc@yahoo.com.br //overlapping. 19112752Sodanrc@yahoo.com.br req->setPaddr((Addr)regNum * sizeof(RegVal)); 19212752Sodanrc@yahoo.com.br return NoFault; 19312752Sodanrc@yahoo.com.br } else if (prefix == IntAddrPrefixIO) { 19412752Sodanrc@yahoo.com.br // TODO If CPL > IOPL or in virtual mode, check the I/O permission 19512752Sodanrc@yahoo.com.br // bitmap in the TSS. 19612752Sodanrc@yahoo.com.br 19712752Sodanrc@yahoo.com.br Addr IOPort = vaddr & ~IntAddrPrefixMask; 19812752Sodanrc@yahoo.com.br // Make sure the address fits in the expected 16 bit IO address 19912752Sodanrc@yahoo.com.br // space. 20012752Sodanrc@yahoo.com.br assert(!(IOPort & ~0xFFFF)); 20112752Sodanrc@yahoo.com.br if (IOPort == 0xCF8 && req->getSize() == 4) { 20212752Sodanrc@yahoo.com.br req->setFlags(Request::MMAPPED_IPR); 20312752Sodanrc@yahoo.com.br req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(RegVal)); 20412752Sodanrc@yahoo.com.br } else if ((IOPort & ~mask(2)) == 0xCFC) { 20512752Sodanrc@yahoo.com.br req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 20612752Sodanrc@yahoo.com.br Addr configAddress = 20712752Sodanrc@yahoo.com.br tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS); 20812752Sodanrc@yahoo.com.br if (bits(configAddress, 31, 31)) { 20912752Sodanrc@yahoo.com.br req->setPaddr(PhysAddrPrefixPciConfig | 21012752Sodanrc@yahoo.com.br mbits(configAddress, 30, 2) | 21112752Sodanrc@yahoo.com.br (IOPort & mask(2))); 21212752Sodanrc@yahoo.com.br } else { 21312752Sodanrc@yahoo.com.br req->setPaddr(PhysAddrPrefixIO | IOPort); 21412752Sodanrc@yahoo.com.br } 21512752Sodanrc@yahoo.com.br } else { 21612752Sodanrc@yahoo.com.br req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 21712752Sodanrc@yahoo.com.br req->setPaddr(PhysAddrPrefixIO | IOPort); 21812752Sodanrc@yahoo.com.br } 21912752Sodanrc@yahoo.com.br return NoFault; 22012752Sodanrc@yahoo.com.br } else { 22112752Sodanrc@yahoo.com.br panic("Access to unrecognized internal address space %#x.\n", 22212752Sodanrc@yahoo.com.br prefix); 22312752Sodanrc@yahoo.com.br } 22412752Sodanrc@yahoo.com.br} 22512752Sodanrc@yahoo.com.br 22612752Sodanrc@yahoo.com.brFault 22712752Sodanrc@yahoo.com.brTLB::finalizePhysical(const RequestPtr &req, 22812752Sodanrc@yahoo.com.br ThreadContext *tc, Mode mode) const 22912752Sodanrc@yahoo.com.br{ 23012752Sodanrc@yahoo.com.br Addr paddr = req->getPaddr(); 23112752Sodanrc@yahoo.com.br 23212752Sodanrc@yahoo.com.br AddrRange m5opRange(0xFFFF0000, 0xFFFFFFFF); 23312752Sodanrc@yahoo.com.br 23412752Sodanrc@yahoo.com.br if (m5opRange.contains(paddr)) { 23512752Sodanrc@yahoo.com.br req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR | 23612752Sodanrc@yahoo.com.br Request::STRICT_ORDER); 23712752Sodanrc@yahoo.com.br req->setPaddr(GenericISA::iprAddressPseudoInst((paddr >> 8) & 0xFF, 23812752Sodanrc@yahoo.com.br paddr & 0xFF)); 23912752Sodanrc@yahoo.com.br } else if (FullSystem) { 24012752Sodanrc@yahoo.com.br // Check for an access to the local APIC 24112752Sodanrc@yahoo.com.br LocalApicBase localApicBase = 24212752Sodanrc@yahoo.com.br tc->readMiscRegNoEffect(MISCREG_APIC_BASE); 24312752Sodanrc@yahoo.com.br AddrRange apicRange(localApicBase.base * PageBytes, 24412752Sodanrc@yahoo.com.br (localApicBase.base + 1) * PageBytes - 1); 24512752Sodanrc@yahoo.com.br 24612752Sodanrc@yahoo.com.br if (apicRange.contains(paddr)) { 247 // The Intel developer's manuals say the below restrictions apply, 248 // but the linux kernel, because of a compiler optimization, breaks 249 // them. 250 /* 251 // Check alignment 252 if (paddr & ((32/8) - 1)) 253 return new GeneralProtection(0); 254 // Check access size 255 if (req->getSize() != (32/8)) 256 return new GeneralProtection(0); 257 */ 258 // Force the access to be uncacheable. 259 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 260 req->setPaddr(x86LocalAPICAddress(tc->contextId(), 261 paddr - apicRange.start())); 262 } 263 } 264 265 return NoFault; 266} 267 268Fault 269TLB::translate(const RequestPtr &req, 270 ThreadContext *tc, Translation *translation, 271 Mode mode, bool &delayedResponse, bool timing) 272{ 273 Request::Flags flags = req->getFlags(); 274 int seg = flags & SegmentFlagMask; 275 bool storeCheck = flags & (StoreCheck << FlagShift); 276 277 delayedResponse = false; 278 279 // If this is true, we're dealing with a request to a non-memory address 280 // space. 281 if (seg == SEGMENT_REG_MS) { 282 return translateInt(req, tc); 283 } 284 285 Addr vaddr = req->getVaddr(); 286 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr); 287 288 HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); 289 290 // If protected mode has been enabled... 291 if (m5Reg.prot) { 292 DPRINTF(TLB, "In protected mode.\n"); 293 // If we're not in 64-bit mode, do protection/limit checks 294 if (m5Reg.mode != LongMode) { 295 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n"); 296 // Check for a NULL segment selector. 297 if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR || 298 seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS) 299 && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg))) 300 return std::make_shared<GeneralProtection>(0); 301 bool expandDown = false; 302 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg)); 303 if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) { 304 if (!attr.writable && (mode == Write || storeCheck)) 305 return std::make_shared<GeneralProtection>(0); 306 if (!attr.readable && mode == Read) 307 return std::make_shared<GeneralProtection>(0); 308 expandDown = attr.expandDown; 309 310 } 311 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg)); 312 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg)); 313 bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift)); 314 unsigned logSize = sizeOverride ? (unsigned)m5Reg.altAddr 315 : (unsigned)m5Reg.defAddr; 316 int size = (1 << logSize) * 8; 317 Addr offset = bits(vaddr - base, size - 1, 0); 318 Addr endOffset = offset + req->getSize() - 1; 319 if (expandDown) { 320 DPRINTF(TLB, "Checking an expand down segment.\n"); 321 warn_once("Expand down segments are untested.\n"); 322 if (offset <= limit || endOffset <= limit) 323 return std::make_shared<GeneralProtection>(0); 324 } else { 325 if (offset > limit || endOffset > limit) 326 return std::make_shared<GeneralProtection>(0); 327 } 328 } 329 if (m5Reg.submode != SixtyFourBitMode || 330 (flags & (AddrSizeFlagBit << FlagShift))) 331 vaddr &= mask(32); 332 // If paging is enabled, do the translation. 333 if (m5Reg.paging) { 334 DPRINTF(TLB, "Paging enabled.\n"); 335 // The vaddr already has the segment base applied. 336 TlbEntry *entry = lookup(vaddr); 337 if (mode == Read) { 338 rdAccesses++; 339 } else { 340 wrAccesses++; 341 } 342 if (!entry) { 343 DPRINTF(TLB, "Handling a TLB miss for " 344 "address %#x at pc %#x.\n", 345 vaddr, tc->instAddr()); 346 if (mode == Read) { 347 rdMisses++; 348 } else { 349 wrMisses++; 350 } 351 if (FullSystem) { 352 Fault fault = walker->start(tc, translation, req, mode); 353 if (timing || fault != NoFault) { 354 // This gets ignored in atomic mode. 355 delayedResponse = true; 356 return fault; 357 } 358 entry = lookup(vaddr); 359 assert(entry); 360 } else { 361 Process *p = tc->getProcessPtr(); 362 const EmulationPageTable::Entry *pte = 363 p->pTable->lookup(vaddr); 364 if (!pte && mode != Execute) { 365 // Check if we just need to grow the stack. 366 if (p->fixupStackFault(vaddr)) { 367 // If we did, lookup the entry for the new page. 368 pte = p->pTable->lookup(vaddr); 369 } 370 } 371 if (!pte) { 372 return std::make_shared<PageFault>(vaddr, true, mode, 373 true, false); 374 } else { 375 Addr alignedVaddr = p->pTable->pageAlign(vaddr); 376 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, 377 pte->paddr); 378 entry = insert(alignedVaddr, TlbEntry( 379 p->pTable->pid(), alignedVaddr, pte->paddr, 380 pte->flags & EmulationPageTable::Uncacheable, 381 pte->flags & EmulationPageTable::ReadOnly)); 382 } 383 DPRINTF(TLB, "Miss was serviced.\n"); 384 } 385 } 386 387 DPRINTF(TLB, "Entry found with paddr %#x, " 388 "doing protection checks.\n", entry->paddr); 389 // Do paging protection checks. 390 bool inUser = (m5Reg.cpl == 3 && 391 !(flags & (CPL0FlagBit << FlagShift))); 392 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 393 bool badWrite = (!entry->writable && (inUser || cr0.wp)); 394 if ((inUser && !entry->user) || (mode == Write && badWrite)) { 395 // The page must have been present to get into the TLB in 396 // the first place. We'll assume the reserved bits are 397 // fine even though we're not checking them. 398 return std::make_shared<PageFault>(vaddr, true, mode, inUser, 399 false); 400 } 401 if (storeCheck && badWrite) { 402 // This would fault if this were a write, so return a page 403 // fault that reflects that happening. 404 return std::make_shared<PageFault>(vaddr, true, Write, inUser, 405 false); 406 } 407 408 Addr paddr = entry->paddr | (vaddr & mask(entry->logBytes)); 409 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr); 410 req->setPaddr(paddr); 411 if (entry->uncacheable) 412 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 413 } else { 414 //Use the address which already has segmentation applied. 415 DPRINTF(TLB, "Paging disabled.\n"); 416 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 417 req->setPaddr(vaddr); 418 } 419 } else { 420 // Real mode 421 DPRINTF(TLB, "In real mode.\n"); 422 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 423 req->setPaddr(vaddr); 424 } 425 426 return finalizePhysical(req, tc, mode); 427} 428 429Fault 430TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode) 431{ 432 bool delayedResponse; 433 return TLB::translate(req, tc, NULL, mode, delayedResponse, false); 434} 435 436void 437TLB::translateTiming(const RequestPtr &req, ThreadContext *tc, 438 Translation *translation, Mode mode) 439{ 440 bool delayedResponse; 441 assert(translation); 442 Fault fault = 443 TLB::translate(req, tc, translation, mode, delayedResponse, true); 444 if (!delayedResponse) 445 translation->finish(fault, req, tc, mode); 446 else 447 translation->markDelayed(); 448} 449 450Walker * 451TLB::getWalker() 452{ 453 return walker; 454} 455 456void 457TLB::regStats() 458{ 459 using namespace Stats; 460 BaseTLB::regStats(); 461 rdAccesses 462 .name(name() + ".rdAccesses") 463 .desc("TLB accesses on read requests"); 464 465 wrAccesses 466 .name(name() + ".wrAccesses") 467 .desc("TLB accesses on write requests"); 468 469 rdMisses 470 .name(name() + ".rdMisses") 471 .desc("TLB misses on read requests"); 472 473 wrMisses 474 .name(name() + ".wrMisses") 475 .desc("TLB misses on write requests"); 476 477} 478 479void 480TLB::serialize(CheckpointOut &cp) const 481{ 482 // Only store the entries in use. 483 uint32_t _size = size - freeList.size(); 484 SERIALIZE_SCALAR(_size); 485 SERIALIZE_SCALAR(lruSeq); 486 487 uint32_t _count = 0; 488 for (uint32_t x = 0; x < size; x++) { 489 if (tlb[x].trieHandle != NULL) 490 tlb[x].serializeSection(cp, csprintf("Entry%d", _count++)); 491 } 492} 493 494void 495TLB::unserialize(CheckpointIn &cp) 496{ 497 // Do not allow to restore with a smaller tlb. 498 uint32_t _size; 499 UNSERIALIZE_SCALAR(_size); 500 if (_size > size) { 501 fatal("TLB size less than the one in checkpoint!"); 502 } 503 504 UNSERIALIZE_SCALAR(lruSeq); 505 506 for (uint32_t x = 0; x < _size; x++) { 507 TlbEntry *newEntry = freeList.front(); 508 freeList.pop_front(); 509 510 newEntry->unserializeSection(cp, csprintf("Entry%d", x)); 511 newEntry->trieHandle = trie.insert(newEntry->vaddr, 512 TlbEntryTrie::MaxBits - newEntry->logBytes, newEntry); 513 } 514} 515 516Port * 517TLB::getTableWalkerPort() 518{ 519 return &walker->getPort("port"); 520} 521 522} // namespace X86ISA 523 524X86ISA::TLB * 525X86TLBParams::create() 526{ 527 return new X86ISA::TLB(this); 528} 529