tlb.cc revision 10474:799c8ee4ecba
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include <cstring>
41#include <memory>
42
43#include "arch/generic/mmapped_ipr.hh"
44#include "arch/x86/insts/microldstop.hh"
45#include "arch/x86/regs/misc.hh"
46#include "arch/x86/regs/msr.hh"
47#include "arch/x86/faults.hh"
48#include "arch/x86/pagetable.hh"
49#include "arch/x86/pagetable_walker.hh"
50#include "arch/x86/tlb.hh"
51#include "arch/x86/x86_traits.hh"
52#include "base/bitfield.hh"
53#include "base/trace.hh"
54#include "cpu/base.hh"
55#include "cpu/thread_context.hh"
56#include "debug/TLB.hh"
57#include "mem/packet_access.hh"
58#include "mem/page_table.hh"
59#include "mem/request.hh"
60#include "sim/full_system.hh"
61#include "sim/process.hh"
62
63namespace X86ISA {
64
65TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size),
66    lruSeq(0)
67{
68    if (!size)
69        fatal("TLBs must have a non-zero size.\n");
70    tlb = new TlbEntry[size];
71    std::memset(tlb, 0, sizeof(TlbEntry) * size);
72
73    for (int x = 0; x < size; x++) {
74        tlb[x].trieHandle = NULL;
75        freeList.push_back(&tlb[x]);
76    }
77
78    walker = p->walker;
79    walker->setTLB(this);
80}
81
82void
83TLB::evictLRU()
84{
85    // Find the entry with the lowest (and hence least recently updated)
86    // sequence number.
87
88    unsigned lru = 0;
89    for (unsigned i = 1; i < size; i++) {
90        if (tlb[i].lruSeq < tlb[lru].lruSeq)
91            lru = i;
92    }
93
94    assert(tlb[lru].trieHandle);
95    trie.remove(tlb[lru].trieHandle);
96    tlb[lru].trieHandle = NULL;
97    freeList.push_back(&tlb[lru]);
98}
99
100TlbEntry *
101TLB::insert(Addr vpn, TlbEntry &entry)
102{
103    // If somebody beat us to it, just use that existing entry.
104    TlbEntry *newEntry = trie.lookup(vpn);
105    if (newEntry) {
106        assert(newEntry->vaddr == vpn);
107        return newEntry;
108    }
109
110    if (freeList.empty())
111        evictLRU();
112
113    newEntry = freeList.front();
114    freeList.pop_front();
115
116    *newEntry = entry;
117    newEntry->lruSeq = nextSeq();
118    newEntry->vaddr = vpn;
119    newEntry->trieHandle =
120    trie.insert(vpn, TlbEntryTrie::MaxBits - entry.logBytes, newEntry);
121    return newEntry;
122}
123
124TlbEntry *
125TLB::lookup(Addr va, bool update_lru)
126{
127    TlbEntry *entry = trie.lookup(va);
128    if (entry && update_lru)
129        entry->lruSeq = nextSeq();
130    return entry;
131}
132
133void
134TLB::flushAll()
135{
136    DPRINTF(TLB, "Invalidating all entries.\n");
137    for (unsigned i = 0; i < size; i++) {
138        if (tlb[i].trieHandle) {
139            trie.remove(tlb[i].trieHandle);
140            tlb[i].trieHandle = NULL;
141            freeList.push_back(&tlb[i]);
142        }
143    }
144}
145
146void
147TLB::setConfigAddress(uint32_t addr)
148{
149    configAddress = addr;
150}
151
152void
153TLB::flushNonGlobal()
154{
155    DPRINTF(TLB, "Invalidating all non global entries.\n");
156    for (unsigned i = 0; i < size; i++) {
157        if (tlb[i].trieHandle && !tlb[i].global) {
158            trie.remove(tlb[i].trieHandle);
159            tlb[i].trieHandle = NULL;
160            freeList.push_back(&tlb[i]);
161        }
162    }
163}
164
165void
166TLB::demapPage(Addr va, uint64_t asn)
167{
168    TlbEntry *entry = trie.lookup(va);
169    if (entry) {
170        trie.remove(entry->trieHandle);
171        entry->trieHandle = NULL;
172        freeList.push_back(entry);
173    }
174}
175
176Fault
177TLB::translateInt(RequestPtr req, ThreadContext *tc)
178{
179    DPRINTF(TLB, "Addresses references internal memory.\n");
180    Addr vaddr = req->getVaddr();
181    Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
182    if (prefix == IntAddrPrefixCPUID) {
183        panic("CPUID memory space not yet implemented!\n");
184    } else if (prefix == IntAddrPrefixMSR) {
185        vaddr = (vaddr >> 3) & ~IntAddrPrefixMask;
186        req->setFlags(Request::MMAPPED_IPR);
187
188        MiscRegIndex regNum;
189        if (!msrAddrToIndex(regNum, vaddr))
190            return std::make_shared<GeneralProtection>(0);
191
192        //The index is multiplied by the size of a MiscReg so that
193        //any memory dependence calculations will not see these as
194        //overlapping.
195        req->setPaddr((Addr)regNum * sizeof(MiscReg));
196        return NoFault;
197    } else if (prefix == IntAddrPrefixIO) {
198        // TODO If CPL > IOPL or in virtual mode, check the I/O permission
199        // bitmap in the TSS.
200
201        Addr IOPort = vaddr & ~IntAddrPrefixMask;
202        // Make sure the address fits in the expected 16 bit IO address
203        // space.
204        assert(!(IOPort & ~0xFFFF));
205        if (IOPort == 0xCF8 && req->getSize() == 4) {
206            req->setFlags(Request::MMAPPED_IPR);
207            req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
208        } else if ((IOPort & ~mask(2)) == 0xCFC) {
209            req->setFlags(Request::UNCACHEABLE);
210            Addr configAddress =
211                tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
212            if (bits(configAddress, 31, 31)) {
213                req->setPaddr(PhysAddrPrefixPciConfig |
214                        mbits(configAddress, 30, 2) |
215                        (IOPort & mask(2)));
216            } else {
217                req->setPaddr(PhysAddrPrefixIO | IOPort);
218            }
219        } else {
220            req->setFlags(Request::UNCACHEABLE);
221            req->setPaddr(PhysAddrPrefixIO | IOPort);
222        }
223        return NoFault;
224    } else {
225        panic("Access to unrecognized internal address space %#x.\n",
226                prefix);
227    }
228}
229
230Fault
231TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
232{
233    Addr paddr = req->getPaddr();
234
235    // Check for an access to the local APIC
236    if (FullSystem) {
237        LocalApicBase localApicBase =
238            tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
239        AddrRange apicRange(localApicBase.base * PageBytes,
240                            (localApicBase.base + 1) * PageBytes - 1);
241
242        AddrRange m5opRange(0xFFFF0000, 0xFFFFFFFF);
243
244        if (apicRange.contains(paddr)) {
245            // The Intel developer's manuals say the below restrictions apply,
246            // but the linux kernel, because of a compiler optimization, breaks
247            // them.
248            /*
249            // Check alignment
250            if (paddr & ((32/8) - 1))
251                return new GeneralProtection(0);
252            // Check access size
253            if (req->getSize() != (32/8))
254                return new GeneralProtection(0);
255            */
256            // Force the access to be uncacheable.
257            req->setFlags(Request::UNCACHEABLE);
258            req->setPaddr(x86LocalAPICAddress(tc->contextId(),
259                                              paddr - apicRange.start()));
260        } else if (m5opRange.contains(paddr)) {
261            req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR);
262            req->setPaddr(GenericISA::iprAddressPseudoInst(
263                              (paddr >> 8) & 0xFF,
264                              paddr & 0xFF));
265        }
266    }
267
268    return NoFault;
269}
270
271Fault
272TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
273        Mode mode, bool &delayedResponse, bool timing)
274{
275    uint32_t flags = req->getFlags();
276    int seg = flags & SegmentFlagMask;
277    bool storeCheck = flags & (StoreCheck << FlagShift);
278
279    delayedResponse = false;
280
281    // If this is true, we're dealing with a request to a non-memory address
282    // space.
283    if (seg == SEGMENT_REG_MS) {
284        return translateInt(req, tc);
285    }
286
287    Addr vaddr = req->getVaddr();
288    DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
289
290    HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
291
292    // If protected mode has been enabled...
293    if (m5Reg.prot) {
294        DPRINTF(TLB, "In protected mode.\n");
295        // If we're not in 64-bit mode, do protection/limit checks
296        if (m5Reg.mode != LongMode) {
297            DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
298            // Check for a NULL segment selector.
299            if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR ||
300                        seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS)
301                    && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
302                return std::make_shared<GeneralProtection>(0);
303            bool expandDown = false;
304            SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
305            if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
306                if (!attr.writable && (mode == Write || storeCheck))
307                    return std::make_shared<GeneralProtection>(0);
308                if (!attr.readable && mode == Read)
309                    return std::make_shared<GeneralProtection>(0);
310                expandDown = attr.expandDown;
311
312            }
313            Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
314            Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
315            bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift));
316            unsigned logSize = sizeOverride ? (unsigned)m5Reg.altAddr
317                                            : (unsigned)m5Reg.defAddr;
318            int size = (1 << logSize) * 8;
319            Addr offset = bits(vaddr - base, size - 1, 0);
320            Addr endOffset = offset + req->getSize() - 1;
321            if (expandDown) {
322                DPRINTF(TLB, "Checking an expand down segment.\n");
323                warn_once("Expand down segments are untested.\n");
324                if (offset <= limit || endOffset <= limit)
325                    return std::make_shared<GeneralProtection>(0);
326            } else {
327                if (offset > limit || endOffset > limit)
328                    return std::make_shared<GeneralProtection>(0);
329            }
330        }
331        if (m5Reg.submode != SixtyFourBitMode ||
332                (flags & (AddrSizeFlagBit << FlagShift)))
333            vaddr &= mask(32);
334        // If paging is enabled, do the translation.
335        if (m5Reg.paging) {
336            DPRINTF(TLB, "Paging enabled.\n");
337            // The vaddr already has the segment base applied.
338            TlbEntry *entry = lookup(vaddr);
339            if (!entry) {
340                if (FullSystem) {
341                    Fault fault = walker->start(tc, translation, req, mode);
342                    if (timing || fault != NoFault) {
343                        // This gets ignored in atomic mode.
344                        delayedResponse = true;
345                        return fault;
346                    }
347                    entry = lookup(vaddr);
348                    assert(entry);
349                } else {
350                    DPRINTF(TLB, "Handling a TLB miss for "
351                            "address %#x at pc %#x.\n",
352                            vaddr, tc->instAddr());
353
354                    Process *p = tc->getProcessPtr();
355                    TlbEntry newEntry;
356                    bool success = p->pTable->lookup(vaddr, newEntry);
357                    if (!success && mode != Execute) {
358                        // Check if we just need to grow the stack.
359                        if (p->fixupStackFault(vaddr)) {
360                            // If we did, lookup the entry for the new page.
361                            success = p->pTable->lookup(vaddr, newEntry);
362                        }
363                    }
364                    if (!success) {
365                        return std::make_shared<PageFault>(vaddr, true, mode,
366                                                           true, false);
367                    } else {
368                        Addr alignedVaddr = p->pTable->pageAlign(vaddr);
369                        DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
370                                newEntry.pageStart());
371                        entry = insert(alignedVaddr, newEntry);
372                    }
373                    DPRINTF(TLB, "Miss was serviced.\n");
374                }
375            }
376
377            DPRINTF(TLB, "Entry found with paddr %#x, "
378                    "doing protection checks.\n", entry->paddr);
379            // Do paging protection checks.
380            bool inUser = (m5Reg.cpl == 3 &&
381                    !(flags & (CPL0FlagBit << FlagShift)));
382            CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
383            bool badWrite = (!entry->writable && (inUser || cr0.wp));
384            if ((inUser && !entry->user) || (mode == Write && badWrite)) {
385                // The page must have been present to get into the TLB in
386                // the first place. We'll assume the reserved bits are
387                // fine even though we're not checking them.
388                return std::make_shared<PageFault>(vaddr, true, mode, inUser,
389                                                   false);
390            }
391            if (storeCheck && badWrite) {
392                // This would fault if this were a write, so return a page
393                // fault that reflects that happening.
394                return std::make_shared<PageFault>(vaddr, true, Write, inUser,
395                                                   false);
396            }
397
398            Addr paddr = entry->paddr | (vaddr & mask(entry->logBytes));
399            DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
400            req->setPaddr(paddr);
401            if (entry->uncacheable)
402                req->setFlags(Request::UNCACHEABLE);
403        } else {
404            //Use the address which already has segmentation applied.
405            DPRINTF(TLB, "Paging disabled.\n");
406            DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
407            req->setPaddr(vaddr);
408        }
409    } else {
410        // Real mode
411        DPRINTF(TLB, "In real mode.\n");
412        DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
413        req->setPaddr(vaddr);
414    }
415
416    return finalizePhysical(req, tc, mode);
417}
418
419Fault
420TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
421{
422    bool delayedResponse;
423    return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
424}
425
426void
427TLB::translateTiming(RequestPtr req, ThreadContext *tc,
428        Translation *translation, Mode mode)
429{
430    bool delayedResponse;
431    assert(translation);
432    Fault fault =
433        TLB::translate(req, tc, translation, mode, delayedResponse, true);
434    if (!delayedResponse)
435        translation->finish(fault, req, tc, mode);
436}
437
438Fault
439TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
440{
441    panic("Not implemented\n");
442    return NoFault;
443}
444
445Walker *
446TLB::getWalker()
447{
448    return walker;
449}
450
451void
452TLB::serialize(std::ostream &os)
453{
454    // Only store the entries in use.
455    uint32_t _size = size - freeList.size();
456    SERIALIZE_SCALAR(_size);
457    SERIALIZE_SCALAR(lruSeq);
458
459    uint32_t _count = 0;
460
461    for (uint32_t x = 0; x < size; x++) {
462        if (tlb[x].trieHandle != NULL) {
463            os << "\n[" << csprintf("%s.Entry%d", name(), _count) << "]\n";
464            tlb[x].serialize(os);
465            _count++;
466        }
467    }
468}
469
470void
471TLB::unserialize(Checkpoint *cp, const std::string &section)
472{
473    // Do not allow to restore with a smaller tlb.
474    uint32_t _size;
475    UNSERIALIZE_SCALAR(_size);
476    if (_size > size) {
477        fatal("TLB size less than the one in checkpoint!");
478    }
479
480    UNSERIALIZE_SCALAR(lruSeq);
481
482    for (uint32_t x = 0; x < _size; x++) {
483        TlbEntry *newEntry = freeList.front();
484        freeList.pop_front();
485
486        newEntry->unserialize(cp, csprintf("%s.Entry%d", name(), x));
487        newEntry->trieHandle = trie.insert(newEntry->vaddr,
488            TlbEntryTrie::MaxBits - newEntry->logBytes, newEntry);
489    }
490}
491
492BaseMasterPort *
493TLB::getMasterPort()
494{
495    return &walker->getMasterPort("port");
496}
497
498} // namespace X86ISA
499
500X86ISA::TLB *
501X86TLBParams::create()
502{
503    return new X86ISA::TLB(this);
504}
505