tlb.cc revision 8888
14997Sgblack@eecs.umich.edu/* 25417Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 34997Sgblack@eecs.umich.edu * All rights reserved. 44997Sgblack@eecs.umich.edu * 57087Snate@binkert.org * The license below extends only to copyright in the software and shall 67087Snate@binkert.org * not be construed as granting a license to any other intellectual 77087Snate@binkert.org * property including but not limited to intellectual property relating 87087Snate@binkert.org * to a hardware implementation of the functionality of the software 97087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 107087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 117087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 127087Snate@binkert.org * modified or unmodified, in source code or in binary form. 134997Sgblack@eecs.umich.edu * 147087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 157087Snate@binkert.org * modification, are permitted provided that the following conditions are 167087Snate@binkert.org * met: redistributions of source code must retain the above copyright 177087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 187087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 197087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 207087Snate@binkert.org * documentation and/or other materials provided with the distribution; 217087Snate@binkert.org * neither the name of the copyright holders nor the names of its 224997Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 237087Snate@binkert.org * this software without specific prior written permission. 244997Sgblack@eecs.umich.edu * 254997Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 264997Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 274997Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 284997Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 294997Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 304997Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 314997Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 324997Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 334997Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 344997Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 354997Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 364997Sgblack@eecs.umich.edu * 374997Sgblack@eecs.umich.edu * Authors: Gabe Black 384997Sgblack@eecs.umich.edu */ 394997Sgblack@eecs.umich.edu 404997Sgblack@eecs.umich.edu#include <cstring> 414997Sgblack@eecs.umich.edu 428229Snate@binkert.org#include "arch/x86/insts/microldstop.hh" 438229Snate@binkert.org#include "arch/x86/regs/misc.hh" 448582Sgblack@eecs.umich.edu#include "arch/x86/regs/msr.hh" 456315Sgblack@eecs.umich.edu#include "arch/x86/faults.hh" 465124Sgblack@eecs.umich.edu#include "arch/x86/pagetable.hh" 478752Sgblack@eecs.umich.edu#include "arch/x86/pagetable_walker.hh" 485086Sgblack@eecs.umich.edu#include "arch/x86/tlb.hh" 495149Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh" 505086Sgblack@eecs.umich.edu#include "base/bitfield.hh" 515086Sgblack@eecs.umich.edu#include "base/trace.hh" 528229Snate@binkert.org#include "cpu/base.hh" 535086Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 548232Snate@binkert.org#include "debug/TLB.hh" 555086Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 568767Sgblack@eecs.umich.edu#include "mem/page_table.hh" 575086Sgblack@eecs.umich.edu#include "mem/request.hh" 588767Sgblack@eecs.umich.edu#include "sim/full_system.hh" 595895Sgblack@eecs.umich.edu#include "sim/process.hh" 605086Sgblack@eecs.umich.edu 615086Sgblack@eecs.umich.edunamespace X86ISA { 625086Sgblack@eecs.umich.edu 635358Sgblack@eecs.umich.eduTLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size) 645124Sgblack@eecs.umich.edu{ 655124Sgblack@eecs.umich.edu tlb = new TlbEntry[size]; 665124Sgblack@eecs.umich.edu std::memset(tlb, 0, sizeof(TlbEntry) * size); 675124Sgblack@eecs.umich.edu 685124Sgblack@eecs.umich.edu for (int x = 0; x < size; x++) 695124Sgblack@eecs.umich.edu freeList.push_back(&tlb[x]); 705124Sgblack@eecs.umich.edu 715245Sgblack@eecs.umich.edu walker = p->walker; 725245Sgblack@eecs.umich.edu walker->setTLB(this); 735236Sgblack@eecs.umich.edu} 745236Sgblack@eecs.umich.edu 755895Sgblack@eecs.umich.eduTlbEntry * 765124Sgblack@eecs.umich.eduTLB::insert(Addr vpn, TlbEntry &entry) 775124Sgblack@eecs.umich.edu{ 785124Sgblack@eecs.umich.edu //TODO Deal with conflicting entries 795124Sgblack@eecs.umich.edu 805124Sgblack@eecs.umich.edu TlbEntry *newEntry = NULL; 815124Sgblack@eecs.umich.edu if (!freeList.empty()) { 825124Sgblack@eecs.umich.edu newEntry = freeList.front(); 835124Sgblack@eecs.umich.edu freeList.pop_front(); 845124Sgblack@eecs.umich.edu } else { 855124Sgblack@eecs.umich.edu newEntry = entryList.back(); 865124Sgblack@eecs.umich.edu entryList.pop_back(); 875124Sgblack@eecs.umich.edu } 885124Sgblack@eecs.umich.edu *newEntry = entry; 895124Sgblack@eecs.umich.edu newEntry->vaddr = vpn; 905124Sgblack@eecs.umich.edu entryList.push_front(newEntry); 915895Sgblack@eecs.umich.edu return newEntry; 925124Sgblack@eecs.umich.edu} 935124Sgblack@eecs.umich.edu 945360Sgblack@eecs.umich.eduTLB::EntryList::iterator 955360Sgblack@eecs.umich.eduTLB::lookupIt(Addr va, bool update_lru) 965124Sgblack@eecs.umich.edu{ 975124Sgblack@eecs.umich.edu //TODO make this smarter at some point 985124Sgblack@eecs.umich.edu EntryList::iterator entry; 995124Sgblack@eecs.umich.edu for (entry = entryList.begin(); entry != entryList.end(); entry++) { 1005124Sgblack@eecs.umich.edu if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) { 1015124Sgblack@eecs.umich.edu DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x " 1025124Sgblack@eecs.umich.edu "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size); 1035124Sgblack@eecs.umich.edu if (update_lru) { 1045360Sgblack@eecs.umich.edu entryList.push_front(*entry); 1055124Sgblack@eecs.umich.edu entryList.erase(entry); 1065360Sgblack@eecs.umich.edu entry = entryList.begin(); 1075124Sgblack@eecs.umich.edu } 1085360Sgblack@eecs.umich.edu break; 1095124Sgblack@eecs.umich.edu } 1105124Sgblack@eecs.umich.edu } 1115360Sgblack@eecs.umich.edu return entry; 1125360Sgblack@eecs.umich.edu} 1135360Sgblack@eecs.umich.edu 1145360Sgblack@eecs.umich.eduTlbEntry * 1155360Sgblack@eecs.umich.eduTLB::lookup(Addr va, bool update_lru) 1165360Sgblack@eecs.umich.edu{ 1175360Sgblack@eecs.umich.edu EntryList::iterator entry = lookupIt(va, update_lru); 1185360Sgblack@eecs.umich.edu if (entry == entryList.end()) 1195360Sgblack@eecs.umich.edu return NULL; 1205360Sgblack@eecs.umich.edu else 1215360Sgblack@eecs.umich.edu return *entry; 1225124Sgblack@eecs.umich.edu} 1235124Sgblack@eecs.umich.edu 1245124Sgblack@eecs.umich.eduvoid 1255124Sgblack@eecs.umich.eduTLB::invalidateAll() 1265124Sgblack@eecs.umich.edu{ 1275242Sgblack@eecs.umich.edu DPRINTF(TLB, "Invalidating all entries.\n"); 1285242Sgblack@eecs.umich.edu while (!entryList.empty()) { 1295242Sgblack@eecs.umich.edu TlbEntry *entry = entryList.front(); 1305242Sgblack@eecs.umich.edu entryList.pop_front(); 1315242Sgblack@eecs.umich.edu freeList.push_back(entry); 1325242Sgblack@eecs.umich.edu } 1335124Sgblack@eecs.umich.edu} 1345124Sgblack@eecs.umich.edu 1355124Sgblack@eecs.umich.eduvoid 1365357Sgblack@eecs.umich.eduTLB::setConfigAddress(uint32_t addr) 1375357Sgblack@eecs.umich.edu{ 1385357Sgblack@eecs.umich.edu configAddress = addr; 1395357Sgblack@eecs.umich.edu} 1405357Sgblack@eecs.umich.edu 1415357Sgblack@eecs.umich.eduvoid 1425124Sgblack@eecs.umich.eduTLB::invalidateNonGlobal() 1435124Sgblack@eecs.umich.edu{ 1445242Sgblack@eecs.umich.edu DPRINTF(TLB, "Invalidating all non global entries.\n"); 1455242Sgblack@eecs.umich.edu EntryList::iterator entryIt; 1465242Sgblack@eecs.umich.edu for (entryIt = entryList.begin(); entryIt != entryList.end();) { 1475242Sgblack@eecs.umich.edu if (!(*entryIt)->global) { 1485242Sgblack@eecs.umich.edu freeList.push_back(*entryIt); 1495242Sgblack@eecs.umich.edu entryList.erase(entryIt++); 1505242Sgblack@eecs.umich.edu } else { 1515242Sgblack@eecs.umich.edu entryIt++; 1525242Sgblack@eecs.umich.edu } 1535242Sgblack@eecs.umich.edu } 1545124Sgblack@eecs.umich.edu} 1555124Sgblack@eecs.umich.edu 1565124Sgblack@eecs.umich.eduvoid 1575358Sgblack@eecs.umich.eduTLB::demapPage(Addr va, uint64_t asn) 1585086Sgblack@eecs.umich.edu{ 1595359Sgblack@eecs.umich.edu EntryList::iterator entry = lookupIt(va, false); 1605359Sgblack@eecs.umich.edu if (entry != entryList.end()) { 1615359Sgblack@eecs.umich.edu freeList.push_back(*entry); 1625359Sgblack@eecs.umich.edu entryList.erase(entry); 1635359Sgblack@eecs.umich.edu } 1645086Sgblack@eecs.umich.edu} 1655086Sgblack@eecs.umich.edu 1665086Sgblack@eecs.umich.eduFault 1676141Sgblack@eecs.umich.eduTLB::translateInt(RequestPtr req, ThreadContext *tc) 1686141Sgblack@eecs.umich.edu{ 1696141Sgblack@eecs.umich.edu DPRINTF(TLB, "Addresses references internal memory.\n"); 1706141Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr(); 1716141Sgblack@eecs.umich.edu Addr prefix = (vaddr >> 3) & IntAddrPrefixMask; 1726141Sgblack@eecs.umich.edu if (prefix == IntAddrPrefixCPUID) { 1736141Sgblack@eecs.umich.edu panic("CPUID memory space not yet implemented!\n"); 1746141Sgblack@eecs.umich.edu } else if (prefix == IntAddrPrefixMSR) { 1758582Sgblack@eecs.umich.edu vaddr = (vaddr >> 3) & ~IntAddrPrefixMask; 1768105Sgblack@eecs.umich.edu req->setFlags(Request::MMAPPED_IPR); 1778582Sgblack@eecs.umich.edu 1788582Sgblack@eecs.umich.edu MiscRegIndex regNum; 1798582Sgblack@eecs.umich.edu if (!msrAddrToIndex(regNum, vaddr)) 1806141Sgblack@eecs.umich.edu return new GeneralProtection(0); 1818582Sgblack@eecs.umich.edu 1826141Sgblack@eecs.umich.edu //The index is multiplied by the size of a MiscReg so that 1836141Sgblack@eecs.umich.edu //any memory dependence calculations will not see these as 1846141Sgblack@eecs.umich.edu //overlapping. 1858582Sgblack@eecs.umich.edu req->setPaddr((Addr)regNum * sizeof(MiscReg)); 1866141Sgblack@eecs.umich.edu return NoFault; 1876141Sgblack@eecs.umich.edu } else if (prefix == IntAddrPrefixIO) { 1886141Sgblack@eecs.umich.edu // TODO If CPL > IOPL or in virtual mode, check the I/O permission 1896141Sgblack@eecs.umich.edu // bitmap in the TSS. 1906141Sgblack@eecs.umich.edu 1916141Sgblack@eecs.umich.edu Addr IOPort = vaddr & ~IntAddrPrefixMask; 1926141Sgblack@eecs.umich.edu // Make sure the address fits in the expected 16 bit IO address 1936141Sgblack@eecs.umich.edu // space. 1946141Sgblack@eecs.umich.edu assert(!(IOPort & ~0xFFFF)); 1956141Sgblack@eecs.umich.edu if (IOPort == 0xCF8 && req->getSize() == 4) { 1968105Sgblack@eecs.umich.edu req->setFlags(Request::MMAPPED_IPR); 1976141Sgblack@eecs.umich.edu req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg)); 1986141Sgblack@eecs.umich.edu } else if ((IOPort & ~mask(2)) == 0xCFC) { 1997774Sgblack@eecs.umich.edu req->setFlags(Request::UNCACHEABLE); 2006141Sgblack@eecs.umich.edu Addr configAddress = 2016141Sgblack@eecs.umich.edu tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS); 2026141Sgblack@eecs.umich.edu if (bits(configAddress, 31, 31)) { 2036141Sgblack@eecs.umich.edu req->setPaddr(PhysAddrPrefixPciConfig | 2046141Sgblack@eecs.umich.edu mbits(configAddress, 30, 2) | 2056141Sgblack@eecs.umich.edu (IOPort & mask(2))); 2068098Sgblack@eecs.umich.edu } else { 2078098Sgblack@eecs.umich.edu req->setPaddr(PhysAddrPrefixIO | IOPort); 2086141Sgblack@eecs.umich.edu } 2096141Sgblack@eecs.umich.edu } else { 2107774Sgblack@eecs.umich.edu req->setFlags(Request::UNCACHEABLE); 2116141Sgblack@eecs.umich.edu req->setPaddr(PhysAddrPrefixIO | IOPort); 2126141Sgblack@eecs.umich.edu } 2136141Sgblack@eecs.umich.edu return NoFault; 2146141Sgblack@eecs.umich.edu } else { 2156141Sgblack@eecs.umich.edu panic("Access to unrecognized internal address space %#x.\n", 2166141Sgblack@eecs.umich.edu prefix); 2176141Sgblack@eecs.umich.edu } 2186141Sgblack@eecs.umich.edu} 2196141Sgblack@eecs.umich.edu 2206141Sgblack@eecs.umich.eduFault 2216023Snate@binkert.orgTLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation, 2226023Snate@binkert.org Mode mode, bool &delayedResponse, bool timing) 2235086Sgblack@eecs.umich.edu{ 2246141Sgblack@eecs.umich.edu uint32_t flags = req->getFlags(); 2256141Sgblack@eecs.umich.edu int seg = flags & SegmentFlagMask; 2266141Sgblack@eecs.umich.edu bool storeCheck = flags & (StoreCheck << FlagShift); 2276141Sgblack@eecs.umich.edu 2288535Sgblack@eecs.umich.edu delayedResponse = false; 2298535Sgblack@eecs.umich.edu 2306141Sgblack@eecs.umich.edu // If this is true, we're dealing with a request to a non-memory address 2316141Sgblack@eecs.umich.edu // space. 2326141Sgblack@eecs.umich.edu if (seg == SEGMENT_REG_MS) { 2336141Sgblack@eecs.umich.edu return translateInt(req, tc); 2346141Sgblack@eecs.umich.edu } 2356141Sgblack@eecs.umich.edu 2365124Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr(); 2375140Sgblack@eecs.umich.edu DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr); 2385140Sgblack@eecs.umich.edu 2396141Sgblack@eecs.umich.edu HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); 2405140Sgblack@eecs.umich.edu 2415140Sgblack@eecs.umich.edu // If protected mode has been enabled... 2426141Sgblack@eecs.umich.edu if (m5Reg.prot) { 2435237Sgblack@eecs.umich.edu DPRINTF(TLB, "In protected mode.\n"); 2445140Sgblack@eecs.umich.edu // If we're not in 64-bit mode, do protection/limit checks 2456141Sgblack@eecs.umich.edu if (m5Reg.mode != LongMode) { 2465237Sgblack@eecs.umich.edu DPRINTF(TLB, "Not in long mode. Checking segment protection.\n"); 2475431Sgblack@eecs.umich.edu // Check for a NULL segment selector. 2486059Sgblack@eecs.umich.edu if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR || 2496141Sgblack@eecs.umich.edu seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS) 2506059Sgblack@eecs.umich.edu && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg))) 2515431Sgblack@eecs.umich.edu return new GeneralProtection(0); 2525433Sgblack@eecs.umich.edu bool expandDown = false; 2535965Sgblack@eecs.umich.edu SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg)); 2545433Sgblack@eecs.umich.edu if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) { 2556099Sgblack@eecs.umich.edu if (!attr.writable && (mode == Write || storeCheck)) 2565433Sgblack@eecs.umich.edu return new GeneralProtection(0); 2576023Snate@binkert.org if (!attr.readable && mode == Read) 2585433Sgblack@eecs.umich.edu return new GeneralProtection(0); 2595433Sgblack@eecs.umich.edu expandDown = attr.expandDown; 2605965Sgblack@eecs.umich.edu 2615433Sgblack@eecs.umich.edu } 2625140Sgblack@eecs.umich.edu Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg)); 2635140Sgblack@eecs.umich.edu Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg)); 2645965Sgblack@eecs.umich.edu // This assumes we're not in 64 bit mode. If we were, the default 2655965Sgblack@eecs.umich.edu // address size is 64 bits, overridable to 32. 2665965Sgblack@eecs.umich.edu int size = 32; 2675965Sgblack@eecs.umich.edu bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift)); 2686141Sgblack@eecs.umich.edu SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR); 2695980Snate@binkert.org if ((csAttr.defaultSize && sizeOverride) || 2705980Snate@binkert.org (!csAttr.defaultSize && !sizeOverride)) 2715965Sgblack@eecs.umich.edu size = 16; 2725965Sgblack@eecs.umich.edu Addr offset = bits(vaddr - base, size-1, 0); 2735965Sgblack@eecs.umich.edu Addr endOffset = offset + req->getSize() - 1; 2745433Sgblack@eecs.umich.edu if (expandDown) { 2755237Sgblack@eecs.umich.edu DPRINTF(TLB, "Checking an expand down segment.\n"); 2765965Sgblack@eecs.umich.edu warn_once("Expand down segments are untested.\n"); 2775965Sgblack@eecs.umich.edu if (offset <= limit || endOffset <= limit) 2785965Sgblack@eecs.umich.edu return new GeneralProtection(0); 2795140Sgblack@eecs.umich.edu } else { 2805965Sgblack@eecs.umich.edu if (offset > limit || endOffset > limit) 2815965Sgblack@eecs.umich.edu return new GeneralProtection(0); 2825140Sgblack@eecs.umich.edu } 2835140Sgblack@eecs.umich.edu } 2845140Sgblack@eecs.umich.edu // If paging is enabled, do the translation. 2856141Sgblack@eecs.umich.edu if (m5Reg.paging) { 2865237Sgblack@eecs.umich.edu DPRINTF(TLB, "Paging enabled.\n"); 2875140Sgblack@eecs.umich.edu // The vaddr already has the segment base applied. 2885140Sgblack@eecs.umich.edu TlbEntry *entry = lookup(vaddr); 2895140Sgblack@eecs.umich.edu if (!entry) { 2908752Sgblack@eecs.umich.edu if (FullSystem) { 2918752Sgblack@eecs.umich.edu Fault fault = walker->start(tc, translation, req, mode); 2928752Sgblack@eecs.umich.edu if (timing || fault != NoFault) { 2938752Sgblack@eecs.umich.edu // This gets ignored in atomic mode. 2948752Sgblack@eecs.umich.edu delayedResponse = true; 2958752Sgblack@eecs.umich.edu return fault; 2968752Sgblack@eecs.umich.edu } 2978752Sgblack@eecs.umich.edu entry = lookup(vaddr); 2988752Sgblack@eecs.umich.edu assert(entry); 2998752Sgblack@eecs.umich.edu } else { 3008752Sgblack@eecs.umich.edu DPRINTF(TLB, "Handling a TLB miss for " 3018752Sgblack@eecs.umich.edu "address %#x at pc %#x.\n", 3028752Sgblack@eecs.umich.edu vaddr, tc->instAddr()); 3038752Sgblack@eecs.umich.edu 3048752Sgblack@eecs.umich.edu Process *p = tc->getProcessPtr(); 3058752Sgblack@eecs.umich.edu TlbEntry newEntry; 3068752Sgblack@eecs.umich.edu bool success = p->pTable->lookup(vaddr, newEntry); 3078752Sgblack@eecs.umich.edu if (!success && mode != Execute) { 3088752Sgblack@eecs.umich.edu // Check if we just need to grow the stack. 3098752Sgblack@eecs.umich.edu if (p->fixupStackFault(vaddr)) { 3108752Sgblack@eecs.umich.edu // If we did, lookup the entry for the new page. 3118752Sgblack@eecs.umich.edu success = p->pTable->lookup(vaddr, newEntry); 3128752Sgblack@eecs.umich.edu } 3138752Sgblack@eecs.umich.edu } 3148752Sgblack@eecs.umich.edu if (!success) { 3158752Sgblack@eecs.umich.edu return new PageFault(vaddr, true, mode, true, false); 3168752Sgblack@eecs.umich.edu } else { 3178752Sgblack@eecs.umich.edu Addr alignedVaddr = p->pTable->pageAlign(vaddr); 3188752Sgblack@eecs.umich.edu DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, 3198752Sgblack@eecs.umich.edu newEntry.pageStart()); 3208752Sgblack@eecs.umich.edu entry = insert(alignedVaddr, newEntry); 3218752Sgblack@eecs.umich.edu } 3228752Sgblack@eecs.umich.edu DPRINTF(TLB, "Miss was serviced.\n"); 3235895Sgblack@eecs.umich.edu } 3245140Sgblack@eecs.umich.edu } 3258646Snilay@cs.wisc.edu 3268646Snilay@cs.wisc.edu DPRINTF(TLB, "Entry found with paddr %#x, " 3278646Snilay@cs.wisc.edu "doing protection checks.\n", entry->paddr); 3285895Sgblack@eecs.umich.edu // Do paging protection checks. 3296141Sgblack@eecs.umich.edu bool inUser = (m5Reg.cpl == 3 && 3305917Sgblack@eecs.umich.edu !(flags & (CPL0FlagBit << FlagShift))); 3317933Stharris@microsoft.com CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 3327933Stharris@microsoft.com bool badWrite = (!entry->writable && (inUser || cr0.wp)); 3337933Stharris@microsoft.com if ((inUser && !entry->user) || (mode == Write && badWrite)) { 3345917Sgblack@eecs.umich.edu // The page must have been present to get into the TLB in 3355917Sgblack@eecs.umich.edu // the first place. We'll assume the reserved bits are 3365917Sgblack@eecs.umich.edu // fine even though we're not checking them. 3376023Snate@binkert.org return new PageFault(vaddr, true, mode, inUser, false); 3385917Sgblack@eecs.umich.edu } 3397933Stharris@microsoft.com if (storeCheck && badWrite) { 3406099Sgblack@eecs.umich.edu // This would fault if this were a write, so return a page 3416099Sgblack@eecs.umich.edu // fault that reflects that happening. 3426099Sgblack@eecs.umich.edu return new PageFault(vaddr, true, Write, inUser, false); 3436099Sgblack@eecs.umich.edu } 3445917Sgblack@eecs.umich.edu 3455895Sgblack@eecs.umich.edu Addr paddr = entry->paddr | (vaddr & (entry->size-1)); 3465895Sgblack@eecs.umich.edu DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr); 3475895Sgblack@eecs.umich.edu req->setPaddr(paddr); 3487775Sgblack@eecs.umich.edu if (entry->uncacheable) 3497775Sgblack@eecs.umich.edu req->setFlags(Request::UNCACHEABLE); 3505140Sgblack@eecs.umich.edu } else { 3515140Sgblack@eecs.umich.edu //Use the address which already has segmentation applied. 3525237Sgblack@eecs.umich.edu DPRINTF(TLB, "Paging disabled.\n"); 3535237Sgblack@eecs.umich.edu DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 3545140Sgblack@eecs.umich.edu req->setPaddr(vaddr); 3555140Sgblack@eecs.umich.edu } 3565124Sgblack@eecs.umich.edu } else { 3575140Sgblack@eecs.umich.edu // Real mode 3585237Sgblack@eecs.umich.edu DPRINTF(TLB, "In real mode.\n"); 3595237Sgblack@eecs.umich.edu DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 3605140Sgblack@eecs.umich.edu req->setPaddr(vaddr); 3615124Sgblack@eecs.umich.edu } 3625360Sgblack@eecs.umich.edu // Check for an access to the local APIC 3638767Sgblack@eecs.umich.edu if (FullSystem) { 3648767Sgblack@eecs.umich.edu LocalApicBase localApicBase = 3658767Sgblack@eecs.umich.edu tc->readMiscRegNoEffect(MISCREG_APIC_BASE); 3668767Sgblack@eecs.umich.edu Addr baseAddr = localApicBase.base * PageBytes; 3678767Sgblack@eecs.umich.edu Addr paddr = req->getPaddr(); 3688767Sgblack@eecs.umich.edu if (baseAddr <= paddr && baseAddr + PageBytes > paddr) { 3698767Sgblack@eecs.umich.edu // The Intel developer's manuals say the below restrictions apply, 3708767Sgblack@eecs.umich.edu // but the linux kernel, because of a compiler optimization, breaks 3718767Sgblack@eecs.umich.edu // them. 3728767Sgblack@eecs.umich.edu /* 3738767Sgblack@eecs.umich.edu // Check alignment 3748767Sgblack@eecs.umich.edu if (paddr & ((32/8) - 1)) 3758767Sgblack@eecs.umich.edu return new GeneralProtection(0); 3768767Sgblack@eecs.umich.edu // Check access size 3778767Sgblack@eecs.umich.edu if (req->getSize() != (32/8)) 3788767Sgblack@eecs.umich.edu return new GeneralProtection(0); 3798767Sgblack@eecs.umich.edu */ 3808767Sgblack@eecs.umich.edu // Force the access to be uncacheable. 3818767Sgblack@eecs.umich.edu req->setFlags(Request::UNCACHEABLE); 3828767Sgblack@eecs.umich.edu req->setPaddr(x86LocalAPICAddress(tc->contextId(), 3838767Sgblack@eecs.umich.edu paddr - baseAddr)); 3848767Sgblack@eecs.umich.edu } 3855360Sgblack@eecs.umich.edu } 3865086Sgblack@eecs.umich.edu return NoFault; 3875086Sgblack@eecs.umich.edu}; 3885086Sgblack@eecs.umich.edu 3895140Sgblack@eecs.umich.eduFault 3906023Snate@binkert.orgTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 3915140Sgblack@eecs.umich.edu{ 3925895Sgblack@eecs.umich.edu bool delayedResponse; 3936023Snate@binkert.org return TLB::translate(req, tc, NULL, mode, delayedResponse, false); 3945140Sgblack@eecs.umich.edu} 3955140Sgblack@eecs.umich.edu 3965894Sgblack@eecs.umich.eduvoid 3976022Sgblack@eecs.umich.eduTLB::translateTiming(RequestPtr req, ThreadContext *tc, 3986023Snate@binkert.org Translation *translation, Mode mode) 3995894Sgblack@eecs.umich.edu{ 4005895Sgblack@eecs.umich.edu bool delayedResponse; 4015894Sgblack@eecs.umich.edu assert(translation); 4026023Snate@binkert.org Fault fault = 4036023Snate@binkert.org TLB::translate(req, tc, translation, mode, delayedResponse, true); 4045895Sgblack@eecs.umich.edu if (!delayedResponse) 4056023Snate@binkert.org translation->finish(fault, req, tc, mode); 4065894Sgblack@eecs.umich.edu} 4075894Sgblack@eecs.umich.edu 4088888Sgeoffrey.blake@arm.comFault 4098888Sgeoffrey.blake@arm.comTLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) 4108888Sgeoffrey.blake@arm.com{ 4118888Sgeoffrey.blake@arm.com panic("Not implemented\n"); 4128888Sgeoffrey.blake@arm.com return NoFault; 4138888Sgeoffrey.blake@arm.com} 4148888Sgeoffrey.blake@arm.com 4157912Shestness@cs.utexas.eduWalker * 4167912Shestness@cs.utexas.eduTLB::getWalker() 4177912Shestness@cs.utexas.edu{ 4187912Shestness@cs.utexas.edu return walker; 4197912Shestness@cs.utexas.edu} 4207912Shestness@cs.utexas.edu 4215086Sgblack@eecs.umich.eduvoid 4225086Sgblack@eecs.umich.eduTLB::serialize(std::ostream &os) 4235086Sgblack@eecs.umich.edu{ 4245086Sgblack@eecs.umich.edu} 4255086Sgblack@eecs.umich.edu 4265086Sgblack@eecs.umich.eduvoid 4275086Sgblack@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 4285086Sgblack@eecs.umich.edu{ 4295086Sgblack@eecs.umich.edu} 4305086Sgblack@eecs.umich.edu 4318864Snilay@cs.wisc.eduPort * 4328864Snilay@cs.wisc.eduTLB::getPort() 4338864Snilay@cs.wisc.edu{ 4348864Snilay@cs.wisc.edu return walker->getPort("port"); 4358864Snilay@cs.wisc.edu} 4368864Snilay@cs.wisc.edu 4377811Ssteve.reinhardt@amd.com} // namespace X86ISA 4385086Sgblack@eecs.umich.edu 4396022Sgblack@eecs.umich.eduX86ISA::TLB * 4406022Sgblack@eecs.umich.eduX86TLBParams::create() 4414997Sgblack@eecs.umich.edu{ 4426022Sgblack@eecs.umich.edu return new X86ISA::TLB(this); 4434997Sgblack@eecs.umich.edu} 444