tlb.cc revision 8535 
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include <cstring>
41
42#include "arch/x86/insts/microldstop.hh"
43#include "arch/x86/regs/misc.hh"
44#include "arch/x86/faults.hh"
45#include "arch/x86/pagetable.hh"
46#include "arch/x86/tlb.hh"
47#include "arch/x86/x86_traits.hh"
48#include "base/bitfield.hh"
49#include "base/trace.hh"
50#include "config/full_system.hh"
51#include "cpu/base.hh"
52#include "cpu/thread_context.hh"
53#include "debug/TLB.hh"
54#include "mem/packet_access.hh"
55#include "mem/request.hh"
56
57#if FULL_SYSTEM
58#include "arch/x86/pagetable_walker.hh"
59#else
60#include "mem/page_table.hh"
61#include "sim/process.hh"
62#endif
63
64namespace X86ISA {
65
66TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
67{
68    tlb = new TlbEntry[size];
69    std::memset(tlb, 0, sizeof(TlbEntry) * size);
70
71    for (int x = 0; x < size; x++)
72        freeList.push_back(&tlb[x]);
73
74#if FULL_SYSTEM
75    walker = p->walker;
76    walker->setTLB(this);
77#endif
78}
79
80TlbEntry *
81TLB::insert(Addr vpn, TlbEntry &entry)
82{
83    //TODO Deal with conflicting entries
84
85    TlbEntry *newEntry = NULL;
86    if (!freeList.empty()) {
87        newEntry = freeList.front();
88        freeList.pop_front();
89    } else {
90        newEntry = entryList.back();
91        entryList.pop_back();
92    }
93    *newEntry = entry;
94    newEntry->vaddr = vpn;
95    entryList.push_front(newEntry);
96    return newEntry;
97}
98
99TLB::EntryList::iterator
100TLB::lookupIt(Addr va, bool update_lru)
101{
102    //TODO make this smarter at some point
103    EntryList::iterator entry;
104    for (entry = entryList.begin(); entry != entryList.end(); entry++) {
105        if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) {
106            DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x "
107                    "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size);
108            if (update_lru) {
109                entryList.push_front(*entry);
110                entryList.erase(entry);
111                entry = entryList.begin();
112            }
113            break;
114        }
115    }
116    return entry;
117}
118
119TlbEntry *
120TLB::lookup(Addr va, bool update_lru)
121{
122    EntryList::iterator entry = lookupIt(va, update_lru);
123    if (entry == entryList.end())
124        return NULL;
125    else
126        return *entry;
127}
128
129void
130TLB::invalidateAll()
131{
132    DPRINTF(TLB, "Invalidating all entries.\n");
133    while (!entryList.empty()) {
134        TlbEntry *entry = entryList.front();
135        entryList.pop_front();
136        freeList.push_back(entry);
137    }
138}
139
140void
141TLB::setConfigAddress(uint32_t addr)
142{
143    configAddress = addr;
144}
145
146void
147TLB::invalidateNonGlobal()
148{
149    DPRINTF(TLB, "Invalidating all non global entries.\n");
150    EntryList::iterator entryIt;
151    for (entryIt = entryList.begin(); entryIt != entryList.end();) {
152        if (!(*entryIt)->global) {
153            freeList.push_back(*entryIt);
154            entryList.erase(entryIt++);
155        } else {
156            entryIt++;
157        }
158    }
159}
160
161void
162TLB::demapPage(Addr va, uint64_t asn)
163{
164    EntryList::iterator entry = lookupIt(va, false);
165    if (entry != entryList.end()) {
166        freeList.push_back(*entry);
167        entryList.erase(entry);
168    }
169}
170
171Fault
172TLB::translateInt(RequestPtr req, ThreadContext *tc)
173{
174    DPRINTF(TLB, "Addresses references internal memory.\n");
175    Addr vaddr = req->getVaddr();
176    Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
177    if (prefix == IntAddrPrefixCPUID) {
178        panic("CPUID memory space not yet implemented!\n");
179    } else if (prefix == IntAddrPrefixMSR) {
180        vaddr = vaddr >> 3;
181        req->setFlags(Request::MMAPPED_IPR);
182        Addr regNum = 0;
183        switch (vaddr & ~IntAddrPrefixMask) {
184          case 0x10:
185            regNum = MISCREG_TSC;
186            break;
187          case 0x1B:
188            regNum = MISCREG_APIC_BASE;
189            break;
190          case 0xFE:
191            regNum = MISCREG_MTRRCAP;
192            break;
193          case 0x174:
194            regNum = MISCREG_SYSENTER_CS;
195            break;
196          case 0x175:
197            regNum = MISCREG_SYSENTER_ESP;
198            break;
199          case 0x176:
200            regNum = MISCREG_SYSENTER_EIP;
201            break;
202          case 0x179:
203            regNum = MISCREG_MCG_CAP;
204            break;
205          case 0x17A:
206            regNum = MISCREG_MCG_STATUS;
207            break;
208          case 0x17B:
209            regNum = MISCREG_MCG_CTL;
210            break;
211          case 0x1D9:
212            regNum = MISCREG_DEBUG_CTL_MSR;
213            break;
214          case 0x1DB:
215            regNum = MISCREG_LAST_BRANCH_FROM_IP;
216            break;
217          case 0x1DC:
218            regNum = MISCREG_LAST_BRANCH_TO_IP;
219            break;
220          case 0x1DD:
221            regNum = MISCREG_LAST_EXCEPTION_FROM_IP;
222            break;
223          case 0x1DE:
224            regNum = MISCREG_LAST_EXCEPTION_TO_IP;
225            break;
226          case 0x200:
227            regNum = MISCREG_MTRR_PHYS_BASE_0;
228            break;
229          case 0x201:
230            regNum = MISCREG_MTRR_PHYS_MASK_0;
231            break;
232          case 0x202:
233            regNum = MISCREG_MTRR_PHYS_BASE_1;
234            break;
235          case 0x203:
236            regNum = MISCREG_MTRR_PHYS_MASK_1;
237            break;
238          case 0x204:
239            regNum = MISCREG_MTRR_PHYS_BASE_2;
240            break;
241          case 0x205:
242            regNum = MISCREG_MTRR_PHYS_MASK_2;
243            break;
244          case 0x206:
245            regNum = MISCREG_MTRR_PHYS_BASE_3;
246            break;
247          case 0x207:
248            regNum = MISCREG_MTRR_PHYS_MASK_3;
249            break;
250          case 0x208:
251            regNum = MISCREG_MTRR_PHYS_BASE_4;
252            break;
253          case 0x209:
254            regNum = MISCREG_MTRR_PHYS_MASK_4;
255            break;
256          case 0x20A:
257            regNum = MISCREG_MTRR_PHYS_BASE_5;
258            break;
259          case 0x20B:
260            regNum = MISCREG_MTRR_PHYS_MASK_5;
261            break;
262          case 0x20C:
263            regNum = MISCREG_MTRR_PHYS_BASE_6;
264            break;
265          case 0x20D:
266            regNum = MISCREG_MTRR_PHYS_MASK_6;
267            break;
268          case 0x20E:
269            regNum = MISCREG_MTRR_PHYS_BASE_7;
270            break;
271          case 0x20F:
272            regNum = MISCREG_MTRR_PHYS_MASK_7;
273            break;
274          case 0x250:
275            regNum = MISCREG_MTRR_FIX_64K_00000;
276            break;
277          case 0x258:
278            regNum = MISCREG_MTRR_FIX_16K_80000;
279            break;
280          case 0x259:
281            regNum = MISCREG_MTRR_FIX_16K_A0000;
282            break;
283          case 0x268:
284            regNum = MISCREG_MTRR_FIX_4K_C0000;
285            break;
286          case 0x269:
287            regNum = MISCREG_MTRR_FIX_4K_C8000;
288            break;
289          case 0x26A:
290            regNum = MISCREG_MTRR_FIX_4K_D0000;
291            break;
292          case 0x26B:
293            regNum = MISCREG_MTRR_FIX_4K_D8000;
294            break;
295          case 0x26C:
296            regNum = MISCREG_MTRR_FIX_4K_E0000;
297            break;
298          case 0x26D:
299            regNum = MISCREG_MTRR_FIX_4K_E8000;
300            break;
301          case 0x26E:
302            regNum = MISCREG_MTRR_FIX_4K_F0000;
303            break;
304          case 0x26F:
305            regNum = MISCREG_MTRR_FIX_4K_F8000;
306            break;
307          case 0x277:
308            regNum = MISCREG_PAT;
309            break;
310          case 0x2FF:
311            regNum = MISCREG_DEF_TYPE;
312            break;
313          case 0x400:
314            regNum = MISCREG_MC0_CTL;
315            break;
316          case 0x404:
317            regNum = MISCREG_MC1_CTL;
318            break;
319          case 0x408:
320            regNum = MISCREG_MC2_CTL;
321            break;
322          case 0x40C:
323            regNum = MISCREG_MC3_CTL;
324            break;
325          case 0x410:
326            regNum = MISCREG_MC4_CTL;
327            break;
328          case 0x414:
329            regNum = MISCREG_MC5_CTL;
330            break;
331          case 0x418:
332            regNum = MISCREG_MC6_CTL;
333            break;
334          case 0x41C:
335            regNum = MISCREG_MC7_CTL;
336            break;
337          case 0x401:
338            regNum = MISCREG_MC0_STATUS;
339            break;
340          case 0x405:
341            regNum = MISCREG_MC1_STATUS;
342            break;
343          case 0x409:
344            regNum = MISCREG_MC2_STATUS;
345            break;
346          case 0x40D:
347            regNum = MISCREG_MC3_STATUS;
348            break;
349          case 0x411:
350            regNum = MISCREG_MC4_STATUS;
351            break;
352          case 0x415:
353            regNum = MISCREG_MC5_STATUS;
354            break;
355          case 0x419:
356            regNum = MISCREG_MC6_STATUS;
357            break;
358          case 0x41D:
359            regNum = MISCREG_MC7_STATUS;
360            break;
361          case 0x402:
362            regNum = MISCREG_MC0_ADDR;
363            break;
364          case 0x406:
365            regNum = MISCREG_MC1_ADDR;
366            break;
367          case 0x40A:
368            regNum = MISCREG_MC2_ADDR;
369            break;
370          case 0x40E:
371            regNum = MISCREG_MC3_ADDR;
372            break;
373          case 0x412:
374            regNum = MISCREG_MC4_ADDR;
375            break;
376          case 0x416:
377            regNum = MISCREG_MC5_ADDR;
378            break;
379          case 0x41A:
380            regNum = MISCREG_MC6_ADDR;
381            break;
382          case 0x41E:
383            regNum = MISCREG_MC7_ADDR;
384            break;
385          case 0x403:
386            regNum = MISCREG_MC0_MISC;
387            break;
388          case 0x407:
389            regNum = MISCREG_MC1_MISC;
390            break;
391          case 0x40B:
392            regNum = MISCREG_MC2_MISC;
393            break;
394          case 0x40F:
395            regNum = MISCREG_MC3_MISC;
396            break;
397          case 0x413:
398            regNum = MISCREG_MC4_MISC;
399            break;
400          case 0x417:
401            regNum = MISCREG_MC5_MISC;
402            break;
403          case 0x41B:
404            regNum = MISCREG_MC6_MISC;
405            break;
406          case 0x41F:
407            regNum = MISCREG_MC7_MISC;
408            break;
409          case 0xC0000080:
410            regNum = MISCREG_EFER;
411            break;
412          case 0xC0000081:
413            regNum = MISCREG_STAR;
414            break;
415          case 0xC0000082:
416            regNum = MISCREG_LSTAR;
417            break;
418          case 0xC0000083:
419            regNum = MISCREG_CSTAR;
420            break;
421          case 0xC0000084:
422            regNum = MISCREG_SF_MASK;
423            break;
424          case 0xC0000100:
425            regNum = MISCREG_FS_BASE;
426            break;
427          case 0xC0000101:
428            regNum = MISCREG_GS_BASE;
429            break;
430          case 0xC0000102:
431            regNum = MISCREG_KERNEL_GS_BASE;
432            break;
433          case 0xC0000103:
434            regNum = MISCREG_TSC_AUX;
435            break;
436          case 0xC0010000:
437            regNum = MISCREG_PERF_EVT_SEL0;
438            break;
439          case 0xC0010001:
440            regNum = MISCREG_PERF_EVT_SEL1;
441            break;
442          case 0xC0010002:
443            regNum = MISCREG_PERF_EVT_SEL2;
444            break;
445          case 0xC0010003:
446            regNum = MISCREG_PERF_EVT_SEL3;
447            break;
448          case 0xC0010004:
449            regNum = MISCREG_PERF_EVT_CTR0;
450            break;
451          case 0xC0010005:
452            regNum = MISCREG_PERF_EVT_CTR1;
453            break;
454          case 0xC0010006:
455            regNum = MISCREG_PERF_EVT_CTR2;
456            break;
457          case 0xC0010007:
458            regNum = MISCREG_PERF_EVT_CTR3;
459            break;
460          case 0xC0010010:
461            regNum = MISCREG_SYSCFG;
462            break;
463          case 0xC0010016:
464            regNum = MISCREG_IORR_BASE0;
465            break;
466          case 0xC0010017:
467            regNum = MISCREG_IORR_BASE1;
468            break;
469          case 0xC0010018:
470            regNum = MISCREG_IORR_MASK0;
471            break;
472          case 0xC0010019:
473            regNum = MISCREG_IORR_MASK1;
474            break;
475          case 0xC001001A:
476            regNum = MISCREG_TOP_MEM;
477            break;
478          case 0xC001001D:
479            regNum = MISCREG_TOP_MEM2;
480            break;
481          case 0xC0010114:
482            regNum = MISCREG_VM_CR;
483            break;
484          case 0xC0010115:
485            regNum = MISCREG_IGNNE;
486            break;
487          case 0xC0010116:
488            regNum = MISCREG_SMM_CTL;
489            break;
490          case 0xC0010117:
491            regNum = MISCREG_VM_HSAVE_PA;
492            break;
493          default:
494            return new GeneralProtection(0);
495        }
496        //The index is multiplied by the size of a MiscReg so that
497        //any memory dependence calculations will not see these as
498        //overlapping.
499        req->setPaddr(regNum * sizeof(MiscReg));
500        return NoFault;
501    } else if (prefix == IntAddrPrefixIO) {
502        // TODO If CPL > IOPL or in virtual mode, check the I/O permission
503        // bitmap in the TSS.
504
505        Addr IOPort = vaddr & ~IntAddrPrefixMask;
506        // Make sure the address fits in the expected 16 bit IO address
507        // space.
508        assert(!(IOPort & ~0xFFFF));
509        if (IOPort == 0xCF8 && req->getSize() == 4) {
510            req->setFlags(Request::MMAPPED_IPR);
511            req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
512        } else if ((IOPort & ~mask(2)) == 0xCFC) {
513            req->setFlags(Request::UNCACHEABLE);
514            Addr configAddress =
515                tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
516            if (bits(configAddress, 31, 31)) {
517                req->setPaddr(PhysAddrPrefixPciConfig |
518                        mbits(configAddress, 30, 2) |
519                        (IOPort & mask(2)));
520            } else {
521                req->setPaddr(PhysAddrPrefixIO | IOPort);
522            }
523        } else {
524            req->setFlags(Request::UNCACHEABLE);
525            req->setPaddr(PhysAddrPrefixIO | IOPort);
526        }
527        return NoFault;
528    } else {
529        panic("Access to unrecognized internal address space %#x.\n",
530                prefix);
531    }
532}
533
534Fault
535TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
536        Mode mode, bool &delayedResponse, bool timing)
537{
538    uint32_t flags = req->getFlags();
539    int seg = flags & SegmentFlagMask;
540    bool storeCheck = flags & (StoreCheck << FlagShift);
541
542    delayedResponse = false;
543
544    // If this is true, we're dealing with a request to a non-memory address
545    // space.
546    if (seg == SEGMENT_REG_MS) {
547        return translateInt(req, tc);
548    }
549
550    Addr vaddr = req->getVaddr();
551    DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
552
553    HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
554
555    // If protected mode has been enabled...
556    if (m5Reg.prot) {
557        DPRINTF(TLB, "In protected mode.\n");
558        // If we're not in 64-bit mode, do protection/limit checks
559        if (m5Reg.mode != LongMode) {
560            DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
561            // Check for a NULL segment selector.
562            if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR ||
563                        seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS)
564                    && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
565                return new GeneralProtection(0);
566            bool expandDown = false;
567            SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
568            if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
569                if (!attr.writable && (mode == Write || storeCheck))
570                    return new GeneralProtection(0);
571                if (!attr.readable && mode == Read)
572                    return new GeneralProtection(0);
573                expandDown = attr.expandDown;
574
575            }
576            Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
577            Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
578            // This assumes we're not in 64 bit mode. If we were, the default
579            // address size is 64 bits, overridable to 32.
580            int size = 32;
581            bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift));
582            SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
583            if ((csAttr.defaultSize && sizeOverride) ||
584                    (!csAttr.defaultSize && !sizeOverride))
585                size = 16;
586            Addr offset = bits(vaddr - base, size-1, 0);
587            Addr endOffset = offset + req->getSize() - 1;
588            if (expandDown) {
589                DPRINTF(TLB, "Checking an expand down segment.\n");
590                warn_once("Expand down segments are untested.\n");
591                if (offset <= limit || endOffset <= limit)
592                    return new GeneralProtection(0);
593            } else {
594                if (offset > limit || endOffset > limit)
595                    return new GeneralProtection(0);
596            }
597        }
598        // If paging is enabled, do the translation.
599        if (m5Reg.paging) {
600            DPRINTF(TLB, "Paging enabled.\n");
601            // The vaddr already has the segment base applied.
602            TlbEntry *entry = lookup(vaddr);
603            if (!entry) {
604#if FULL_SYSTEM
605                Fault fault = walker->start(tc, translation, req, mode);
606                if (timing || fault != NoFault) {
607                    // This gets ignored in atomic mode.
608                    delayedResponse = true;
609                    return fault;
610                }
611                entry = lookup(vaddr);
612                assert(entry);
613#else
614                DPRINTF(TLB, "Handling a TLB miss for "
615                        "address %#x at pc %#x.\n",
616                        vaddr, tc->instAddr());
617
618                Process *p = tc->getProcessPtr();
619                TlbEntry newEntry;
620                bool success = p->pTable->lookup(vaddr, newEntry);
621                if (!success && mode != Execute) {
622                    // This may fail because for some reason the requested
623                    // address is not allocatable on the stack.  If it's a stack
624                    // address, then it's because the address fell outside of
625                    // max stack range and user should increase max size of
626                    // stack.  Otherwise, it could be a random address that was
627                    // not in the page table and not on the stack.  Either way,
628                    // you'll end up with a page fault.
629                    if (p->checkAndAllocNextPage(vaddr))
630                        // Might as well not check this if you failed to
631                        // allocate.  Partially nested this just so code
632                        // maintainers can understand this is a separate and
633                        // necessary step not sufficient just by reading return
634                        // value of checkAndAlloc call because there is a side
635                        // effect.  This call will populate (it's called by
636                        // reference).
637                        success = p->pTable->lookup(vaddr, newEntry);
638                }
639                if (!success) {
640                    return new PageFault(vaddr, true, mode, true, false);
641                } else {
642                    Addr alignedVaddr = p->pTable->pageAlign(vaddr);
643                    DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
644                            newEntry.pageStart());
645                    entry = insert(alignedVaddr, newEntry);
646                }
647                DPRINTF(TLB, "Miss was serviced.\n");
648#endif
649            }
650            // Do paging protection checks.
651            bool inUser = (m5Reg.cpl == 3 &&
652                    !(flags & (CPL0FlagBit << FlagShift)));
653            CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
654            bool badWrite = (!entry->writable && (inUser || cr0.wp));
655            if ((inUser && !entry->user) || (mode == Write && badWrite)) {
656                // The page must have been present to get into the TLB in
657                // the first place. We'll assume the reserved bits are
658                // fine even though we're not checking them.
659                return new PageFault(vaddr, true, mode, inUser, false);
660            }
661            if (storeCheck && badWrite) {
662                // This would fault if this were a write, so return a page
663                // fault that reflects that happening.
664                return new PageFault(vaddr, true, Write, inUser, false);
665            }
666
667
668            DPRINTF(TLB, "Entry found with paddr %#x, "
669                    "doing protection checks.\n", entry->paddr);
670            Addr paddr = entry->paddr | (vaddr & (entry->size-1));
671            DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
672            req->setPaddr(paddr);
673            if (entry->uncacheable)
674                req->setFlags(Request::UNCACHEABLE);
675        } else {
676            //Use the address which already has segmentation applied.
677            DPRINTF(TLB, "Paging disabled.\n");
678            DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
679            req->setPaddr(vaddr);
680        }
681    } else {
682        // Real mode
683        DPRINTF(TLB, "In real mode.\n");
684        DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
685        req->setPaddr(vaddr);
686    }
687    // Check for an access to the local APIC
688#if FULL_SYSTEM
689    LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
690    Addr baseAddr = localApicBase.base * PageBytes;
691    Addr paddr = req->getPaddr();
692    if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
693        // The Intel developer's manuals say the below restrictions apply,
694        // but the linux kernel, because of a compiler optimization, breaks
695        // them.
696        /*
697        // Check alignment
698        if (paddr & ((32/8) - 1))
699            return new GeneralProtection(0);
700        // Check access size
701        if (req->getSize() != (32/8))
702            return new GeneralProtection(0);
703        */
704        // Force the access to be uncacheable.
705        req->setFlags(Request::UNCACHEABLE);
706        req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr));
707    }
708#endif
709    return NoFault;
710};
711
712Fault
713TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
714{
715    bool delayedResponse;
716    return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
717}
718
719void
720TLB::translateTiming(RequestPtr req, ThreadContext *tc,
721        Translation *translation, Mode mode)
722{
723    bool delayedResponse;
724    assert(translation);
725    Fault fault =
726        TLB::translate(req, tc, translation, mode, delayedResponse, true);
727    if (!delayedResponse)
728        translation->finish(fault, req, tc, mode);
729}
730
731#if FULL_SYSTEM
732
733Tick
734TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
735{
736    return tc->getCpuPtr()->ticks(1);
737}
738
739Tick
740TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
741{
742    return tc->getCpuPtr()->ticks(1);
743}
744
745Walker *
746TLB::getWalker()
747{
748    return walker;
749}
750
751#endif
752
753void
754TLB::serialize(std::ostream &os)
755{
756}
757
758void
759TLB::unserialize(Checkpoint *cp, const std::string &section)
760{
761}
762
763} // namespace X86ISA
764
765X86ISA::TLB *
766X86TLBParams::create()
767{
768    return new X86ISA::TLB(this);
769}
770