tlb.cc revision 6315
14997Sgblack@eecs.umich.edu/* 25417Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 34997Sgblack@eecs.umich.edu * All rights reserved. 44997Sgblack@eecs.umich.edu * 54997Sgblack@eecs.umich.edu * Redistribution and use of this software in source and binary forms, 64997Sgblack@eecs.umich.edu * with or without modification, are permitted provided that the 74997Sgblack@eecs.umich.edu * following conditions are met: 84997Sgblack@eecs.umich.edu * 94997Sgblack@eecs.umich.edu * The software must be used only for Non-Commercial Use which means any 104997Sgblack@eecs.umich.edu * use which is NOT directed to receiving any direct monetary 114997Sgblack@eecs.umich.edu * compensation for, or commercial advantage from such use. Illustrative 124997Sgblack@eecs.umich.edu * examples of non-commercial use are academic research, personal study, 134997Sgblack@eecs.umich.edu * teaching, education and corporate research & development. 144997Sgblack@eecs.umich.edu * Illustrative examples of commercial use are distributing products for 154997Sgblack@eecs.umich.edu * commercial advantage and providing services using the software for 164997Sgblack@eecs.umich.edu * commercial advantage. 174997Sgblack@eecs.umich.edu * 184997Sgblack@eecs.umich.edu * If you wish to use this software or functionality therein that may be 194997Sgblack@eecs.umich.edu * covered by patents for commercial use, please contact: 204997Sgblack@eecs.umich.edu * Director of Intellectual Property Licensing 214997Sgblack@eecs.umich.edu * Office of Strategy and Technology 224997Sgblack@eecs.umich.edu * Hewlett-Packard Company 234997Sgblack@eecs.umich.edu * 1501 Page Mill Road 244997Sgblack@eecs.umich.edu * Palo Alto, California 94304 254997Sgblack@eecs.umich.edu * 264997Sgblack@eecs.umich.edu * Redistributions of source code must retain the above copyright notice, 274997Sgblack@eecs.umich.edu * this list of conditions and the following disclaimer. Redistributions 284997Sgblack@eecs.umich.edu * in binary form must reproduce the above copyright notice, this list of 294997Sgblack@eecs.umich.edu * conditions and the following disclaimer in the documentation and/or 304997Sgblack@eecs.umich.edu * other materials provided with the distribution. Neither the name of 314997Sgblack@eecs.umich.edu * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 324997Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 334997Sgblack@eecs.umich.edu * this software without specific prior written permission. No right of 344997Sgblack@eecs.umich.edu * sublicense is granted herewith. Derivatives of the software and 354997Sgblack@eecs.umich.edu * output created using the software may be prepared, but only for 364997Sgblack@eecs.umich.edu * Non-Commercial Uses. Derivatives of the software may be shared with 374997Sgblack@eecs.umich.edu * others provided: (i) the others agree to abide by the list of 384997Sgblack@eecs.umich.edu * conditions herein which includes the Non-Commercial Use restrictions; 394997Sgblack@eecs.umich.edu * and (ii) such Derivatives of the software include the above copyright 404997Sgblack@eecs.umich.edu * notice to acknowledge the contribution from this software where 414997Sgblack@eecs.umich.edu * applicable, this list of conditions and the disclaimer below. 424997Sgblack@eecs.umich.edu * 434997Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 444997Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 454997Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 464997Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 474997Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 484997Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 494997Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 504997Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 514997Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 524997Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 534997Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 544997Sgblack@eecs.umich.edu * 554997Sgblack@eecs.umich.edu * Authors: Gabe Black 564997Sgblack@eecs.umich.edu */ 574997Sgblack@eecs.umich.edu 584997Sgblack@eecs.umich.edu#include <cstring> 594997Sgblack@eecs.umich.edu 605086Sgblack@eecs.umich.edu#include "config/full_system.hh" 615086Sgblack@eecs.umich.edu 626315Sgblack@eecs.umich.edu#include "arch/x86/faults.hh" 635912Sgblack@eecs.umich.edu#include "arch/x86/insts/microldstop.hh" 646313Sgblack@eecs.umich.edu#include "arch/x86/miscregs.hh" 655124Sgblack@eecs.umich.edu#include "arch/x86/pagetable.hh" 665086Sgblack@eecs.umich.edu#include "arch/x86/tlb.hh" 675149Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh" 685086Sgblack@eecs.umich.edu#include "base/bitfield.hh" 695086Sgblack@eecs.umich.edu#include "base/trace.hh" 705237Sgblack@eecs.umich.edu#include "config/full_system.hh" 715086Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 725086Sgblack@eecs.umich.edu#include "cpu/base.hh" 735086Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 745086Sgblack@eecs.umich.edu#include "mem/request.hh" 755245Sgblack@eecs.umich.edu 765245Sgblack@eecs.umich.edu#if FULL_SYSTEM 775245Sgblack@eecs.umich.edu#include "arch/x86/pagetable_walker.hh" 785895Sgblack@eecs.umich.edu#else 795895Sgblack@eecs.umich.edu#include "mem/page_table.hh" 805895Sgblack@eecs.umich.edu#include "sim/process.hh" 815245Sgblack@eecs.umich.edu#endif 825086Sgblack@eecs.umich.edu 835086Sgblack@eecs.umich.edunamespace X86ISA { 845086Sgblack@eecs.umich.edu 855358Sgblack@eecs.umich.eduTLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size) 865124Sgblack@eecs.umich.edu{ 875124Sgblack@eecs.umich.edu tlb = new TlbEntry[size]; 885124Sgblack@eecs.umich.edu std::memset(tlb, 0, sizeof(TlbEntry) * size); 895124Sgblack@eecs.umich.edu 905124Sgblack@eecs.umich.edu for (int x = 0; x < size; x++) 915124Sgblack@eecs.umich.edu freeList.push_back(&tlb[x]); 925124Sgblack@eecs.umich.edu 935237Sgblack@eecs.umich.edu#if FULL_SYSTEM 945245Sgblack@eecs.umich.edu walker = p->walker; 955245Sgblack@eecs.umich.edu walker->setTLB(this); 965245Sgblack@eecs.umich.edu#endif 975236Sgblack@eecs.umich.edu} 985236Sgblack@eecs.umich.edu 995895Sgblack@eecs.umich.eduTlbEntry * 1005124Sgblack@eecs.umich.eduTLB::insert(Addr vpn, TlbEntry &entry) 1015124Sgblack@eecs.umich.edu{ 1025124Sgblack@eecs.umich.edu //TODO Deal with conflicting entries 1035124Sgblack@eecs.umich.edu 1045124Sgblack@eecs.umich.edu TlbEntry *newEntry = NULL; 1055124Sgblack@eecs.umich.edu if (!freeList.empty()) { 1065124Sgblack@eecs.umich.edu newEntry = freeList.front(); 1075124Sgblack@eecs.umich.edu freeList.pop_front(); 1085124Sgblack@eecs.umich.edu } else { 1095124Sgblack@eecs.umich.edu newEntry = entryList.back(); 1105124Sgblack@eecs.umich.edu entryList.pop_back(); 1115124Sgblack@eecs.umich.edu } 1125124Sgblack@eecs.umich.edu *newEntry = entry; 1135124Sgblack@eecs.umich.edu newEntry->vaddr = vpn; 1145124Sgblack@eecs.umich.edu entryList.push_front(newEntry); 1155895Sgblack@eecs.umich.edu return newEntry; 1165124Sgblack@eecs.umich.edu} 1175124Sgblack@eecs.umich.edu 1185360Sgblack@eecs.umich.eduTLB::EntryList::iterator 1195360Sgblack@eecs.umich.eduTLB::lookupIt(Addr va, bool update_lru) 1205124Sgblack@eecs.umich.edu{ 1215124Sgblack@eecs.umich.edu //TODO make this smarter at some point 1225124Sgblack@eecs.umich.edu EntryList::iterator entry; 1235124Sgblack@eecs.umich.edu for (entry = entryList.begin(); entry != entryList.end(); entry++) { 1245124Sgblack@eecs.umich.edu if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) { 1255124Sgblack@eecs.umich.edu DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x " 1265124Sgblack@eecs.umich.edu "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size); 1275124Sgblack@eecs.umich.edu if (update_lru) { 1285360Sgblack@eecs.umich.edu entryList.push_front(*entry); 1295124Sgblack@eecs.umich.edu entryList.erase(entry); 1305360Sgblack@eecs.umich.edu entry = entryList.begin(); 1315124Sgblack@eecs.umich.edu } 1325360Sgblack@eecs.umich.edu break; 1335124Sgblack@eecs.umich.edu } 1345124Sgblack@eecs.umich.edu } 1355360Sgblack@eecs.umich.edu return entry; 1365360Sgblack@eecs.umich.edu} 1375360Sgblack@eecs.umich.edu 1385360Sgblack@eecs.umich.eduTlbEntry * 1395360Sgblack@eecs.umich.eduTLB::lookup(Addr va, bool update_lru) 1405360Sgblack@eecs.umich.edu{ 1415360Sgblack@eecs.umich.edu EntryList::iterator entry = lookupIt(va, update_lru); 1425360Sgblack@eecs.umich.edu if (entry == entryList.end()) 1435360Sgblack@eecs.umich.edu return NULL; 1445360Sgblack@eecs.umich.edu else 1455360Sgblack@eecs.umich.edu return *entry; 1465124Sgblack@eecs.umich.edu} 1475124Sgblack@eecs.umich.edu 1485124Sgblack@eecs.umich.eduvoid 1495124Sgblack@eecs.umich.eduTLB::invalidateAll() 1505124Sgblack@eecs.umich.edu{ 1515242Sgblack@eecs.umich.edu DPRINTF(TLB, "Invalidating all entries.\n"); 1525242Sgblack@eecs.umich.edu while (!entryList.empty()) { 1535242Sgblack@eecs.umich.edu TlbEntry *entry = entryList.front(); 1545242Sgblack@eecs.umich.edu entryList.pop_front(); 1555242Sgblack@eecs.umich.edu freeList.push_back(entry); 1565242Sgblack@eecs.umich.edu } 1575124Sgblack@eecs.umich.edu} 1585124Sgblack@eecs.umich.edu 1595124Sgblack@eecs.umich.eduvoid 1605357Sgblack@eecs.umich.eduTLB::setConfigAddress(uint32_t addr) 1615357Sgblack@eecs.umich.edu{ 1625357Sgblack@eecs.umich.edu configAddress = addr; 1635357Sgblack@eecs.umich.edu} 1645357Sgblack@eecs.umich.edu 1655357Sgblack@eecs.umich.eduvoid 1665124Sgblack@eecs.umich.eduTLB::invalidateNonGlobal() 1675124Sgblack@eecs.umich.edu{ 1685242Sgblack@eecs.umich.edu DPRINTF(TLB, "Invalidating all non global entries.\n"); 1695242Sgblack@eecs.umich.edu EntryList::iterator entryIt; 1705242Sgblack@eecs.umich.edu for (entryIt = entryList.begin(); entryIt != entryList.end();) { 1715242Sgblack@eecs.umich.edu if (!(*entryIt)->global) { 1725242Sgblack@eecs.umich.edu freeList.push_back(*entryIt); 1735242Sgblack@eecs.umich.edu entryList.erase(entryIt++); 1745242Sgblack@eecs.umich.edu } else { 1755242Sgblack@eecs.umich.edu entryIt++; 1765242Sgblack@eecs.umich.edu } 1775242Sgblack@eecs.umich.edu } 1785124Sgblack@eecs.umich.edu} 1795124Sgblack@eecs.umich.edu 1805124Sgblack@eecs.umich.eduvoid 1815358Sgblack@eecs.umich.eduTLB::demapPage(Addr va, uint64_t asn) 1825086Sgblack@eecs.umich.edu{ 1835359Sgblack@eecs.umich.edu EntryList::iterator entry = lookupIt(va, false); 1845359Sgblack@eecs.umich.edu if (entry != entryList.end()) { 1855359Sgblack@eecs.umich.edu freeList.push_back(*entry); 1865359Sgblack@eecs.umich.edu entryList.erase(entry); 1875359Sgblack@eecs.umich.edu } 1885086Sgblack@eecs.umich.edu} 1895086Sgblack@eecs.umich.edu 1905086Sgblack@eecs.umich.eduFault 1916141Sgblack@eecs.umich.eduTLB::translateInt(RequestPtr req, ThreadContext *tc) 1926141Sgblack@eecs.umich.edu{ 1936141Sgblack@eecs.umich.edu DPRINTF(TLB, "Addresses references internal memory.\n"); 1946141Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr(); 1956141Sgblack@eecs.umich.edu Addr prefix = (vaddr >> 3) & IntAddrPrefixMask; 1966141Sgblack@eecs.umich.edu if (prefix == IntAddrPrefixCPUID) { 1976141Sgblack@eecs.umich.edu panic("CPUID memory space not yet implemented!\n"); 1986141Sgblack@eecs.umich.edu } else if (prefix == IntAddrPrefixMSR) { 1996141Sgblack@eecs.umich.edu vaddr = vaddr >> 3; 2006141Sgblack@eecs.umich.edu req->setMmapedIpr(true); 2016141Sgblack@eecs.umich.edu Addr regNum = 0; 2026141Sgblack@eecs.umich.edu switch (vaddr & ~IntAddrPrefixMask) { 2036141Sgblack@eecs.umich.edu case 0x10: 2046141Sgblack@eecs.umich.edu regNum = MISCREG_TSC; 2056141Sgblack@eecs.umich.edu break; 2066141Sgblack@eecs.umich.edu case 0x1B: 2076141Sgblack@eecs.umich.edu regNum = MISCREG_APIC_BASE; 2086141Sgblack@eecs.umich.edu break; 2096141Sgblack@eecs.umich.edu case 0xFE: 2106141Sgblack@eecs.umich.edu regNum = MISCREG_MTRRCAP; 2116141Sgblack@eecs.umich.edu break; 2126141Sgblack@eecs.umich.edu case 0x174: 2136141Sgblack@eecs.umich.edu regNum = MISCREG_SYSENTER_CS; 2146141Sgblack@eecs.umich.edu break; 2156141Sgblack@eecs.umich.edu case 0x175: 2166141Sgblack@eecs.umich.edu regNum = MISCREG_SYSENTER_ESP; 2176141Sgblack@eecs.umich.edu break; 2186141Sgblack@eecs.umich.edu case 0x176: 2196141Sgblack@eecs.umich.edu regNum = MISCREG_SYSENTER_EIP; 2206141Sgblack@eecs.umich.edu break; 2216141Sgblack@eecs.umich.edu case 0x179: 2226141Sgblack@eecs.umich.edu regNum = MISCREG_MCG_CAP; 2236141Sgblack@eecs.umich.edu break; 2246141Sgblack@eecs.umich.edu case 0x17A: 2256141Sgblack@eecs.umich.edu regNum = MISCREG_MCG_STATUS; 2266141Sgblack@eecs.umich.edu break; 2276141Sgblack@eecs.umich.edu case 0x17B: 2286141Sgblack@eecs.umich.edu regNum = MISCREG_MCG_CTL; 2296141Sgblack@eecs.umich.edu break; 2306141Sgblack@eecs.umich.edu case 0x1D9: 2316141Sgblack@eecs.umich.edu regNum = MISCREG_DEBUG_CTL_MSR; 2326141Sgblack@eecs.umich.edu break; 2336141Sgblack@eecs.umich.edu case 0x1DB: 2346141Sgblack@eecs.umich.edu regNum = MISCREG_LAST_BRANCH_FROM_IP; 2356141Sgblack@eecs.umich.edu break; 2366141Sgblack@eecs.umich.edu case 0x1DC: 2376141Sgblack@eecs.umich.edu regNum = MISCREG_LAST_BRANCH_TO_IP; 2386141Sgblack@eecs.umich.edu break; 2396141Sgblack@eecs.umich.edu case 0x1DD: 2406141Sgblack@eecs.umich.edu regNum = MISCREG_LAST_EXCEPTION_FROM_IP; 2416141Sgblack@eecs.umich.edu break; 2426141Sgblack@eecs.umich.edu case 0x1DE: 2436141Sgblack@eecs.umich.edu regNum = MISCREG_LAST_EXCEPTION_TO_IP; 2446141Sgblack@eecs.umich.edu break; 2456141Sgblack@eecs.umich.edu case 0x200: 2466141Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_0; 2476141Sgblack@eecs.umich.edu break; 2486141Sgblack@eecs.umich.edu case 0x201: 2496141Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_0; 2506141Sgblack@eecs.umich.edu break; 2516141Sgblack@eecs.umich.edu case 0x202: 2526141Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_1; 2536141Sgblack@eecs.umich.edu break; 2546141Sgblack@eecs.umich.edu case 0x203: 2556141Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_1; 2566141Sgblack@eecs.umich.edu break; 2576141Sgblack@eecs.umich.edu case 0x204: 2586141Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_2; 2596141Sgblack@eecs.umich.edu break; 2606141Sgblack@eecs.umich.edu case 0x205: 2616141Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_2; 2626141Sgblack@eecs.umich.edu break; 2636141Sgblack@eecs.umich.edu case 0x206: 2646141Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_3; 2656141Sgblack@eecs.umich.edu break; 2666141Sgblack@eecs.umich.edu case 0x207: 2676141Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_3; 2686141Sgblack@eecs.umich.edu break; 2696141Sgblack@eecs.umich.edu case 0x208: 2706141Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_4; 2716141Sgblack@eecs.umich.edu break; 2726141Sgblack@eecs.umich.edu case 0x209: 2736141Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_4; 2746141Sgblack@eecs.umich.edu break; 2756141Sgblack@eecs.umich.edu case 0x20A: 2766141Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_5; 2776141Sgblack@eecs.umich.edu break; 2786141Sgblack@eecs.umich.edu case 0x20B: 2796141Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_5; 2806141Sgblack@eecs.umich.edu break; 2816141Sgblack@eecs.umich.edu case 0x20C: 2826141Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_6; 2836141Sgblack@eecs.umich.edu break; 2846141Sgblack@eecs.umich.edu case 0x20D: 2856141Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_6; 2866141Sgblack@eecs.umich.edu break; 2876141Sgblack@eecs.umich.edu case 0x20E: 2886141Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_7; 2896141Sgblack@eecs.umich.edu break; 2906141Sgblack@eecs.umich.edu case 0x20F: 2916141Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_7; 2926141Sgblack@eecs.umich.edu break; 2936141Sgblack@eecs.umich.edu case 0x250: 2946141Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_64K_00000; 2956141Sgblack@eecs.umich.edu break; 2966141Sgblack@eecs.umich.edu case 0x258: 2976141Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_16K_80000; 2986141Sgblack@eecs.umich.edu break; 2996141Sgblack@eecs.umich.edu case 0x259: 3006141Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_16K_A0000; 3016141Sgblack@eecs.umich.edu break; 3026141Sgblack@eecs.umich.edu case 0x268: 3036141Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_C0000; 3046141Sgblack@eecs.umich.edu break; 3056141Sgblack@eecs.umich.edu case 0x269: 3066141Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_C8000; 3076141Sgblack@eecs.umich.edu break; 3086141Sgblack@eecs.umich.edu case 0x26A: 3096141Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_D0000; 3106141Sgblack@eecs.umich.edu break; 3116141Sgblack@eecs.umich.edu case 0x26B: 3126141Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_D8000; 3136141Sgblack@eecs.umich.edu break; 3146141Sgblack@eecs.umich.edu case 0x26C: 3156141Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_E0000; 3166141Sgblack@eecs.umich.edu break; 3176141Sgblack@eecs.umich.edu case 0x26D: 3186141Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_E8000; 3196141Sgblack@eecs.umich.edu break; 3206141Sgblack@eecs.umich.edu case 0x26E: 3216141Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_F0000; 3226141Sgblack@eecs.umich.edu break; 3236141Sgblack@eecs.umich.edu case 0x26F: 3246141Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_F8000; 3256141Sgblack@eecs.umich.edu break; 3266141Sgblack@eecs.umich.edu case 0x277: 3276141Sgblack@eecs.umich.edu regNum = MISCREG_PAT; 3286141Sgblack@eecs.umich.edu break; 3296141Sgblack@eecs.umich.edu case 0x2FF: 3306141Sgblack@eecs.umich.edu regNum = MISCREG_DEF_TYPE; 3316141Sgblack@eecs.umich.edu break; 3326141Sgblack@eecs.umich.edu case 0x400: 3336141Sgblack@eecs.umich.edu regNum = MISCREG_MC0_CTL; 3346141Sgblack@eecs.umich.edu break; 3356141Sgblack@eecs.umich.edu case 0x404: 3366141Sgblack@eecs.umich.edu regNum = MISCREG_MC1_CTL; 3376141Sgblack@eecs.umich.edu break; 3386141Sgblack@eecs.umich.edu case 0x408: 3396141Sgblack@eecs.umich.edu regNum = MISCREG_MC2_CTL; 3406141Sgblack@eecs.umich.edu break; 3416141Sgblack@eecs.umich.edu case 0x40C: 3426141Sgblack@eecs.umich.edu regNum = MISCREG_MC3_CTL; 3436141Sgblack@eecs.umich.edu break; 3446141Sgblack@eecs.umich.edu case 0x410: 3456141Sgblack@eecs.umich.edu regNum = MISCREG_MC4_CTL; 3466141Sgblack@eecs.umich.edu break; 3476141Sgblack@eecs.umich.edu case 0x414: 3486141Sgblack@eecs.umich.edu regNum = MISCREG_MC5_CTL; 3496141Sgblack@eecs.umich.edu break; 3506141Sgblack@eecs.umich.edu case 0x418: 3516141Sgblack@eecs.umich.edu regNum = MISCREG_MC6_CTL; 3526141Sgblack@eecs.umich.edu break; 3536141Sgblack@eecs.umich.edu case 0x41C: 3546141Sgblack@eecs.umich.edu regNum = MISCREG_MC7_CTL; 3556141Sgblack@eecs.umich.edu break; 3566141Sgblack@eecs.umich.edu case 0x401: 3576141Sgblack@eecs.umich.edu regNum = MISCREG_MC0_STATUS; 3586141Sgblack@eecs.umich.edu break; 3596141Sgblack@eecs.umich.edu case 0x405: 3606141Sgblack@eecs.umich.edu regNum = MISCREG_MC1_STATUS; 3616141Sgblack@eecs.umich.edu break; 3626141Sgblack@eecs.umich.edu case 0x409: 3636141Sgblack@eecs.umich.edu regNum = MISCREG_MC2_STATUS; 3646141Sgblack@eecs.umich.edu break; 3656141Sgblack@eecs.umich.edu case 0x40D: 3666141Sgblack@eecs.umich.edu regNum = MISCREG_MC3_STATUS; 3676141Sgblack@eecs.umich.edu break; 3686141Sgblack@eecs.umich.edu case 0x411: 3696141Sgblack@eecs.umich.edu regNum = MISCREG_MC4_STATUS; 3706141Sgblack@eecs.umich.edu break; 3716141Sgblack@eecs.umich.edu case 0x415: 3726141Sgblack@eecs.umich.edu regNum = MISCREG_MC5_STATUS; 3736141Sgblack@eecs.umich.edu break; 3746141Sgblack@eecs.umich.edu case 0x419: 3756141Sgblack@eecs.umich.edu regNum = MISCREG_MC6_STATUS; 3766141Sgblack@eecs.umich.edu break; 3776141Sgblack@eecs.umich.edu case 0x41D: 3786141Sgblack@eecs.umich.edu regNum = MISCREG_MC7_STATUS; 3796141Sgblack@eecs.umich.edu break; 3806141Sgblack@eecs.umich.edu case 0x402: 3816141Sgblack@eecs.umich.edu regNum = MISCREG_MC0_ADDR; 3826141Sgblack@eecs.umich.edu break; 3836141Sgblack@eecs.umich.edu case 0x406: 3846141Sgblack@eecs.umich.edu regNum = MISCREG_MC1_ADDR; 3856141Sgblack@eecs.umich.edu break; 3866141Sgblack@eecs.umich.edu case 0x40A: 3876141Sgblack@eecs.umich.edu regNum = MISCREG_MC2_ADDR; 3886141Sgblack@eecs.umich.edu break; 3896141Sgblack@eecs.umich.edu case 0x40E: 3906141Sgblack@eecs.umich.edu regNum = MISCREG_MC3_ADDR; 3916141Sgblack@eecs.umich.edu break; 3926141Sgblack@eecs.umich.edu case 0x412: 3936141Sgblack@eecs.umich.edu regNum = MISCREG_MC4_ADDR; 3946141Sgblack@eecs.umich.edu break; 3956141Sgblack@eecs.umich.edu case 0x416: 3966141Sgblack@eecs.umich.edu regNum = MISCREG_MC5_ADDR; 3976141Sgblack@eecs.umich.edu break; 3986141Sgblack@eecs.umich.edu case 0x41A: 3996141Sgblack@eecs.umich.edu regNum = MISCREG_MC6_ADDR; 4006141Sgblack@eecs.umich.edu break; 4016141Sgblack@eecs.umich.edu case 0x41E: 4026141Sgblack@eecs.umich.edu regNum = MISCREG_MC7_ADDR; 4036141Sgblack@eecs.umich.edu break; 4046141Sgblack@eecs.umich.edu case 0x403: 4056141Sgblack@eecs.umich.edu regNum = MISCREG_MC0_MISC; 4066141Sgblack@eecs.umich.edu break; 4076141Sgblack@eecs.umich.edu case 0x407: 4086141Sgblack@eecs.umich.edu regNum = MISCREG_MC1_MISC; 4096141Sgblack@eecs.umich.edu break; 4106141Sgblack@eecs.umich.edu case 0x40B: 4116141Sgblack@eecs.umich.edu regNum = MISCREG_MC2_MISC; 4126141Sgblack@eecs.umich.edu break; 4136141Sgblack@eecs.umich.edu case 0x40F: 4146141Sgblack@eecs.umich.edu regNum = MISCREG_MC3_MISC; 4156141Sgblack@eecs.umich.edu break; 4166141Sgblack@eecs.umich.edu case 0x413: 4176141Sgblack@eecs.umich.edu regNum = MISCREG_MC4_MISC; 4186141Sgblack@eecs.umich.edu break; 4196141Sgblack@eecs.umich.edu case 0x417: 4206141Sgblack@eecs.umich.edu regNum = MISCREG_MC5_MISC; 4216141Sgblack@eecs.umich.edu break; 4226141Sgblack@eecs.umich.edu case 0x41B: 4236141Sgblack@eecs.umich.edu regNum = MISCREG_MC6_MISC; 4246141Sgblack@eecs.umich.edu break; 4256141Sgblack@eecs.umich.edu case 0x41F: 4266141Sgblack@eecs.umich.edu regNum = MISCREG_MC7_MISC; 4276141Sgblack@eecs.umich.edu break; 4286141Sgblack@eecs.umich.edu case 0xC0000080: 4296141Sgblack@eecs.umich.edu regNum = MISCREG_EFER; 4306141Sgblack@eecs.umich.edu break; 4316141Sgblack@eecs.umich.edu case 0xC0000081: 4326141Sgblack@eecs.umich.edu regNum = MISCREG_STAR; 4336141Sgblack@eecs.umich.edu break; 4346141Sgblack@eecs.umich.edu case 0xC0000082: 4356141Sgblack@eecs.umich.edu regNum = MISCREG_LSTAR; 4366141Sgblack@eecs.umich.edu break; 4376141Sgblack@eecs.umich.edu case 0xC0000083: 4386141Sgblack@eecs.umich.edu regNum = MISCREG_CSTAR; 4396141Sgblack@eecs.umich.edu break; 4406141Sgblack@eecs.umich.edu case 0xC0000084: 4416141Sgblack@eecs.umich.edu regNum = MISCREG_SF_MASK; 4426141Sgblack@eecs.umich.edu break; 4436141Sgblack@eecs.umich.edu case 0xC0000100: 4446141Sgblack@eecs.umich.edu regNum = MISCREG_FS_BASE; 4456141Sgblack@eecs.umich.edu break; 4466141Sgblack@eecs.umich.edu case 0xC0000101: 4476141Sgblack@eecs.umich.edu regNum = MISCREG_GS_BASE; 4486141Sgblack@eecs.umich.edu break; 4496141Sgblack@eecs.umich.edu case 0xC0000102: 4506141Sgblack@eecs.umich.edu regNum = MISCREG_KERNEL_GS_BASE; 4516141Sgblack@eecs.umich.edu break; 4526141Sgblack@eecs.umich.edu case 0xC0000103: 4536141Sgblack@eecs.umich.edu regNum = MISCREG_TSC_AUX; 4546141Sgblack@eecs.umich.edu break; 4556141Sgblack@eecs.umich.edu case 0xC0010000: 4566141Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_SEL0; 4576141Sgblack@eecs.umich.edu break; 4586141Sgblack@eecs.umich.edu case 0xC0010001: 4596141Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_SEL1; 4606141Sgblack@eecs.umich.edu break; 4616141Sgblack@eecs.umich.edu case 0xC0010002: 4626141Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_SEL2; 4636141Sgblack@eecs.umich.edu break; 4646141Sgblack@eecs.umich.edu case 0xC0010003: 4656141Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_SEL3; 4666141Sgblack@eecs.umich.edu break; 4676141Sgblack@eecs.umich.edu case 0xC0010004: 4686141Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_CTR0; 4696141Sgblack@eecs.umich.edu break; 4706141Sgblack@eecs.umich.edu case 0xC0010005: 4716141Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_CTR1; 4726141Sgblack@eecs.umich.edu break; 4736141Sgblack@eecs.umich.edu case 0xC0010006: 4746141Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_CTR2; 4756141Sgblack@eecs.umich.edu break; 4766141Sgblack@eecs.umich.edu case 0xC0010007: 4776141Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_CTR3; 4786141Sgblack@eecs.umich.edu break; 4796141Sgblack@eecs.umich.edu case 0xC0010010: 4806141Sgblack@eecs.umich.edu regNum = MISCREG_SYSCFG; 4816141Sgblack@eecs.umich.edu break; 4826141Sgblack@eecs.umich.edu case 0xC0010016: 4836141Sgblack@eecs.umich.edu regNum = MISCREG_IORR_BASE0; 4846141Sgblack@eecs.umich.edu break; 4856141Sgblack@eecs.umich.edu case 0xC0010017: 4866141Sgblack@eecs.umich.edu regNum = MISCREG_IORR_BASE1; 4876141Sgblack@eecs.umich.edu break; 4886141Sgblack@eecs.umich.edu case 0xC0010018: 4896141Sgblack@eecs.umich.edu regNum = MISCREG_IORR_MASK0; 4906141Sgblack@eecs.umich.edu break; 4916141Sgblack@eecs.umich.edu case 0xC0010019: 4926141Sgblack@eecs.umich.edu regNum = MISCREG_IORR_MASK1; 4936141Sgblack@eecs.umich.edu break; 4946141Sgblack@eecs.umich.edu case 0xC001001A: 4956141Sgblack@eecs.umich.edu regNum = MISCREG_TOP_MEM; 4966141Sgblack@eecs.umich.edu break; 4976141Sgblack@eecs.umich.edu case 0xC001001D: 4986141Sgblack@eecs.umich.edu regNum = MISCREG_TOP_MEM2; 4996141Sgblack@eecs.umich.edu break; 5006141Sgblack@eecs.umich.edu case 0xC0010114: 5016141Sgblack@eecs.umich.edu regNum = MISCREG_VM_CR; 5026141Sgblack@eecs.umich.edu break; 5036141Sgblack@eecs.umich.edu case 0xC0010115: 5046141Sgblack@eecs.umich.edu regNum = MISCREG_IGNNE; 5056141Sgblack@eecs.umich.edu break; 5066141Sgblack@eecs.umich.edu case 0xC0010116: 5076141Sgblack@eecs.umich.edu regNum = MISCREG_SMM_CTL; 5086141Sgblack@eecs.umich.edu break; 5096141Sgblack@eecs.umich.edu case 0xC0010117: 5106141Sgblack@eecs.umich.edu regNum = MISCREG_VM_HSAVE_PA; 5116141Sgblack@eecs.umich.edu break; 5126141Sgblack@eecs.umich.edu default: 5136141Sgblack@eecs.umich.edu return new GeneralProtection(0); 5146141Sgblack@eecs.umich.edu } 5156141Sgblack@eecs.umich.edu //The index is multiplied by the size of a MiscReg so that 5166141Sgblack@eecs.umich.edu //any memory dependence calculations will not see these as 5176141Sgblack@eecs.umich.edu //overlapping. 5186141Sgblack@eecs.umich.edu req->setPaddr(regNum * sizeof(MiscReg)); 5196141Sgblack@eecs.umich.edu return NoFault; 5206141Sgblack@eecs.umich.edu } else if (prefix == IntAddrPrefixIO) { 5216141Sgblack@eecs.umich.edu // TODO If CPL > IOPL or in virtual mode, check the I/O permission 5226141Sgblack@eecs.umich.edu // bitmap in the TSS. 5236141Sgblack@eecs.umich.edu 5246141Sgblack@eecs.umich.edu Addr IOPort = vaddr & ~IntAddrPrefixMask; 5256141Sgblack@eecs.umich.edu // Make sure the address fits in the expected 16 bit IO address 5266141Sgblack@eecs.umich.edu // space. 5276141Sgblack@eecs.umich.edu assert(!(IOPort & ~0xFFFF)); 5286141Sgblack@eecs.umich.edu if (IOPort == 0xCF8 && req->getSize() == 4) { 5296141Sgblack@eecs.umich.edu req->setMmapedIpr(true); 5306141Sgblack@eecs.umich.edu req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg)); 5316141Sgblack@eecs.umich.edu } else if ((IOPort & ~mask(2)) == 0xCFC) { 5326141Sgblack@eecs.umich.edu Addr configAddress = 5336141Sgblack@eecs.umich.edu tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS); 5346141Sgblack@eecs.umich.edu if (bits(configAddress, 31, 31)) { 5356141Sgblack@eecs.umich.edu req->setPaddr(PhysAddrPrefixPciConfig | 5366141Sgblack@eecs.umich.edu mbits(configAddress, 30, 2) | 5376141Sgblack@eecs.umich.edu (IOPort & mask(2))); 5386141Sgblack@eecs.umich.edu } 5396141Sgblack@eecs.umich.edu } else { 5406141Sgblack@eecs.umich.edu req->setPaddr(PhysAddrPrefixIO | IOPort); 5416141Sgblack@eecs.umich.edu } 5426141Sgblack@eecs.umich.edu return NoFault; 5436141Sgblack@eecs.umich.edu } else { 5446141Sgblack@eecs.umich.edu panic("Access to unrecognized internal address space %#x.\n", 5456141Sgblack@eecs.umich.edu prefix); 5466141Sgblack@eecs.umich.edu } 5476141Sgblack@eecs.umich.edu} 5486141Sgblack@eecs.umich.edu 5496141Sgblack@eecs.umich.eduFault 5506023Snate@binkert.orgTLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation, 5516023Snate@binkert.org Mode mode, bool &delayedResponse, bool timing) 5525086Sgblack@eecs.umich.edu{ 5536141Sgblack@eecs.umich.edu uint32_t flags = req->getFlags(); 5546141Sgblack@eecs.umich.edu int seg = flags & SegmentFlagMask; 5556141Sgblack@eecs.umich.edu bool storeCheck = flags & (StoreCheck << FlagShift); 5566141Sgblack@eecs.umich.edu 5576141Sgblack@eecs.umich.edu // If this is true, we're dealing with a request to a non-memory address 5586141Sgblack@eecs.umich.edu // space. 5596141Sgblack@eecs.umich.edu if (seg == SEGMENT_REG_MS) { 5606141Sgblack@eecs.umich.edu return translateInt(req, tc); 5616141Sgblack@eecs.umich.edu } 5626141Sgblack@eecs.umich.edu 5635895Sgblack@eecs.umich.edu delayedResponse = false; 5645124Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr(); 5655140Sgblack@eecs.umich.edu DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr); 5665140Sgblack@eecs.umich.edu 5676141Sgblack@eecs.umich.edu HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); 5685140Sgblack@eecs.umich.edu 5695140Sgblack@eecs.umich.edu // If protected mode has been enabled... 5706141Sgblack@eecs.umich.edu if (m5Reg.prot) { 5715237Sgblack@eecs.umich.edu DPRINTF(TLB, "In protected mode.\n"); 5725140Sgblack@eecs.umich.edu // If we're not in 64-bit mode, do protection/limit checks 5736141Sgblack@eecs.umich.edu if (m5Reg.mode != LongMode) { 5745237Sgblack@eecs.umich.edu DPRINTF(TLB, "Not in long mode. Checking segment protection.\n"); 5755431Sgblack@eecs.umich.edu // Check for a NULL segment selector. 5766059Sgblack@eecs.umich.edu if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR || 5776141Sgblack@eecs.umich.edu seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS) 5786059Sgblack@eecs.umich.edu && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg))) 5795431Sgblack@eecs.umich.edu return new GeneralProtection(0); 5805433Sgblack@eecs.umich.edu bool expandDown = false; 5815965Sgblack@eecs.umich.edu SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg)); 5825433Sgblack@eecs.umich.edu if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) { 5836099Sgblack@eecs.umich.edu if (!attr.writable && (mode == Write || storeCheck)) 5845433Sgblack@eecs.umich.edu return new GeneralProtection(0); 5856023Snate@binkert.org if (!attr.readable && mode == Read) 5865433Sgblack@eecs.umich.edu return new GeneralProtection(0); 5875433Sgblack@eecs.umich.edu expandDown = attr.expandDown; 5885965Sgblack@eecs.umich.edu 5895433Sgblack@eecs.umich.edu } 5905140Sgblack@eecs.umich.edu Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg)); 5915140Sgblack@eecs.umich.edu Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg)); 5925965Sgblack@eecs.umich.edu // This assumes we're not in 64 bit mode. If we were, the default 5935965Sgblack@eecs.umich.edu // address size is 64 bits, overridable to 32. 5945965Sgblack@eecs.umich.edu int size = 32; 5955965Sgblack@eecs.umich.edu bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift)); 5966141Sgblack@eecs.umich.edu SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR); 5975980Snate@binkert.org if ((csAttr.defaultSize && sizeOverride) || 5985980Snate@binkert.org (!csAttr.defaultSize && !sizeOverride)) 5995965Sgblack@eecs.umich.edu size = 16; 6005965Sgblack@eecs.umich.edu Addr offset = bits(vaddr - base, size-1, 0); 6015965Sgblack@eecs.umich.edu Addr endOffset = offset + req->getSize() - 1; 6025433Sgblack@eecs.umich.edu if (expandDown) { 6035237Sgblack@eecs.umich.edu DPRINTF(TLB, "Checking an expand down segment.\n"); 6045965Sgblack@eecs.umich.edu warn_once("Expand down segments are untested.\n"); 6055965Sgblack@eecs.umich.edu if (offset <= limit || endOffset <= limit) 6065965Sgblack@eecs.umich.edu return new GeneralProtection(0); 6075140Sgblack@eecs.umich.edu } else { 6085965Sgblack@eecs.umich.edu if (offset > limit || endOffset > limit) 6095965Sgblack@eecs.umich.edu return new GeneralProtection(0); 6105140Sgblack@eecs.umich.edu } 6115140Sgblack@eecs.umich.edu } 6125140Sgblack@eecs.umich.edu // If paging is enabled, do the translation. 6136141Sgblack@eecs.umich.edu if (m5Reg.paging) { 6145237Sgblack@eecs.umich.edu DPRINTF(TLB, "Paging enabled.\n"); 6155140Sgblack@eecs.umich.edu // The vaddr already has the segment base applied. 6165140Sgblack@eecs.umich.edu TlbEntry *entry = lookup(vaddr); 6175140Sgblack@eecs.umich.edu if (!entry) { 6185895Sgblack@eecs.umich.edu#if FULL_SYSTEM 6196023Snate@binkert.org Fault fault = walker->start(tc, translation, req, mode); 6205895Sgblack@eecs.umich.edu if (timing || fault != NoFault) { 6215895Sgblack@eecs.umich.edu // This gets ignored in atomic mode. 6225895Sgblack@eecs.umich.edu delayedResponse = true; 6235895Sgblack@eecs.umich.edu return fault; 6245895Sgblack@eecs.umich.edu } 6255895Sgblack@eecs.umich.edu entry = lookup(vaddr); 6265895Sgblack@eecs.umich.edu assert(entry); 6275895Sgblack@eecs.umich.edu#else 6285895Sgblack@eecs.umich.edu DPRINTF(TLB, "Handling a TLB miss for " 6295895Sgblack@eecs.umich.edu "address %#x at pc %#x.\n", 6305895Sgblack@eecs.umich.edu vaddr, tc->readPC()); 6315895Sgblack@eecs.umich.edu 6325895Sgblack@eecs.umich.edu Process *p = tc->getProcessPtr(); 6335895Sgblack@eecs.umich.edu TlbEntry newEntry; 6345895Sgblack@eecs.umich.edu bool success = p->pTable->lookup(vaddr, newEntry); 6356023Snate@binkert.org if(!success && mode != Execute) { 6365895Sgblack@eecs.umich.edu p->checkAndAllocNextPage(vaddr); 6375895Sgblack@eecs.umich.edu success = p->pTable->lookup(vaddr, newEntry); 6385895Sgblack@eecs.umich.edu } 6395895Sgblack@eecs.umich.edu if(!success) { 6405895Sgblack@eecs.umich.edu panic("Tried to execute unmapped address %#x.\n", vaddr); 6415895Sgblack@eecs.umich.edu } else { 6425895Sgblack@eecs.umich.edu Addr alignedVaddr = p->pTable->pageAlign(vaddr); 6435895Sgblack@eecs.umich.edu DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, 6445895Sgblack@eecs.umich.edu newEntry.pageStart()); 6455895Sgblack@eecs.umich.edu entry = insert(alignedVaddr, newEntry); 6465895Sgblack@eecs.umich.edu } 6475895Sgblack@eecs.umich.edu DPRINTF(TLB, "Miss was serviced.\n"); 6485895Sgblack@eecs.umich.edu#endif 6495140Sgblack@eecs.umich.edu } 6505895Sgblack@eecs.umich.edu // Do paging protection checks. 6516141Sgblack@eecs.umich.edu bool inUser = (m5Reg.cpl == 3 && 6525917Sgblack@eecs.umich.edu !(flags & (CPL0FlagBit << FlagShift))); 6535980Snate@binkert.org if ((inUser && !entry->user) || 6546023Snate@binkert.org (mode == Write && !entry->writable)) { 6555917Sgblack@eecs.umich.edu // The page must have been present to get into the TLB in 6565917Sgblack@eecs.umich.edu // the first place. We'll assume the reserved bits are 6575917Sgblack@eecs.umich.edu // fine even though we're not checking them. 6586023Snate@binkert.org return new PageFault(vaddr, true, mode, inUser, false); 6595917Sgblack@eecs.umich.edu } 6606099Sgblack@eecs.umich.edu if (storeCheck && !entry->writable) { 6616099Sgblack@eecs.umich.edu // This would fault if this were a write, so return a page 6626099Sgblack@eecs.umich.edu // fault that reflects that happening. 6636099Sgblack@eecs.umich.edu return new PageFault(vaddr, true, Write, inUser, false); 6646099Sgblack@eecs.umich.edu } 6655917Sgblack@eecs.umich.edu 6665917Sgblack@eecs.umich.edu 6675895Sgblack@eecs.umich.edu DPRINTF(TLB, "Entry found with paddr %#x, " 6685895Sgblack@eecs.umich.edu "doing protection checks.\n", entry->paddr); 6695895Sgblack@eecs.umich.edu Addr paddr = entry->paddr | (vaddr & (entry->size-1)); 6705895Sgblack@eecs.umich.edu DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr); 6715895Sgblack@eecs.umich.edu req->setPaddr(paddr); 6725140Sgblack@eecs.umich.edu } else { 6735140Sgblack@eecs.umich.edu //Use the address which already has segmentation applied. 6745237Sgblack@eecs.umich.edu DPRINTF(TLB, "Paging disabled.\n"); 6755237Sgblack@eecs.umich.edu DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 6765140Sgblack@eecs.umich.edu req->setPaddr(vaddr); 6775140Sgblack@eecs.umich.edu } 6785124Sgblack@eecs.umich.edu } else { 6795140Sgblack@eecs.umich.edu // Real mode 6805237Sgblack@eecs.umich.edu DPRINTF(TLB, "In real mode.\n"); 6815237Sgblack@eecs.umich.edu DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 6825140Sgblack@eecs.umich.edu req->setPaddr(vaddr); 6835124Sgblack@eecs.umich.edu } 6845360Sgblack@eecs.umich.edu // Check for an access to the local APIC 6855374Sgblack@eecs.umich.edu#if FULL_SYSTEM 6865360Sgblack@eecs.umich.edu LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE); 6875648Sgblack@eecs.umich.edu Addr baseAddr = localApicBase.base * PageBytes; 6885360Sgblack@eecs.umich.edu Addr paddr = req->getPaddr(); 6895648Sgblack@eecs.umich.edu if (baseAddr <= paddr && baseAddr + PageBytes > paddr) { 6905417Sgblack@eecs.umich.edu // The Intel developer's manuals say the below restrictions apply, 6915417Sgblack@eecs.umich.edu // but the linux kernel, because of a compiler optimization, breaks 6925417Sgblack@eecs.umich.edu // them. 6935417Sgblack@eecs.umich.edu /* 6945360Sgblack@eecs.umich.edu // Check alignment 6955360Sgblack@eecs.umich.edu if (paddr & ((32/8) - 1)) 6965360Sgblack@eecs.umich.edu return new GeneralProtection(0); 6975360Sgblack@eecs.umich.edu // Check access size 6985360Sgblack@eecs.umich.edu if (req->getSize() != (32/8)) 6995360Sgblack@eecs.umich.edu return new GeneralProtection(0); 7005417Sgblack@eecs.umich.edu */ 7015648Sgblack@eecs.umich.edu // Force the access to be uncacheable. 7025736Snate@binkert.org req->setFlags(Request::UNCACHEABLE); 7035714Shsul@eecs.umich.edu req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr)); 7045360Sgblack@eecs.umich.edu } 7055374Sgblack@eecs.umich.edu#endif 7065086Sgblack@eecs.umich.edu return NoFault; 7075086Sgblack@eecs.umich.edu}; 7085086Sgblack@eecs.umich.edu 7095140Sgblack@eecs.umich.eduFault 7106023Snate@binkert.orgTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 7115140Sgblack@eecs.umich.edu{ 7125895Sgblack@eecs.umich.edu bool delayedResponse; 7136023Snate@binkert.org return TLB::translate(req, tc, NULL, mode, delayedResponse, false); 7145140Sgblack@eecs.umich.edu} 7155140Sgblack@eecs.umich.edu 7165894Sgblack@eecs.umich.eduvoid 7176022Sgblack@eecs.umich.eduTLB::translateTiming(RequestPtr req, ThreadContext *tc, 7186023Snate@binkert.org Translation *translation, Mode mode) 7195894Sgblack@eecs.umich.edu{ 7205895Sgblack@eecs.umich.edu bool delayedResponse; 7215894Sgblack@eecs.umich.edu assert(translation); 7226023Snate@binkert.org Fault fault = 7236023Snate@binkert.org TLB::translate(req, tc, translation, mode, delayedResponse, true); 7245895Sgblack@eecs.umich.edu if (!delayedResponse) 7256023Snate@binkert.org translation->finish(fault, req, tc, mode); 7265894Sgblack@eecs.umich.edu} 7275894Sgblack@eecs.umich.edu 7285086Sgblack@eecs.umich.edu#if FULL_SYSTEM 7295086Sgblack@eecs.umich.edu 7305086Sgblack@eecs.umich.eduTick 7316022Sgblack@eecs.umich.eduTLB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 7325086Sgblack@eecs.umich.edu{ 7335100Ssaidi@eecs.umich.edu return tc->getCpuPtr()->ticks(1); 7345086Sgblack@eecs.umich.edu} 7355086Sgblack@eecs.umich.edu 7365086Sgblack@eecs.umich.eduTick 7376022Sgblack@eecs.umich.eduTLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 7385086Sgblack@eecs.umich.edu{ 7395100Ssaidi@eecs.umich.edu return tc->getCpuPtr()->ticks(1); 7405086Sgblack@eecs.umich.edu} 7415086Sgblack@eecs.umich.edu 7425086Sgblack@eecs.umich.edu#endif 7435086Sgblack@eecs.umich.edu 7445086Sgblack@eecs.umich.eduvoid 7455086Sgblack@eecs.umich.eduTLB::serialize(std::ostream &os) 7465086Sgblack@eecs.umich.edu{ 7475086Sgblack@eecs.umich.edu} 7485086Sgblack@eecs.umich.edu 7495086Sgblack@eecs.umich.eduvoid 7505086Sgblack@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 7515086Sgblack@eecs.umich.edu{ 7525086Sgblack@eecs.umich.edu} 7535086Sgblack@eecs.umich.edu 7545086Sgblack@eecs.umich.edu/* end namespace X86ISA */ } 7555086Sgblack@eecs.umich.edu 7566022Sgblack@eecs.umich.eduX86ISA::TLB * 7576022Sgblack@eecs.umich.eduX86TLBParams::create() 7584997Sgblack@eecs.umich.edu{ 7596022Sgblack@eecs.umich.edu return new X86ISA::TLB(this); 7604997Sgblack@eecs.umich.edu} 761