tlb.cc revision 5837
12810SN/A/* 212724Snikos.nikoleris@arm.com * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 38856Sandreas.hansson@arm.com * All rights reserved. 48856Sandreas.hansson@arm.com * 58856Sandreas.hansson@arm.com * Redistribution and use of this software in source and binary forms, 68856Sandreas.hansson@arm.com * with or without modification, are permitted provided that the 78856Sandreas.hansson@arm.com * following conditions are met: 88856Sandreas.hansson@arm.com * 98856Sandreas.hansson@arm.com * The software must be used only for Non-Commercial Use which means any 108856Sandreas.hansson@arm.com * use which is NOT directed to receiving any direct monetary 118856Sandreas.hansson@arm.com * compensation for, or commercial advantage from such use. Illustrative 128856Sandreas.hansson@arm.com * examples of non-commercial use are academic research, personal study, 138856Sandreas.hansson@arm.com * teaching, education and corporate research & development. 142810SN/A * Illustrative examples of commercial use are distributing products for 152810SN/A * commercial advantage and providing services using the software for 162810SN/A * commercial advantage. 172810SN/A * 182810SN/A * If you wish to use this software or functionality therein that may be 192810SN/A * covered by patents for commercial use, please contact: 202810SN/A * Director of Intellectual Property Licensing 212810SN/A * Office of Strategy and Technology 222810SN/A * Hewlett-Packard Company 232810SN/A * 1501 Page Mill Road 242810SN/A * Palo Alto, California 94304 252810SN/A * 262810SN/A * Redistributions of source code must retain the above copyright notice, 272810SN/A * this list of conditions and the following disclaimer. Redistributions 282810SN/A * in binary form must reproduce the above copyright notice, this list of 292810SN/A * conditions and the following disclaimer in the documentation and/or 302810SN/A * other materials provided with the distribution. Neither the name of 312810SN/A * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 322810SN/A * contributors may be used to endorse or promote products derived from 332810SN/A * this software without specific prior written permission. No right of 342810SN/A * sublicense is granted herewith. Derivatives of the software and 352810SN/A * output created using the software may be prepared, but only for 362810SN/A * Non-Commercial Uses. Derivatives of the software may be shared with 372810SN/A * others provided: (i) the others agree to abide by the list of 382810SN/A * conditions herein which includes the Non-Commercial Use restrictions; 392810SN/A * and (ii) such Derivatives of the software include the above copyright 402810SN/A * notice to acknowledge the contribution from this software where 414458SN/A * applicable, this list of conditions and the disclaimer below. 424458SN/A * 4312724Snikos.nikoleris@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 4412724Snikos.nikoleris@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 452810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 462810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 472810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 482810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 492810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 502810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 512810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 5211051Sandreas.hansson@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 5311051Sandreas.hansson@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 542810SN/A * 5512724Snikos.nikoleris@arm.com * Authors: Gabe Black 5612724Snikos.nikoleris@arm.com */ 577676Snate@binkert.org 582810SN/A#include <cstring> 5912724Snikos.nikoleris@arm.com 602810SN/A#include "config/full_system.hh" 612810SN/A 626215Snate@binkert.org#include "arch/x86/pagetable.hh" 638232Snate@binkert.org#include "arch/x86/tlb.hh" 648232Snate@binkert.org#include "arch/x86/x86_traits.hh" 6512724Snikos.nikoleris@arm.com#include "base/bitfield.hh" 6612724Snikos.nikoleris@arm.com#include "base/trace.hh" 675338Sstever@gmail.com#include "config/full_system.hh" 6812724Snikos.nikoleris@arm.com#include "cpu/thread_context.hh" 6911375Sandreas.hansson@arm.com#include "cpu/base.hh" 7012724Snikos.nikoleris@arm.com#include "mem/packet_access.hh" 712810SN/A#include "mem/request.hh" 722810SN/A 7312724Snikos.nikoleris@arm.com#if FULL_SYSTEM 748914Sandreas.hansson@arm.com#include "arch/x86/pagetable_walker.hh" 758229Snate@binkert.org#endif 762811SN/A 7712724Snikos.nikoleris@arm.comnamespace X86ISA { 784626SN/A 798833Sdam.sunwoo@arm.comTLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size) 802810SN/A{ 8112724Snikos.nikoleris@arm.com tlb = new TlbEntry[size]; 8212724Snikos.nikoleris@arm.com std::memset(tlb, 0, sizeof(TlbEntry) * size); 8312724Snikos.nikoleris@arm.com 8412724Snikos.nikoleris@arm.com for (int x = 0; x < size; x++) 8512724Snikos.nikoleris@arm.com freeList.push_back(&tlb[x]); 8612724Snikos.nikoleris@arm.com 8712724Snikos.nikoleris@arm.com#if FULL_SYSTEM 8812724Snikos.nikoleris@arm.com walker = p->walker; 892810SN/A walker->setTLB(this); 902810SN/A#endif 912810SN/A} 922810SN/A 932810SN/Avoid 9411375Sandreas.hansson@arm.comTLB::insert(Addr vpn, TlbEntry &entry) 954628SN/A{ 964628SN/A //TODO Deal with conflicting entries 974628SN/A 984628SN/A TlbEntry *newEntry = NULL; 994628SN/A if (!freeList.empty()) { 1004628SN/A newEntry = freeList.front(); 1014628SN/A freeList.pop_front(); 1024628SN/A } else { 1038737Skoansin.tan@gmail.com newEntry = entryList.back(); 1044628SN/A entryList.pop_back(); 1054628SN/A } 1064628SN/A *newEntry = entry; 1074628SN/A newEntry->vaddr = vpn; 1084628SN/A entryList.push_front(newEntry); 1094628SN/A} 1104628SN/A 1114628SN/ATLB::EntryList::iterator 1124628SN/ATLB::lookupIt(Addr va, bool update_lru) 1134628SN/A{ 1148737Skoansin.tan@gmail.com //TODO make this smarter at some point 1154628SN/A EntryList::iterator entry; 1168856Sandreas.hansson@arm.com for (entry = entryList.begin(); entry != entryList.end(); entry++) { 1178856Sandreas.hansson@arm.com if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) { 1188856Sandreas.hansson@arm.com DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x " 1198856Sandreas.hansson@arm.com "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size); 1208856Sandreas.hansson@arm.com if (update_lru) { 12110942Sandreas.hansson@arm.com entryList.push_front(*entry); 1228856Sandreas.hansson@arm.com entryList.erase(entry); 1238856Sandreas.hansson@arm.com entry = entryList.begin(); 1248856Sandreas.hansson@arm.com } 1258922Swilliam.wang@arm.com break; 1262810SN/A } 1278856Sandreas.hansson@arm.com } 1282844SN/A return entry; 1298856Sandreas.hansson@arm.com} 1308856Sandreas.hansson@arm.com 1318856Sandreas.hansson@arm.comTlbEntry * 13210713Sandreas.hansson@arm.comTLB::lookup(Addr va, bool update_lru) 1338856Sandreas.hansson@arm.com{ 13410942Sandreas.hansson@arm.com EntryList::iterator entry = lookupIt(va, update_lru); 1358856Sandreas.hansson@arm.com if (entry == entryList.end()) 13610942Sandreas.hansson@arm.com return NULL; 13710713Sandreas.hansson@arm.com else 1388856Sandreas.hansson@arm.com return *entry; 1398856Sandreas.hansson@arm.com} 1403738SN/A 1414458SN/A#if FULL_SYSTEM 1428856Sandreas.hansson@arm.comvoid 14310713Sandreas.hansson@arm.comTLB::walk(ThreadContext * _tc, Addr vaddr) 14410713Sandreas.hansson@arm.com{ 14510713Sandreas.hansson@arm.com walker->start(_tc, vaddr); 1468914Sandreas.hansson@arm.com} 1472810SN/A#endif 1488856Sandreas.hansson@arm.com 1498856Sandreas.hansson@arm.comvoid 1508856Sandreas.hansson@arm.comTLB::invalidateAll() 1518914Sandreas.hansson@arm.com{ 1528856Sandreas.hansson@arm.com DPRINTF(TLB, "Invalidating all entries.\n"); 1538922Swilliam.wang@arm.com while (!entryList.empty()) { 1548856Sandreas.hansson@arm.com TlbEntry *entry = entryList.front(); 1553013SN/A entryList.pop_front(); 1568856Sandreas.hansson@arm.com freeList.push_back(entry); 15712724Snikos.nikoleris@arm.com } 15812724Snikos.nikoleris@arm.com} 15912724Snikos.nikoleris@arm.com 16012724Snikos.nikoleris@arm.comvoid 16112724Snikos.nikoleris@arm.comTLB::setConfigAddress(uint32_t addr) 16212724Snikos.nikoleris@arm.com{ 16312724Snikos.nikoleris@arm.com configAddress = addr; 16412724Snikos.nikoleris@arm.com} 16512724Snikos.nikoleris@arm.com 16612724Snikos.nikoleris@arm.comvoid 16712724Snikos.nikoleris@arm.comTLB::invalidateNonGlobal() 16812724Snikos.nikoleris@arm.com{ 16912724Snikos.nikoleris@arm.com DPRINTF(TLB, "Invalidating all non global entries.\n"); 17012724Snikos.nikoleris@arm.com EntryList::iterator entryIt; 17112724Snikos.nikoleris@arm.com for (entryIt = entryList.begin(); entryIt != entryList.end();) { 17212724Snikos.nikoleris@arm.com if (!(*entryIt)->global) { 17312724Snikos.nikoleris@arm.com freeList.push_back(*entryIt); 17412724Snikos.nikoleris@arm.com entryList.erase(entryIt++); 17512724Snikos.nikoleris@arm.com } else { 17612724Snikos.nikoleris@arm.com entryIt++; 17712724Snikos.nikoleris@arm.com } 17812724Snikos.nikoleris@arm.com } 17912724Snikos.nikoleris@arm.com} 18012724Snikos.nikoleris@arm.com 18112724Snikos.nikoleris@arm.comvoid 18212724Snikos.nikoleris@arm.comTLB::demapPage(Addr va, uint64_t asn) 18312724Snikos.nikoleris@arm.com{ 18412724Snikos.nikoleris@arm.com EntryList::iterator entry = lookupIt(va, false); 18512724Snikos.nikoleris@arm.com if (entry != entryList.end()) { 18612724Snikos.nikoleris@arm.com freeList.push_back(*entry); 18712724Snikos.nikoleris@arm.com entryList.erase(entry); 18812724Snikos.nikoleris@arm.com } 18912724Snikos.nikoleris@arm.com} 19012724Snikos.nikoleris@arm.com 19112724Snikos.nikoleris@arm.comtemplate<class TlbFault> 19212724Snikos.nikoleris@arm.comFault 19312724Snikos.nikoleris@arm.comTLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute) 19412724Snikos.nikoleris@arm.com{ 19512724Snikos.nikoleris@arm.com Addr vaddr = req->getVaddr(); 19612724Snikos.nikoleris@arm.com DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr); 19712724Snikos.nikoleris@arm.com uint32_t flags = req->getFlags(); 19812724Snikos.nikoleris@arm.com bool storeCheck = flags & StoreCheck; 19912724Snikos.nikoleris@arm.com 20012724Snikos.nikoleris@arm.com int seg = flags & mask(4); 20112724Snikos.nikoleris@arm.com 20212724Snikos.nikoleris@arm.com //XXX Junk code to surpress the warning 20312724Snikos.nikoleris@arm.com if (storeCheck); 20412724Snikos.nikoleris@arm.com 20512724Snikos.nikoleris@arm.com // If this is true, we're dealing with a request to read an internal 20612724Snikos.nikoleris@arm.com // value. 20712724Snikos.nikoleris@arm.com if (seg == SEGMENT_REG_MS) { 20812724Snikos.nikoleris@arm.com DPRINTF(TLB, "Addresses references internal memory.\n"); 20912724Snikos.nikoleris@arm.com Addr prefix = (vaddr >> 3) & IntAddrPrefixMask; 21012724Snikos.nikoleris@arm.com if (prefix == IntAddrPrefixCPUID) { 21112724Snikos.nikoleris@arm.com panic("CPUID memory space not yet implemented!\n"); 21212724Snikos.nikoleris@arm.com } else if (prefix == IntAddrPrefixMSR) { 21312724Snikos.nikoleris@arm.com vaddr = vaddr >> 3; 21412724Snikos.nikoleris@arm.com req->setMmapedIpr(true); 21512724Snikos.nikoleris@arm.com Addr regNum = 0; 21612724Snikos.nikoleris@arm.com switch (vaddr & ~IntAddrPrefixMask) { 21712724Snikos.nikoleris@arm.com case 0x10: 21812724Snikos.nikoleris@arm.com regNum = MISCREG_TSC; 21912724Snikos.nikoleris@arm.com break; 22012724Snikos.nikoleris@arm.com case 0x1B: 22112724Snikos.nikoleris@arm.com regNum = MISCREG_APIC_BASE; 22212724Snikos.nikoleris@arm.com break; 22312724Snikos.nikoleris@arm.com case 0xFE: 22412724Snikos.nikoleris@arm.com regNum = MISCREG_MTRRCAP; 22512724Snikos.nikoleris@arm.com break; 22612724Snikos.nikoleris@arm.com case 0x174: 22712724Snikos.nikoleris@arm.com regNum = MISCREG_SYSENTER_CS; 22812724Snikos.nikoleris@arm.com break; 22912724Snikos.nikoleris@arm.com case 0x175: 23012724Snikos.nikoleris@arm.com regNum = MISCREG_SYSENTER_ESP; 23112724Snikos.nikoleris@arm.com break; 23212724Snikos.nikoleris@arm.com case 0x176: 23312724Snikos.nikoleris@arm.com regNum = MISCREG_SYSENTER_EIP; 23412724Snikos.nikoleris@arm.com break; 23512724Snikos.nikoleris@arm.com case 0x179: 23612724Snikos.nikoleris@arm.com regNum = MISCREG_MCG_CAP; 23712724Snikos.nikoleris@arm.com break; 2388856Sandreas.hansson@arm.com case 0x17A: 2398856Sandreas.hansson@arm.com regNum = MISCREG_MCG_STATUS; 2408856Sandreas.hansson@arm.com break; 2418856Sandreas.hansson@arm.com case 0x17B: 2428856Sandreas.hansson@arm.com regNum = MISCREG_MCG_CTL; 2438856Sandreas.hansson@arm.com break; 2448856Sandreas.hansson@arm.com case 0x1D9: 2458922Swilliam.wang@arm.com regNum = MISCREG_DEBUG_CTL_MSR; 2468856Sandreas.hansson@arm.com break; 2475314SN/A case 0x1DB: 2482811SN/A regNum = MISCREG_LAST_BRANCH_FROM_IP; 2498856Sandreas.hansson@arm.com break; 2508856Sandreas.hansson@arm.com case 0x1DC: 2512810SN/A regNum = MISCREG_LAST_BRANCH_TO_IP; 2522810SN/A break; 2538856Sandreas.hansson@arm.com case 0x1DD: 2542810SN/A regNum = MISCREG_LAST_EXCEPTION_FROM_IP; 2552810SN/A break; 25610345SCurtis.Dunham@arm.com case 0x1DE: 25710345SCurtis.Dunham@arm.com regNum = MISCREG_LAST_EXCEPTION_TO_IP; 2588856Sandreas.hansson@arm.com break; 2598856Sandreas.hansson@arm.com case 0x200: 2608856Sandreas.hansson@arm.com regNum = MISCREG_MTRR_PHYS_BASE_0; 2618856Sandreas.hansson@arm.com break; 2623606SN/A case 0x201: 2638914Sandreas.hansson@arm.com regNum = MISCREG_MTRR_PHYS_MASK_0; 26410713Sandreas.hansson@arm.com break; 2658914Sandreas.hansson@arm.com case 0x202: 2662810SN/A regNum = MISCREG_MTRR_PHYS_BASE_1; 2672810SN/A break; 2682897SN/A case 0x203: 2692897SN/A regNum = MISCREG_MTRR_PHYS_MASK_1; 2708856Sandreas.hansson@arm.com break; 2714458SN/A case 0x204: 27210344Sandreas.hansson@arm.com regNum = MISCREG_MTRR_PHYS_BASE_2; 27310344Sandreas.hansson@arm.com break; 27412084Sspwilson2@wisc.edu case 0x205: 2758856Sandreas.hansson@arm.com regNum = MISCREG_MTRR_PHYS_MASK_2; 2762811SN/A break; 2772810SN/A case 0x206: 27812724Snikos.nikoleris@arm.com regNum = MISCREG_MTRR_PHYS_BASE_3; 27912724Snikos.nikoleris@arm.com break; 28012724Snikos.nikoleris@arm.com case 0x207: 28112724Snikos.nikoleris@arm.com regNum = MISCREG_MTRR_PHYS_MASK_3; 28212724Snikos.nikoleris@arm.com break; 28312724Snikos.nikoleris@arm.com case 0x208: 28412724Snikos.nikoleris@arm.com regNum = MISCREG_MTRR_PHYS_BASE_4; 28512724Snikos.nikoleris@arm.com break; 28612724Snikos.nikoleris@arm.com case 0x209: 28712724Snikos.nikoleris@arm.com regNum = MISCREG_MTRR_PHYS_MASK_4; 28812724Snikos.nikoleris@arm.com break; 28912724Snikos.nikoleris@arm.com case 0x20A: 29012724Snikos.nikoleris@arm.com regNum = MISCREG_MTRR_PHYS_BASE_5; 29112724Snikos.nikoleris@arm.com break; 29212724Snikos.nikoleris@arm.com case 0x20B: 29312724Snikos.nikoleris@arm.com regNum = MISCREG_MTRR_PHYS_MASK_5; 29412724Snikos.nikoleris@arm.com break; 29512724Snikos.nikoleris@arm.com case 0x20C: 29612724Snikos.nikoleris@arm.com regNum = MISCREG_MTRR_PHYS_BASE_6; 29712724Snikos.nikoleris@arm.com break; 29812724Snikos.nikoleris@arm.com case 0x20D: 29912724Snikos.nikoleris@arm.com regNum = MISCREG_MTRR_PHYS_MASK_6; 30012724Snikos.nikoleris@arm.com break; 30112724Snikos.nikoleris@arm.com case 0x20E: 30212724Snikos.nikoleris@arm.com regNum = MISCREG_MTRR_PHYS_BASE_7; 30312724Snikos.nikoleris@arm.com break; 30412724Snikos.nikoleris@arm.com case 0x20F: 30512724Snikos.nikoleris@arm.com regNum = MISCREG_MTRR_PHYS_MASK_7; 30612724Snikos.nikoleris@arm.com break; 30712724Snikos.nikoleris@arm.com case 0x250: 30812724Snikos.nikoleris@arm.com regNum = MISCREG_MTRR_FIX_64K_00000; 30912724Snikos.nikoleris@arm.com break; 31012724Snikos.nikoleris@arm.com case 0x258: 3113338SN/A regNum = MISCREG_MTRR_FIX_16K_80000; 3124626SN/A break; 3134626SN/A case 0x259: 3144626SN/A regNum = MISCREG_MTRR_FIX_16K_A0000; 3154626SN/A break; 3164626SN/A case 0x268: 3174626SN/A regNum = MISCREG_MTRR_FIX_4K_C0000; 31811375Sandreas.hansson@arm.com break; 3194626SN/A case 0x269: 32012724Snikos.nikoleris@arm.com regNum = MISCREG_MTRR_FIX_4K_C8000; 32112724Snikos.nikoleris@arm.com break; 32212724Snikos.nikoleris@arm.com case 0x26A: 32312724Snikos.nikoleris@arm.com regNum = MISCREG_MTRR_FIX_4K_D0000; 32412724Snikos.nikoleris@arm.com break; 32512724Snikos.nikoleris@arm.com case 0x26B: 32612724Snikos.nikoleris@arm.com regNum = MISCREG_MTRR_FIX_4K_D8000; 32712724Snikos.nikoleris@arm.com break; 32812724Snikos.nikoleris@arm.com case 0x26C: 32912724Snikos.nikoleris@arm.com regNum = MISCREG_MTRR_FIX_4K_E0000; 33012724Snikos.nikoleris@arm.com break; 33112724Snikos.nikoleris@arm.com case 0x26D: 33212724Snikos.nikoleris@arm.com regNum = MISCREG_MTRR_FIX_4K_E8000; 33312724Snikos.nikoleris@arm.com break; 33412724Snikos.nikoleris@arm.com case 0x26E: 33512724Snikos.nikoleris@arm.com regNum = MISCREG_MTRR_FIX_4K_F0000; 33612724Snikos.nikoleris@arm.com break; 33712724Snikos.nikoleris@arm.com case 0x26F: 33812724Snikos.nikoleris@arm.com regNum = MISCREG_MTRR_FIX_4K_F8000; 33912724Snikos.nikoleris@arm.com break; 34012724Snikos.nikoleris@arm.com case 0x277: 34112724Snikos.nikoleris@arm.com regNum = MISCREG_PAT; 34212724Snikos.nikoleris@arm.com break; 34312724Snikos.nikoleris@arm.com case 0x2FF: 34412724Snikos.nikoleris@arm.com regNum = MISCREG_DEF_TYPE; 34510693SMarco.Balboni@ARM.com break; 34611375Sandreas.hansson@arm.com case 0x400: 34711375Sandreas.hansson@arm.com regNum = MISCREG_MC0_CTL; 34810693SMarco.Balboni@ARM.com break; 34911375Sandreas.hansson@arm.com case 0x404: 3504628SN/A regNum = MISCREG_MC1_CTL; 35111375Sandreas.hansson@arm.com break; 35211375Sandreas.hansson@arm.com case 0x408: 35310764Sandreas.hansson@arm.com regNum = MISCREG_MC2_CTL; 35411375Sandreas.hansson@arm.com break; 35511375Sandreas.hansson@arm.com case 0x40C: 3564628SN/A regNum = MISCREG_MC3_CTL; 3574628SN/A break; 3584628SN/A case 0x410: 35911375Sandreas.hansson@arm.com regNum = MISCREG_MC4_CTL; 3604628SN/A break; 36111375Sandreas.hansson@arm.com case 0x414: 36211375Sandreas.hansson@arm.com regNum = MISCREG_MC5_CTL; 36311375Sandreas.hansson@arm.com break; 36411375Sandreas.hansson@arm.com case 0x418: 36511375Sandreas.hansson@arm.com regNum = MISCREG_MC6_CTL; 3664628SN/A break; 3674628SN/A case 0x41C: 3684628SN/A regNum = MISCREG_MC7_CTL; 3699347SAndreas.Sandberg@arm.com break; 37012724Snikos.nikoleris@arm.com case 0x401: 37112724Snikos.nikoleris@arm.com regNum = MISCREG_MC0_STATUS; 37212724Snikos.nikoleris@arm.com break; 37312724Snikos.nikoleris@arm.com case 0x405: 37412724Snikos.nikoleris@arm.com regNum = MISCREG_MC1_STATUS; 37512724Snikos.nikoleris@arm.com break; 37612724Snikos.nikoleris@arm.com case 0x409: 37712724Snikos.nikoleris@arm.com regNum = MISCREG_MC2_STATUS; 37811197Sandreas.hansson@arm.com break; 37912724Snikos.nikoleris@arm.com case 0x40D: 38012724Snikos.nikoleris@arm.com regNum = MISCREG_MC3_STATUS; 38112724Snikos.nikoleris@arm.com break; 38212724Snikos.nikoleris@arm.com case 0x411: 38312724Snikos.nikoleris@arm.com regNum = MISCREG_MC4_STATUS; 38412724Snikos.nikoleris@arm.com break; 38512724Snikos.nikoleris@arm.com case 0x415: 38612724Snikos.nikoleris@arm.com regNum = MISCREG_MC5_STATUS; 38712724Snikos.nikoleris@arm.com break; 38812724Snikos.nikoleris@arm.com case 0x419: 38912724Snikos.nikoleris@arm.com regNum = MISCREG_MC6_STATUS; 39012724Snikos.nikoleris@arm.com break; 39112724Snikos.nikoleris@arm.com case 0x41D: 39212724Snikos.nikoleris@arm.com regNum = MISCREG_MC7_STATUS; 39312724Snikos.nikoleris@arm.com break; 39412724Snikos.nikoleris@arm.com case 0x402: 39512724Snikos.nikoleris@arm.com regNum = MISCREG_MC0_ADDR; 39612724Snikos.nikoleris@arm.com break; 39712724Snikos.nikoleris@arm.com case 0x406: 39812724Snikos.nikoleris@arm.com regNum = MISCREG_MC1_ADDR; 39912724Snikos.nikoleris@arm.com break; 40012724Snikos.nikoleris@arm.com case 0x40A: 40112724Snikos.nikoleris@arm.com regNum = MISCREG_MC2_ADDR; 40212724Snikos.nikoleris@arm.com break; 40312724Snikos.nikoleris@arm.com case 0x40E: 40412724Snikos.nikoleris@arm.com regNum = MISCREG_MC3_ADDR; 40511197Sandreas.hansson@arm.com break; 40612724Snikos.nikoleris@arm.com case 0x412: 40712724Snikos.nikoleris@arm.com regNum = MISCREG_MC4_ADDR; 40812724Snikos.nikoleris@arm.com break; 40911197Sandreas.hansson@arm.com case 0x416: 41012724Snikos.nikoleris@arm.com regNum = MISCREG_MC5_ADDR; 41112724Snikos.nikoleris@arm.com break; 41212724Snikos.nikoleris@arm.com case 0x41A: 41312724Snikos.nikoleris@arm.com regNum = MISCREG_MC6_ADDR; 41412724Snikos.nikoleris@arm.com break; 41512724Snikos.nikoleris@arm.com case 0x41E: 41612724Snikos.nikoleris@arm.com regNum = MISCREG_MC7_ADDR; 41712724Snikos.nikoleris@arm.com break; 41812724Snikos.nikoleris@arm.com case 0x403: 41912724Snikos.nikoleris@arm.com regNum = MISCREG_MC0_MISC; 42012724Snikos.nikoleris@arm.com break; 42112724Snikos.nikoleris@arm.com case 0x407: 42212724Snikos.nikoleris@arm.com regNum = MISCREG_MC1_MISC; 42312724Snikos.nikoleris@arm.com break; 42412724Snikos.nikoleris@arm.com case 0x40B: 42512724Snikos.nikoleris@arm.com regNum = MISCREG_MC2_MISC; 42612724Snikos.nikoleris@arm.com break; 42712724Snikos.nikoleris@arm.com case 0x40F: 42812724Snikos.nikoleris@arm.com regNum = MISCREG_MC3_MISC; 42912724Snikos.nikoleris@arm.com break; 43012724Snikos.nikoleris@arm.com case 0x413: 43112724Snikos.nikoleris@arm.com regNum = MISCREG_MC4_MISC; 43212724Snikos.nikoleris@arm.com break; 43312724Snikos.nikoleris@arm.com case 0x417: 43412724Snikos.nikoleris@arm.com regNum = MISCREG_MC5_MISC; 43512724Snikos.nikoleris@arm.com break; 43612724Snikos.nikoleris@arm.com case 0x41B: 43712724Snikos.nikoleris@arm.com regNum = MISCREG_MC6_MISC; 43812724Snikos.nikoleris@arm.com break; 43912724Snikos.nikoleris@arm.com case 0x41F: 44012724Snikos.nikoleris@arm.com regNum = MISCREG_MC7_MISC; 44112724Snikos.nikoleris@arm.com break; 44212724Snikos.nikoleris@arm.com case 0xC0000080: 44312724Snikos.nikoleris@arm.com regNum = MISCREG_EFER; 44412724Snikos.nikoleris@arm.com break; 44512724Snikos.nikoleris@arm.com case 0xC0000081: 44612724Snikos.nikoleris@arm.com regNum = MISCREG_STAR; 44712724Snikos.nikoleris@arm.com break; 44812724Snikos.nikoleris@arm.com case 0xC0000082: 44912724Snikos.nikoleris@arm.com regNum = MISCREG_LSTAR; 45012724Snikos.nikoleris@arm.com break; 45112724Snikos.nikoleris@arm.com case 0xC0000083: 45212724Snikos.nikoleris@arm.com regNum = MISCREG_CSTAR; 45312724Snikos.nikoleris@arm.com break; 45412724Snikos.nikoleris@arm.com case 0xC0000084: 45512724Snikos.nikoleris@arm.com regNum = MISCREG_SF_MASK; 45612724Snikos.nikoleris@arm.com break; 45712724Snikos.nikoleris@arm.com case 0xC0000100: 45812724Snikos.nikoleris@arm.com regNum = MISCREG_FS_BASE; 45912724Snikos.nikoleris@arm.com break; 46012724Snikos.nikoleris@arm.com case 0xC0000101: 46112724Snikos.nikoleris@arm.com regNum = MISCREG_GS_BASE; 46212724Snikos.nikoleris@arm.com break; 46312724Snikos.nikoleris@arm.com case 0xC0000102: 46412724Snikos.nikoleris@arm.com regNum = MISCREG_KERNEL_GS_BASE; 46512724Snikos.nikoleris@arm.com break; 46612724Snikos.nikoleris@arm.com case 0xC0000103: 46712724Snikos.nikoleris@arm.com regNum = MISCREG_TSC_AUX; 46812724Snikos.nikoleris@arm.com break; 46912724Snikos.nikoleris@arm.com case 0xC0010000: 47012724Snikos.nikoleris@arm.com regNum = MISCREG_PERF_EVT_SEL0; 47112724Snikos.nikoleris@arm.com break; 47212724Snikos.nikoleris@arm.com case 0xC0010001: 47312724Snikos.nikoleris@arm.com regNum = MISCREG_PERF_EVT_SEL1; 47412724Snikos.nikoleris@arm.com break; 47512724Snikos.nikoleris@arm.com case 0xC0010002: 47612724Snikos.nikoleris@arm.com regNum = MISCREG_PERF_EVT_SEL2; 47712724Snikos.nikoleris@arm.com break; 47812724Snikos.nikoleris@arm.com case 0xC0010003: 47912724Snikos.nikoleris@arm.com regNum = MISCREG_PERF_EVT_SEL3; 48012724Snikos.nikoleris@arm.com break; 48112724Snikos.nikoleris@arm.com case 0xC0010004: 48212724Snikos.nikoleris@arm.com regNum = MISCREG_PERF_EVT_CTR0; 48312724Snikos.nikoleris@arm.com break; 48412724Snikos.nikoleris@arm.com case 0xC0010005: 48512724Snikos.nikoleris@arm.com regNum = MISCREG_PERF_EVT_CTR1; 48612724Snikos.nikoleris@arm.com break; 48712724Snikos.nikoleris@arm.com case 0xC0010006: 48812724Snikos.nikoleris@arm.com regNum = MISCREG_PERF_EVT_CTR2; 48912724Snikos.nikoleris@arm.com break; 49012724Snikos.nikoleris@arm.com case 0xC0010007: 49112724Snikos.nikoleris@arm.com regNum = MISCREG_PERF_EVT_CTR3; 49212724Snikos.nikoleris@arm.com break; 49312724Snikos.nikoleris@arm.com case 0xC0010010: 49412724Snikos.nikoleris@arm.com regNum = MISCREG_SYSCFG; 49512724Snikos.nikoleris@arm.com break; 49612724Snikos.nikoleris@arm.com case 0xC0010016: 49712724Snikos.nikoleris@arm.com regNum = MISCREG_IORR_BASE0; 49812724Snikos.nikoleris@arm.com break; 49912724Snikos.nikoleris@arm.com case 0xC0010017: 50012724Snikos.nikoleris@arm.com regNum = MISCREG_IORR_BASE1; 50112724Snikos.nikoleris@arm.com break; 50212724Snikos.nikoleris@arm.com case 0xC0010018: 50312724Snikos.nikoleris@arm.com regNum = MISCREG_IORR_MASK0; 50412724Snikos.nikoleris@arm.com break; 50512724Snikos.nikoleris@arm.com case 0xC0010019: 50612724Snikos.nikoleris@arm.com regNum = MISCREG_IORR_MASK1; 50712724Snikos.nikoleris@arm.com break; 50812724Snikos.nikoleris@arm.com case 0xC001001A: 50912724Snikos.nikoleris@arm.com regNum = MISCREG_TOP_MEM; 51012724Snikos.nikoleris@arm.com break; 51112724Snikos.nikoleris@arm.com case 0xC001001D: 51212724Snikos.nikoleris@arm.com regNum = MISCREG_TOP_MEM2; 51312724Snikos.nikoleris@arm.com break; 51412724Snikos.nikoleris@arm.com case 0xC0010114: 51512724Snikos.nikoleris@arm.com regNum = MISCREG_VM_CR; 51612724Snikos.nikoleris@arm.com break; 51712724Snikos.nikoleris@arm.com case 0xC0010115: 51812724Snikos.nikoleris@arm.com regNum = MISCREG_IGNNE; 51912724Snikos.nikoleris@arm.com break; 52012724Snikos.nikoleris@arm.com case 0xC0010116: 52112724Snikos.nikoleris@arm.com regNum = MISCREG_SMM_CTL; 52212724Snikos.nikoleris@arm.com break; 52312724Snikos.nikoleris@arm.com case 0xC0010117: 52412724Snikos.nikoleris@arm.com regNum = MISCREG_VM_HSAVE_PA; 52512724Snikos.nikoleris@arm.com break; 52612724Snikos.nikoleris@arm.com default: 52712724Snikos.nikoleris@arm.com return new GeneralProtection(0); 52812724Snikos.nikoleris@arm.com } 52912724Snikos.nikoleris@arm.com //The index is multiplied by the size of a MiscReg so that 53012724Snikos.nikoleris@arm.com //any memory dependence calculations will not see these as 53112724Snikos.nikoleris@arm.com //overlapping. 53212724Snikos.nikoleris@arm.com req->setPaddr(regNum * sizeof(MiscReg)); 53312724Snikos.nikoleris@arm.com return NoFault; 53412724Snikos.nikoleris@arm.com } else if (prefix == IntAddrPrefixIO) { 53512724Snikos.nikoleris@arm.com // TODO If CPL > IOPL or in virtual mode, check the I/O permission 53612724Snikos.nikoleris@arm.com // bitmap in the TSS. 53712724Snikos.nikoleris@arm.com 53812724Snikos.nikoleris@arm.com Addr IOPort = vaddr & ~IntAddrPrefixMask; 53912724Snikos.nikoleris@arm.com // Make sure the address fits in the expected 16 bit IO address 54012724Snikos.nikoleris@arm.com // space. 54112724Snikos.nikoleris@arm.com assert(!(IOPort & ~0xFFFF)); 54212724Snikos.nikoleris@arm.com if (IOPort == 0xCF8 && req->getSize() == 4) { 54312724Snikos.nikoleris@arm.com req->setMmapedIpr(true); 54412724Snikos.nikoleris@arm.com req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg)); 54512724Snikos.nikoleris@arm.com } else if ((IOPort & ~mask(2)) == 0xCFC) { 54612724Snikos.nikoleris@arm.com Addr configAddress = 54712724Snikos.nikoleris@arm.com tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS); 54812724Snikos.nikoleris@arm.com if (bits(configAddress, 31, 31)) { 54912724Snikos.nikoleris@arm.com req->setPaddr(PhysAddrPrefixPciConfig | 55012724Snikos.nikoleris@arm.com mbits(configAddress, 30, 2) | 55112724Snikos.nikoleris@arm.com (IOPort & mask(2))); 55212724Snikos.nikoleris@arm.com } 55312724Snikos.nikoleris@arm.com } else { 55412724Snikos.nikoleris@arm.com req->setPaddr(PhysAddrPrefixIO | IOPort); 55512724Snikos.nikoleris@arm.com } 55612724Snikos.nikoleris@arm.com return NoFault; 55712724Snikos.nikoleris@arm.com } else { 55812724Snikos.nikoleris@arm.com panic("Access to unrecognized internal address space %#x.\n", 55912724Snikos.nikoleris@arm.com prefix); 56012724Snikos.nikoleris@arm.com } 56112724Snikos.nikoleris@arm.com } 56212724Snikos.nikoleris@arm.com 56312724Snikos.nikoleris@arm.com // Get cr0. This will tell us how to do translation. We'll assume it was 56412724Snikos.nikoleris@arm.com // verified to be correct and consistent when set. 56512724Snikos.nikoleris@arm.com CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 56612724Snikos.nikoleris@arm.com 56712724Snikos.nikoleris@arm.com // If protected mode has been enabled... 56812724Snikos.nikoleris@arm.com if (cr0.pe) { 56912724Snikos.nikoleris@arm.com DPRINTF(TLB, "In protected mode.\n"); 57012724Snikos.nikoleris@arm.com Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER); 57112724Snikos.nikoleris@arm.com SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR); 57212724Snikos.nikoleris@arm.com // If we're not in 64-bit mode, do protection/limit checks 57312724Snikos.nikoleris@arm.com if (!efer.lma || !csAttr.longMode) { 57412724Snikos.nikoleris@arm.com DPRINTF(TLB, "Not in long mode. Checking segment protection.\n"); 57512724Snikos.nikoleris@arm.com // Check for a NULL segment selector. 57612724Snikos.nikoleris@arm.com if (!tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg))) 57712724Snikos.nikoleris@arm.com return new GeneralProtection(0); 57812724Snikos.nikoleris@arm.com bool expandDown = false; 57912724Snikos.nikoleris@arm.com if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) { 58012724Snikos.nikoleris@arm.com SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg)); 58112724Snikos.nikoleris@arm.com if (!attr.writable && write) 58212724Snikos.nikoleris@arm.com return new GeneralProtection(0); 58312724Snikos.nikoleris@arm.com if (!attr.readable && !write && !execute) 58412724Snikos.nikoleris@arm.com return new GeneralProtection(0); 58512724Snikos.nikoleris@arm.com expandDown = attr.expandDown; 58612724Snikos.nikoleris@arm.com } 58712724Snikos.nikoleris@arm.com Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg)); 58812724Snikos.nikoleris@arm.com Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg)); 58912724Snikos.nikoleris@arm.com if (expandDown) { 59012724Snikos.nikoleris@arm.com DPRINTF(TLB, "Checking an expand down segment.\n"); 59112724Snikos.nikoleris@arm.com // We don't have to worry about the access going around the 59212724Snikos.nikoleris@arm.com // end of memory because accesses will be broken up into 59312724Snikos.nikoleris@arm.com // pieces at boundaries aligned on sizes smaller than an 59412724Snikos.nikoleris@arm.com // entire address space. We do have to worry about the limit 59512724Snikos.nikoleris@arm.com // being less than the base. 59612724Snikos.nikoleris@arm.com if (limit < base) { 59712724Snikos.nikoleris@arm.com if (limit < vaddr + req->getSize() && vaddr < base) 59812724Snikos.nikoleris@arm.com return new GeneralProtection(0); 59912724Snikos.nikoleris@arm.com } else { 60012724Snikos.nikoleris@arm.com if (limit < vaddr + req->getSize()) 60112724Snikos.nikoleris@arm.com return new GeneralProtection(0); 60212724Snikos.nikoleris@arm.com } 60312724Snikos.nikoleris@arm.com } else { 60412724Snikos.nikoleris@arm.com if (limit < base) { 60512724Snikos.nikoleris@arm.com if (vaddr <= limit || vaddr + req->getSize() >= base) 60612724Snikos.nikoleris@arm.com return new GeneralProtection(0); 60712724Snikos.nikoleris@arm.com } else { 60812724Snikos.nikoleris@arm.com if (vaddr <= limit && vaddr + req->getSize() >= base) 60912724Snikos.nikoleris@arm.com return new GeneralProtection(0); 61012724Snikos.nikoleris@arm.com } 61112724Snikos.nikoleris@arm.com } 61212724Snikos.nikoleris@arm.com } 61312724Snikos.nikoleris@arm.com // If paging is enabled, do the translation. 61412724Snikos.nikoleris@arm.com if (cr0.pg) { 61512724Snikos.nikoleris@arm.com DPRINTF(TLB, "Paging enabled.\n"); 61612724Snikos.nikoleris@arm.com // The vaddr already has the segment base applied. 61712724Snikos.nikoleris@arm.com TlbEntry *entry = lookup(vaddr); 61812724Snikos.nikoleris@arm.com if (!entry) { 61912724Snikos.nikoleris@arm.com return new TlbFault(vaddr); 62012724Snikos.nikoleris@arm.com } else { 62112724Snikos.nikoleris@arm.com // Do paging protection checks. 62212724Snikos.nikoleris@arm.com DPRINTF(TLB, "Entry found with paddr %#x, doing protection checks.\n", entry->paddr); 62312724Snikos.nikoleris@arm.com Addr paddr = entry->paddr | (vaddr & (entry->size-1)); 62412724Snikos.nikoleris@arm.com DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr); 62512724Snikos.nikoleris@arm.com req->setPaddr(paddr); 62612724Snikos.nikoleris@arm.com } 62712724Snikos.nikoleris@arm.com } else { 62812724Snikos.nikoleris@arm.com //Use the address which already has segmentation applied. 62912724Snikos.nikoleris@arm.com DPRINTF(TLB, "Paging disabled.\n"); 63012724Snikos.nikoleris@arm.com DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 63112724Snikos.nikoleris@arm.com req->setPaddr(vaddr); 63212724Snikos.nikoleris@arm.com } 63312724Snikos.nikoleris@arm.com } else { 63412724Snikos.nikoleris@arm.com // Real mode 63512724Snikos.nikoleris@arm.com DPRINTF(TLB, "In real mode.\n"); 63612724Snikos.nikoleris@arm.com DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 63712724Snikos.nikoleris@arm.com req->setPaddr(vaddr); 63812724Snikos.nikoleris@arm.com } 63912724Snikos.nikoleris@arm.com // Check for an access to the local APIC 64012724Snikos.nikoleris@arm.com#if FULL_SYSTEM 64112724Snikos.nikoleris@arm.com LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE); 64212724Snikos.nikoleris@arm.com Addr baseAddr = localApicBase.base * PageBytes; 64312724Snikos.nikoleris@arm.com Addr paddr = req->getPaddr(); 64412724Snikos.nikoleris@arm.com if (baseAddr <= paddr && baseAddr + PageBytes > paddr) { 64512724Snikos.nikoleris@arm.com // The Intel developer's manuals say the below restrictions apply, 64612724Snikos.nikoleris@arm.com // but the linux kernel, because of a compiler optimization, breaks 64712724Snikos.nikoleris@arm.com // them. 64812724Snikos.nikoleris@arm.com /* 64912724Snikos.nikoleris@arm.com // Check alignment 65012724Snikos.nikoleris@arm.com if (paddr & ((32/8) - 1)) 65112724Snikos.nikoleris@arm.com return new GeneralProtection(0); 65212724Snikos.nikoleris@arm.com // Check access size 65312724Snikos.nikoleris@arm.com if (req->getSize() != (32/8)) 65412724Snikos.nikoleris@arm.com return new GeneralProtection(0); 65512724Snikos.nikoleris@arm.com */ 65612724Snikos.nikoleris@arm.com // Force the access to be uncacheable. 65712724Snikos.nikoleris@arm.com req->setFlags(Request::UNCACHEABLE); 65812724Snikos.nikoleris@arm.com req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr)); 65912724Snikos.nikoleris@arm.com } 66012724Snikos.nikoleris@arm.com#endif 66112724Snikos.nikoleris@arm.com return NoFault; 66212724Snikos.nikoleris@arm.com}; 66312724Snikos.nikoleris@arm.com 66412724Snikos.nikoleris@arm.comFault 66512724Snikos.nikoleris@arm.comDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 66612724Snikos.nikoleris@arm.com{ 66712724Snikos.nikoleris@arm.com return TLB::translate<FakeDTLBFault>(req, tc, write, false); 66812724Snikos.nikoleris@arm.com} 66912724Snikos.nikoleris@arm.com 67012724Snikos.nikoleris@arm.comFault 67112724Snikos.nikoleris@arm.comITB::translate(RequestPtr &req, ThreadContext *tc) 67212724Snikos.nikoleris@arm.com{ 67312724Snikos.nikoleris@arm.com return TLB::translate<FakeITLBFault>(req, tc, false, true); 67412724Snikos.nikoleris@arm.com} 67512724Snikos.nikoleris@arm.com 67612724Snikos.nikoleris@arm.com#if FULL_SYSTEM 67712724Snikos.nikoleris@arm.com 67812724Snikos.nikoleris@arm.comTick 67912724Snikos.nikoleris@arm.comDTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 68012724Snikos.nikoleris@arm.com{ 68112724Snikos.nikoleris@arm.com return tc->getCpuPtr()->ticks(1); 68212724Snikos.nikoleris@arm.com} 68312724Snikos.nikoleris@arm.com 68412724Snikos.nikoleris@arm.comTick 68512724Snikos.nikoleris@arm.comDTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 68612724Snikos.nikoleris@arm.com{ 68712724Snikos.nikoleris@arm.com return tc->getCpuPtr()->ticks(1); 68812724Snikos.nikoleris@arm.com} 68912724Snikos.nikoleris@arm.com 69012724Snikos.nikoleris@arm.com#endif 69112724Snikos.nikoleris@arm.com 69212724Snikos.nikoleris@arm.comvoid 69312724Snikos.nikoleris@arm.comTLB::serialize(std::ostream &os) 69412724Snikos.nikoleris@arm.com{ 69512724Snikos.nikoleris@arm.com} 69612724Snikos.nikoleris@arm.com 69712724Snikos.nikoleris@arm.comvoid 69812724Snikos.nikoleris@arm.comTLB::unserialize(Checkpoint *cp, const std::string §ion) 69912724Snikos.nikoleris@arm.com{ 70012724Snikos.nikoleris@arm.com} 70112724Snikos.nikoleris@arm.com 70212724Snikos.nikoleris@arm.comvoid 70312724Snikos.nikoleris@arm.comDTB::serialize(std::ostream &os) 70412724Snikos.nikoleris@arm.com{ 70512724Snikos.nikoleris@arm.com TLB::serialize(os); 70612724Snikos.nikoleris@arm.com} 70711197Sandreas.hansson@arm.com 70811197Sandreas.hansson@arm.comvoid 7099347SAndreas.Sandberg@arm.comDTB::unserialize(Checkpoint *cp, const std::string §ion) 7109347SAndreas.Sandberg@arm.com{ 71112724Snikos.nikoleris@arm.com TLB::unserialize(cp, section); 71212724Snikos.nikoleris@arm.com} 7139347SAndreas.Sandberg@arm.com 7149347SAndreas.Sandberg@arm.com/* end namespace X86ISA */ } 7159347SAndreas.Sandberg@arm.com 7169347SAndreas.Sandberg@arm.comX86ISA::ITB * 7179347SAndreas.Sandberg@arm.comX86ITBParams::create() 7189347SAndreas.Sandberg@arm.com{ 7199347SAndreas.Sandberg@arm.com return new X86ISA::ITB(this); 72012724Snikos.nikoleris@arm.com} 72112724Snikos.nikoleris@arm.com 7229347SAndreas.Sandberg@arm.comX86ISA::DTB * 7239347SAndreas.Sandberg@arm.comX86DTBParams::create() 7249347SAndreas.Sandberg@arm.com{ 72512724Snikos.nikoleris@arm.com return new X86ISA::DTB(this); 7269347SAndreas.Sandberg@arm.com} 72712724Snikos.nikoleris@arm.com