tlb.cc revision 5418
14997Sgblack@eecs.umich.edu/* 25417Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 34997Sgblack@eecs.umich.edu * All rights reserved. 44997Sgblack@eecs.umich.edu * 54997Sgblack@eecs.umich.edu * Redistribution and use of this software in source and binary forms, 64997Sgblack@eecs.umich.edu * with or without modification, are permitted provided that the 74997Sgblack@eecs.umich.edu * following conditions are met: 84997Sgblack@eecs.umich.edu * 94997Sgblack@eecs.umich.edu * The software must be used only for Non-Commercial Use which means any 104997Sgblack@eecs.umich.edu * use which is NOT directed to receiving any direct monetary 114997Sgblack@eecs.umich.edu * compensation for, or commercial advantage from such use. Illustrative 124997Sgblack@eecs.umich.edu * examples of non-commercial use are academic research, personal study, 134997Sgblack@eecs.umich.edu * teaching, education and corporate research & development. 144997Sgblack@eecs.umich.edu * Illustrative examples of commercial use are distributing products for 154997Sgblack@eecs.umich.edu * commercial advantage and providing services using the software for 164997Sgblack@eecs.umich.edu * commercial advantage. 174997Sgblack@eecs.umich.edu * 184997Sgblack@eecs.umich.edu * If you wish to use this software or functionality therein that may be 194997Sgblack@eecs.umich.edu * covered by patents for commercial use, please contact: 204997Sgblack@eecs.umich.edu * Director of Intellectual Property Licensing 214997Sgblack@eecs.umich.edu * Office of Strategy and Technology 224997Sgblack@eecs.umich.edu * Hewlett-Packard Company 234997Sgblack@eecs.umich.edu * 1501 Page Mill Road 244997Sgblack@eecs.umich.edu * Palo Alto, California 94304 254997Sgblack@eecs.umich.edu * 264997Sgblack@eecs.umich.edu * Redistributions of source code must retain the above copyright notice, 274997Sgblack@eecs.umich.edu * this list of conditions and the following disclaimer. Redistributions 284997Sgblack@eecs.umich.edu * in binary form must reproduce the above copyright notice, this list of 294997Sgblack@eecs.umich.edu * conditions and the following disclaimer in the documentation and/or 304997Sgblack@eecs.umich.edu * other materials provided with the distribution. Neither the name of 314997Sgblack@eecs.umich.edu * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 324997Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 334997Sgblack@eecs.umich.edu * this software without specific prior written permission. No right of 344997Sgblack@eecs.umich.edu * sublicense is granted herewith. Derivatives of the software and 354997Sgblack@eecs.umich.edu * output created using the software may be prepared, but only for 364997Sgblack@eecs.umich.edu * Non-Commercial Uses. Derivatives of the software may be shared with 374997Sgblack@eecs.umich.edu * others provided: (i) the others agree to abide by the list of 384997Sgblack@eecs.umich.edu * conditions herein which includes the Non-Commercial Use restrictions; 394997Sgblack@eecs.umich.edu * and (ii) such Derivatives of the software include the above copyright 404997Sgblack@eecs.umich.edu * notice to acknowledge the contribution from this software where 414997Sgblack@eecs.umich.edu * applicable, this list of conditions and the disclaimer below. 424997Sgblack@eecs.umich.edu * 434997Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 444997Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 454997Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 464997Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 474997Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 484997Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 494997Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 504997Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 514997Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 524997Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 534997Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 544997Sgblack@eecs.umich.edu * 554997Sgblack@eecs.umich.edu * Authors: Gabe Black 564997Sgblack@eecs.umich.edu */ 574997Sgblack@eecs.umich.edu 584997Sgblack@eecs.umich.edu#include <cstring> 594997Sgblack@eecs.umich.edu 605086Sgblack@eecs.umich.edu#include "config/full_system.hh" 615086Sgblack@eecs.umich.edu 625124Sgblack@eecs.umich.edu#include "arch/x86/pagetable.hh" 635086Sgblack@eecs.umich.edu#include "arch/x86/tlb.hh" 645149Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh" 655086Sgblack@eecs.umich.edu#include "base/bitfield.hh" 665086Sgblack@eecs.umich.edu#include "base/trace.hh" 675237Sgblack@eecs.umich.edu#include "config/full_system.hh" 685086Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 695086Sgblack@eecs.umich.edu#include "cpu/base.hh" 705086Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 715086Sgblack@eecs.umich.edu#include "mem/request.hh" 725245Sgblack@eecs.umich.edu 735245Sgblack@eecs.umich.edu#if FULL_SYSTEM 745245Sgblack@eecs.umich.edu#include "arch/x86/pagetable_walker.hh" 755245Sgblack@eecs.umich.edu#endif 765086Sgblack@eecs.umich.edu 775086Sgblack@eecs.umich.edunamespace X86ISA { 785086Sgblack@eecs.umich.edu 795358Sgblack@eecs.umich.eduTLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size) 805124Sgblack@eecs.umich.edu{ 815124Sgblack@eecs.umich.edu tlb = new TlbEntry[size]; 825124Sgblack@eecs.umich.edu std::memset(tlb, 0, sizeof(TlbEntry) * size); 835124Sgblack@eecs.umich.edu 845124Sgblack@eecs.umich.edu for (int x = 0; x < size; x++) 855124Sgblack@eecs.umich.edu freeList.push_back(&tlb[x]); 865124Sgblack@eecs.umich.edu 875237Sgblack@eecs.umich.edu#if FULL_SYSTEM 885245Sgblack@eecs.umich.edu walker = p->walker; 895245Sgblack@eecs.umich.edu walker->setTLB(this); 905245Sgblack@eecs.umich.edu#endif 915236Sgblack@eecs.umich.edu} 925236Sgblack@eecs.umich.edu 935236Sgblack@eecs.umich.eduvoid 945124Sgblack@eecs.umich.eduTLB::insert(Addr vpn, TlbEntry &entry) 955124Sgblack@eecs.umich.edu{ 965124Sgblack@eecs.umich.edu //TODO Deal with conflicting entries 975124Sgblack@eecs.umich.edu 985124Sgblack@eecs.umich.edu TlbEntry *newEntry = NULL; 995124Sgblack@eecs.umich.edu if (!freeList.empty()) { 1005124Sgblack@eecs.umich.edu newEntry = freeList.front(); 1015124Sgblack@eecs.umich.edu freeList.pop_front(); 1025124Sgblack@eecs.umich.edu } else { 1035124Sgblack@eecs.umich.edu newEntry = entryList.back(); 1045124Sgblack@eecs.umich.edu entryList.pop_back(); 1055124Sgblack@eecs.umich.edu } 1065124Sgblack@eecs.umich.edu *newEntry = entry; 1075124Sgblack@eecs.umich.edu newEntry->vaddr = vpn; 1085124Sgblack@eecs.umich.edu entryList.push_front(newEntry); 1095124Sgblack@eecs.umich.edu} 1105124Sgblack@eecs.umich.edu 1115360Sgblack@eecs.umich.eduTLB::EntryList::iterator 1125360Sgblack@eecs.umich.eduTLB::lookupIt(Addr va, bool update_lru) 1135124Sgblack@eecs.umich.edu{ 1145124Sgblack@eecs.umich.edu //TODO make this smarter at some point 1155124Sgblack@eecs.umich.edu EntryList::iterator entry; 1165124Sgblack@eecs.umich.edu for (entry = entryList.begin(); entry != entryList.end(); entry++) { 1175124Sgblack@eecs.umich.edu if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) { 1185124Sgblack@eecs.umich.edu DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x " 1195124Sgblack@eecs.umich.edu "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size); 1205124Sgblack@eecs.umich.edu if (update_lru) { 1215360Sgblack@eecs.umich.edu entryList.push_front(*entry); 1225124Sgblack@eecs.umich.edu entryList.erase(entry); 1235360Sgblack@eecs.umich.edu entry = entryList.begin(); 1245124Sgblack@eecs.umich.edu } 1255360Sgblack@eecs.umich.edu break; 1265124Sgblack@eecs.umich.edu } 1275124Sgblack@eecs.umich.edu } 1285360Sgblack@eecs.umich.edu return entry; 1295360Sgblack@eecs.umich.edu} 1305360Sgblack@eecs.umich.edu 1315360Sgblack@eecs.umich.eduTlbEntry * 1325360Sgblack@eecs.umich.eduTLB::lookup(Addr va, bool update_lru) 1335360Sgblack@eecs.umich.edu{ 1345360Sgblack@eecs.umich.edu EntryList::iterator entry = lookupIt(va, update_lru); 1355360Sgblack@eecs.umich.edu if (entry == entryList.end()) 1365360Sgblack@eecs.umich.edu return NULL; 1375360Sgblack@eecs.umich.edu else 1385360Sgblack@eecs.umich.edu return *entry; 1395124Sgblack@eecs.umich.edu} 1405124Sgblack@eecs.umich.edu 1415245Sgblack@eecs.umich.edu#if FULL_SYSTEM 1425245Sgblack@eecs.umich.eduvoid 1435245Sgblack@eecs.umich.eduTLB::walk(ThreadContext * _tc, Addr vaddr) 1445245Sgblack@eecs.umich.edu{ 1455245Sgblack@eecs.umich.edu walker->start(_tc, vaddr); 1465245Sgblack@eecs.umich.edu} 1475245Sgblack@eecs.umich.edu#endif 1485245Sgblack@eecs.umich.edu 1495124Sgblack@eecs.umich.eduvoid 1505124Sgblack@eecs.umich.eduTLB::invalidateAll() 1515124Sgblack@eecs.umich.edu{ 1525242Sgblack@eecs.umich.edu DPRINTF(TLB, "Invalidating all entries.\n"); 1535242Sgblack@eecs.umich.edu while (!entryList.empty()) { 1545242Sgblack@eecs.umich.edu TlbEntry *entry = entryList.front(); 1555242Sgblack@eecs.umich.edu entryList.pop_front(); 1565242Sgblack@eecs.umich.edu freeList.push_back(entry); 1575242Sgblack@eecs.umich.edu } 1585124Sgblack@eecs.umich.edu} 1595124Sgblack@eecs.umich.edu 1605124Sgblack@eecs.umich.eduvoid 1615357Sgblack@eecs.umich.eduTLB::setConfigAddress(uint32_t addr) 1625357Sgblack@eecs.umich.edu{ 1635357Sgblack@eecs.umich.edu configAddress = addr; 1645357Sgblack@eecs.umich.edu} 1655357Sgblack@eecs.umich.edu 1665357Sgblack@eecs.umich.eduvoid 1675124Sgblack@eecs.umich.eduTLB::invalidateNonGlobal() 1685124Sgblack@eecs.umich.edu{ 1695242Sgblack@eecs.umich.edu DPRINTF(TLB, "Invalidating all non global entries.\n"); 1705242Sgblack@eecs.umich.edu EntryList::iterator entryIt; 1715242Sgblack@eecs.umich.edu for (entryIt = entryList.begin(); entryIt != entryList.end();) { 1725242Sgblack@eecs.umich.edu if (!(*entryIt)->global) { 1735242Sgblack@eecs.umich.edu freeList.push_back(*entryIt); 1745242Sgblack@eecs.umich.edu entryList.erase(entryIt++); 1755242Sgblack@eecs.umich.edu } else { 1765242Sgblack@eecs.umich.edu entryIt++; 1775242Sgblack@eecs.umich.edu } 1785242Sgblack@eecs.umich.edu } 1795124Sgblack@eecs.umich.edu} 1805124Sgblack@eecs.umich.edu 1815124Sgblack@eecs.umich.eduvoid 1825358Sgblack@eecs.umich.eduTLB::demapPage(Addr va, uint64_t asn) 1835086Sgblack@eecs.umich.edu{ 1845359Sgblack@eecs.umich.edu EntryList::iterator entry = lookupIt(va, false); 1855359Sgblack@eecs.umich.edu if (entry != entryList.end()) { 1865359Sgblack@eecs.umich.edu freeList.push_back(*entry); 1875359Sgblack@eecs.umich.edu entryList.erase(entry); 1885359Sgblack@eecs.umich.edu } 1895086Sgblack@eecs.umich.edu} 1905086Sgblack@eecs.umich.edu 1915140Sgblack@eecs.umich.edutemplate<class TlbFault> 1925086Sgblack@eecs.umich.eduFault 1935140Sgblack@eecs.umich.eduTLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute) 1945086Sgblack@eecs.umich.edu{ 1955124Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr(); 1965140Sgblack@eecs.umich.edu DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr); 1975124Sgblack@eecs.umich.edu uint32_t flags = req->getFlags(); 1985124Sgblack@eecs.umich.edu bool storeCheck = flags & StoreCheck; 1995140Sgblack@eecs.umich.edu 2005294Sgblack@eecs.umich.edu int seg = flags & mask(4); 2015124Sgblack@eecs.umich.edu 2025124Sgblack@eecs.umich.edu //XXX Junk code to surpress the warning 2035149Sgblack@eecs.umich.edu if (storeCheck); 2045149Sgblack@eecs.umich.edu 2055149Sgblack@eecs.umich.edu // If this is true, we're dealing with a request to read an internal 2065149Sgblack@eecs.umich.edu // value. 2075294Sgblack@eecs.umich.edu if (seg == SEGMENT_REG_MS) { 2085243Sgblack@eecs.umich.edu DPRINTF(TLB, "Addresses references internal memory.\n"); 2095418Sgblack@eecs.umich.edu Addr prefix = (vaddr >> 3) & IntAddrPrefixMask; 2105149Sgblack@eecs.umich.edu if (prefix == IntAddrPrefixCPUID) { 2115149Sgblack@eecs.umich.edu panic("CPUID memory space not yet implemented!\n"); 2125149Sgblack@eecs.umich.edu } else if (prefix == IntAddrPrefixMSR) { 2135418Sgblack@eecs.umich.edu vaddr = vaddr >> 3; 2145149Sgblack@eecs.umich.edu req->setMmapedIpr(true); 2155149Sgblack@eecs.umich.edu Addr regNum = 0; 2165149Sgblack@eecs.umich.edu switch (vaddr & ~IntAddrPrefixMask) { 2175149Sgblack@eecs.umich.edu case 0x10: 2185149Sgblack@eecs.umich.edu regNum = MISCREG_TSC; 2195149Sgblack@eecs.umich.edu break; 2205360Sgblack@eecs.umich.edu case 0x1B: 2215360Sgblack@eecs.umich.edu regNum = MISCREG_APIC_BASE; 2225360Sgblack@eecs.umich.edu break; 2235149Sgblack@eecs.umich.edu case 0xFE: 2245149Sgblack@eecs.umich.edu regNum = MISCREG_MTRRCAP; 2255149Sgblack@eecs.umich.edu break; 2265149Sgblack@eecs.umich.edu case 0x174: 2275149Sgblack@eecs.umich.edu regNum = MISCREG_SYSENTER_CS; 2285149Sgblack@eecs.umich.edu break; 2295149Sgblack@eecs.umich.edu case 0x175: 2305149Sgblack@eecs.umich.edu regNum = MISCREG_SYSENTER_ESP; 2315149Sgblack@eecs.umich.edu break; 2325149Sgblack@eecs.umich.edu case 0x176: 2335149Sgblack@eecs.umich.edu regNum = MISCREG_SYSENTER_EIP; 2345149Sgblack@eecs.umich.edu break; 2355149Sgblack@eecs.umich.edu case 0x179: 2365149Sgblack@eecs.umich.edu regNum = MISCREG_MCG_CAP; 2375149Sgblack@eecs.umich.edu break; 2385149Sgblack@eecs.umich.edu case 0x17A: 2395149Sgblack@eecs.umich.edu regNum = MISCREG_MCG_STATUS; 2405149Sgblack@eecs.umich.edu break; 2415149Sgblack@eecs.umich.edu case 0x17B: 2425149Sgblack@eecs.umich.edu regNum = MISCREG_MCG_CTL; 2435149Sgblack@eecs.umich.edu break; 2445149Sgblack@eecs.umich.edu case 0x1D9: 2455149Sgblack@eecs.umich.edu regNum = MISCREG_DEBUG_CTL_MSR; 2465149Sgblack@eecs.umich.edu break; 2475149Sgblack@eecs.umich.edu case 0x1DB: 2485149Sgblack@eecs.umich.edu regNum = MISCREG_LAST_BRANCH_FROM_IP; 2495149Sgblack@eecs.umich.edu break; 2505149Sgblack@eecs.umich.edu case 0x1DC: 2515149Sgblack@eecs.umich.edu regNum = MISCREG_LAST_BRANCH_TO_IP; 2525149Sgblack@eecs.umich.edu break; 2535149Sgblack@eecs.umich.edu case 0x1DD: 2545149Sgblack@eecs.umich.edu regNum = MISCREG_LAST_EXCEPTION_FROM_IP; 2555149Sgblack@eecs.umich.edu break; 2565149Sgblack@eecs.umich.edu case 0x1DE: 2575149Sgblack@eecs.umich.edu regNum = MISCREG_LAST_EXCEPTION_TO_IP; 2585149Sgblack@eecs.umich.edu break; 2595149Sgblack@eecs.umich.edu case 0x200: 2605149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_0; 2615149Sgblack@eecs.umich.edu break; 2625149Sgblack@eecs.umich.edu case 0x201: 2635149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_0; 2645149Sgblack@eecs.umich.edu break; 2655149Sgblack@eecs.umich.edu case 0x202: 2665149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_1; 2675149Sgblack@eecs.umich.edu break; 2685149Sgblack@eecs.umich.edu case 0x203: 2695149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_1; 2705149Sgblack@eecs.umich.edu break; 2715149Sgblack@eecs.umich.edu case 0x204: 2725149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_2; 2735149Sgblack@eecs.umich.edu break; 2745149Sgblack@eecs.umich.edu case 0x205: 2755149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_2; 2765149Sgblack@eecs.umich.edu break; 2775149Sgblack@eecs.umich.edu case 0x206: 2785149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_3; 2795149Sgblack@eecs.umich.edu break; 2805149Sgblack@eecs.umich.edu case 0x207: 2815149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_3; 2825149Sgblack@eecs.umich.edu break; 2835149Sgblack@eecs.umich.edu case 0x208: 2845149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_4; 2855149Sgblack@eecs.umich.edu break; 2865149Sgblack@eecs.umich.edu case 0x209: 2875149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_4; 2885149Sgblack@eecs.umich.edu break; 2895149Sgblack@eecs.umich.edu case 0x20A: 2905149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_5; 2915149Sgblack@eecs.umich.edu break; 2925149Sgblack@eecs.umich.edu case 0x20B: 2935149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_5; 2945149Sgblack@eecs.umich.edu break; 2955149Sgblack@eecs.umich.edu case 0x20C: 2965149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_6; 2975149Sgblack@eecs.umich.edu break; 2985149Sgblack@eecs.umich.edu case 0x20D: 2995149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_6; 3005149Sgblack@eecs.umich.edu break; 3015149Sgblack@eecs.umich.edu case 0x20E: 3025149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_BASE_7; 3035149Sgblack@eecs.umich.edu break; 3045149Sgblack@eecs.umich.edu case 0x20F: 3055149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_PHYS_MASK_7; 3065149Sgblack@eecs.umich.edu break; 3075149Sgblack@eecs.umich.edu case 0x250: 3085149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_64K_00000; 3095149Sgblack@eecs.umich.edu break; 3105149Sgblack@eecs.umich.edu case 0x258: 3115149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_16K_80000; 3125149Sgblack@eecs.umich.edu break; 3135149Sgblack@eecs.umich.edu case 0x259: 3145149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_16K_A0000; 3155149Sgblack@eecs.umich.edu break; 3165149Sgblack@eecs.umich.edu case 0x268: 3175149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_C0000; 3185149Sgblack@eecs.umich.edu break; 3195149Sgblack@eecs.umich.edu case 0x269: 3205149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_C8000; 3215149Sgblack@eecs.umich.edu break; 3225149Sgblack@eecs.umich.edu case 0x26A: 3235149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_D0000; 3245149Sgblack@eecs.umich.edu break; 3255149Sgblack@eecs.umich.edu case 0x26B: 3265149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_D8000; 3275149Sgblack@eecs.umich.edu break; 3285149Sgblack@eecs.umich.edu case 0x26C: 3295149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_E0000; 3305149Sgblack@eecs.umich.edu break; 3315149Sgblack@eecs.umich.edu case 0x26D: 3325149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_E8000; 3335149Sgblack@eecs.umich.edu break; 3345149Sgblack@eecs.umich.edu case 0x26E: 3355149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_F0000; 3365149Sgblack@eecs.umich.edu break; 3375149Sgblack@eecs.umich.edu case 0x26F: 3385149Sgblack@eecs.umich.edu regNum = MISCREG_MTRR_FIX_4K_F8000; 3395149Sgblack@eecs.umich.edu break; 3405149Sgblack@eecs.umich.edu case 0x277: 3415149Sgblack@eecs.umich.edu regNum = MISCREG_PAT; 3425149Sgblack@eecs.umich.edu break; 3435149Sgblack@eecs.umich.edu case 0x2FF: 3445149Sgblack@eecs.umich.edu regNum = MISCREG_DEF_TYPE; 3455149Sgblack@eecs.umich.edu break; 3465149Sgblack@eecs.umich.edu case 0x400: 3475149Sgblack@eecs.umich.edu regNum = MISCREG_MC0_CTL; 3485149Sgblack@eecs.umich.edu break; 3495149Sgblack@eecs.umich.edu case 0x404: 3505149Sgblack@eecs.umich.edu regNum = MISCREG_MC1_CTL; 3515149Sgblack@eecs.umich.edu break; 3525149Sgblack@eecs.umich.edu case 0x408: 3535149Sgblack@eecs.umich.edu regNum = MISCREG_MC2_CTL; 3545149Sgblack@eecs.umich.edu break; 3555149Sgblack@eecs.umich.edu case 0x40C: 3565149Sgblack@eecs.umich.edu regNum = MISCREG_MC3_CTL; 3575149Sgblack@eecs.umich.edu break; 3585149Sgblack@eecs.umich.edu case 0x410: 3595149Sgblack@eecs.umich.edu regNum = MISCREG_MC4_CTL; 3605149Sgblack@eecs.umich.edu break; 3615149Sgblack@eecs.umich.edu case 0x401: 3625149Sgblack@eecs.umich.edu regNum = MISCREG_MC0_STATUS; 3635149Sgblack@eecs.umich.edu break; 3645149Sgblack@eecs.umich.edu case 0x405: 3655149Sgblack@eecs.umich.edu regNum = MISCREG_MC1_STATUS; 3665149Sgblack@eecs.umich.edu break; 3675149Sgblack@eecs.umich.edu case 0x409: 3685149Sgblack@eecs.umich.edu regNum = MISCREG_MC2_STATUS; 3695149Sgblack@eecs.umich.edu break; 3705149Sgblack@eecs.umich.edu case 0x40D: 3715149Sgblack@eecs.umich.edu regNum = MISCREG_MC3_STATUS; 3725149Sgblack@eecs.umich.edu break; 3735149Sgblack@eecs.umich.edu case 0x411: 3745149Sgblack@eecs.umich.edu regNum = MISCREG_MC4_STATUS; 3755149Sgblack@eecs.umich.edu break; 3765149Sgblack@eecs.umich.edu case 0x402: 3775149Sgblack@eecs.umich.edu regNum = MISCREG_MC0_ADDR; 3785149Sgblack@eecs.umich.edu break; 3795149Sgblack@eecs.umich.edu case 0x406: 3805149Sgblack@eecs.umich.edu regNum = MISCREG_MC1_ADDR; 3815149Sgblack@eecs.umich.edu break; 3825149Sgblack@eecs.umich.edu case 0x40A: 3835149Sgblack@eecs.umich.edu regNum = MISCREG_MC2_ADDR; 3845149Sgblack@eecs.umich.edu break; 3855149Sgblack@eecs.umich.edu case 0x40E: 3865149Sgblack@eecs.umich.edu regNum = MISCREG_MC3_ADDR; 3875149Sgblack@eecs.umich.edu break; 3885149Sgblack@eecs.umich.edu case 0x412: 3895149Sgblack@eecs.umich.edu regNum = MISCREG_MC4_ADDR; 3905149Sgblack@eecs.umich.edu break; 3915149Sgblack@eecs.umich.edu case 0x403: 3925149Sgblack@eecs.umich.edu regNum = MISCREG_MC0_MISC; 3935149Sgblack@eecs.umich.edu break; 3945149Sgblack@eecs.umich.edu case 0x407: 3955149Sgblack@eecs.umich.edu regNum = MISCREG_MC1_MISC; 3965149Sgblack@eecs.umich.edu break; 3975149Sgblack@eecs.umich.edu case 0x40B: 3985149Sgblack@eecs.umich.edu regNum = MISCREG_MC2_MISC; 3995149Sgblack@eecs.umich.edu break; 4005149Sgblack@eecs.umich.edu case 0x40F: 4015149Sgblack@eecs.umich.edu regNum = MISCREG_MC3_MISC; 4025149Sgblack@eecs.umich.edu break; 4035149Sgblack@eecs.umich.edu case 0x413: 4045149Sgblack@eecs.umich.edu regNum = MISCREG_MC4_MISC; 4055149Sgblack@eecs.umich.edu break; 4065149Sgblack@eecs.umich.edu case 0xC0000080: 4075149Sgblack@eecs.umich.edu regNum = MISCREG_EFER; 4085149Sgblack@eecs.umich.edu break; 4095149Sgblack@eecs.umich.edu case 0xC0000081: 4105149Sgblack@eecs.umich.edu regNum = MISCREG_STAR; 4115149Sgblack@eecs.umich.edu break; 4125149Sgblack@eecs.umich.edu case 0xC0000082: 4135149Sgblack@eecs.umich.edu regNum = MISCREG_LSTAR; 4145149Sgblack@eecs.umich.edu break; 4155149Sgblack@eecs.umich.edu case 0xC0000083: 4165149Sgblack@eecs.umich.edu regNum = MISCREG_CSTAR; 4175149Sgblack@eecs.umich.edu break; 4185149Sgblack@eecs.umich.edu case 0xC0000084: 4195149Sgblack@eecs.umich.edu regNum = MISCREG_SF_MASK; 4205149Sgblack@eecs.umich.edu break; 4215149Sgblack@eecs.umich.edu case 0xC0000100: 4225149Sgblack@eecs.umich.edu regNum = MISCREG_FS_BASE; 4235149Sgblack@eecs.umich.edu break; 4245149Sgblack@eecs.umich.edu case 0xC0000101: 4255149Sgblack@eecs.umich.edu regNum = MISCREG_GS_BASE; 4265149Sgblack@eecs.umich.edu break; 4275149Sgblack@eecs.umich.edu case 0xC0000102: 4285149Sgblack@eecs.umich.edu regNum = MISCREG_KERNEL_GS_BASE; 4295149Sgblack@eecs.umich.edu break; 4305149Sgblack@eecs.umich.edu case 0xC0000103: 4315149Sgblack@eecs.umich.edu regNum = MISCREG_TSC_AUX; 4325149Sgblack@eecs.umich.edu break; 4335149Sgblack@eecs.umich.edu case 0xC0010000: 4345149Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_SEL0; 4355149Sgblack@eecs.umich.edu break; 4365149Sgblack@eecs.umich.edu case 0xC0010001: 4375149Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_SEL1; 4385149Sgblack@eecs.umich.edu break; 4395149Sgblack@eecs.umich.edu case 0xC0010002: 4405149Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_SEL2; 4415149Sgblack@eecs.umich.edu break; 4425149Sgblack@eecs.umich.edu case 0xC0010003: 4435149Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_SEL3; 4445149Sgblack@eecs.umich.edu break; 4455149Sgblack@eecs.umich.edu case 0xC0010004: 4465149Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_CTR0; 4475149Sgblack@eecs.umich.edu break; 4485149Sgblack@eecs.umich.edu case 0xC0010005: 4495149Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_CTR1; 4505149Sgblack@eecs.umich.edu break; 4515149Sgblack@eecs.umich.edu case 0xC0010006: 4525149Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_CTR2; 4535149Sgblack@eecs.umich.edu break; 4545149Sgblack@eecs.umich.edu case 0xC0010007: 4555149Sgblack@eecs.umich.edu regNum = MISCREG_PERF_EVT_CTR3; 4565149Sgblack@eecs.umich.edu break; 4575149Sgblack@eecs.umich.edu case 0xC0010010: 4585149Sgblack@eecs.umich.edu regNum = MISCREG_SYSCFG; 4595149Sgblack@eecs.umich.edu break; 4605149Sgblack@eecs.umich.edu case 0xC0010016: 4615149Sgblack@eecs.umich.edu regNum = MISCREG_IORR_BASE0; 4625149Sgblack@eecs.umich.edu break; 4635149Sgblack@eecs.umich.edu case 0xC0010017: 4645149Sgblack@eecs.umich.edu regNum = MISCREG_IORR_BASE1; 4655149Sgblack@eecs.umich.edu break; 4665149Sgblack@eecs.umich.edu case 0xC0010018: 4675149Sgblack@eecs.umich.edu regNum = MISCREG_IORR_MASK0; 4685149Sgblack@eecs.umich.edu break; 4695149Sgblack@eecs.umich.edu case 0xC0010019: 4705149Sgblack@eecs.umich.edu regNum = MISCREG_IORR_MASK1; 4715149Sgblack@eecs.umich.edu break; 4725149Sgblack@eecs.umich.edu case 0xC001001A: 4735149Sgblack@eecs.umich.edu regNum = MISCREG_TOP_MEM; 4745149Sgblack@eecs.umich.edu break; 4755149Sgblack@eecs.umich.edu case 0xC001001D: 4765149Sgblack@eecs.umich.edu regNum = MISCREG_TOP_MEM2; 4775149Sgblack@eecs.umich.edu break; 4785149Sgblack@eecs.umich.edu case 0xC0010114: 4795149Sgblack@eecs.umich.edu regNum = MISCREG_VM_CR; 4805149Sgblack@eecs.umich.edu break; 4815149Sgblack@eecs.umich.edu case 0xC0010115: 4825149Sgblack@eecs.umich.edu regNum = MISCREG_IGNNE; 4835149Sgblack@eecs.umich.edu break; 4845149Sgblack@eecs.umich.edu case 0xC0010116: 4855149Sgblack@eecs.umich.edu regNum = MISCREG_SMM_CTL; 4865149Sgblack@eecs.umich.edu break; 4875149Sgblack@eecs.umich.edu case 0xC0010117: 4885149Sgblack@eecs.umich.edu regNum = MISCREG_VM_HSAVE_PA; 4895149Sgblack@eecs.umich.edu break; 4905149Sgblack@eecs.umich.edu default: 4915149Sgblack@eecs.umich.edu return new GeneralProtection(0); 4925149Sgblack@eecs.umich.edu } 4935149Sgblack@eecs.umich.edu //The index is multiplied by the size of a MiscReg so that 4945149Sgblack@eecs.umich.edu //any memory dependence calculations will not see these as 4955149Sgblack@eecs.umich.edu //overlapping. 4965149Sgblack@eecs.umich.edu req->setPaddr(regNum * sizeof(MiscReg)); 4975149Sgblack@eecs.umich.edu return NoFault; 4985323Sgblack@eecs.umich.edu } else if (prefix == IntAddrPrefixIO) { 4995323Sgblack@eecs.umich.edu // TODO If CPL > IOPL or in virtual mode, check the I/O permission 5005323Sgblack@eecs.umich.edu // bitmap in the TSS. 5015323Sgblack@eecs.umich.edu 5025323Sgblack@eecs.umich.edu Addr IOPort = vaddr & ~IntAddrPrefixMask; 5035323Sgblack@eecs.umich.edu // Make sure the address fits in the expected 16 bit IO address 5045323Sgblack@eecs.umich.edu // space. 5055323Sgblack@eecs.umich.edu assert(!(IOPort & ~0xFFFF)); 5065357Sgblack@eecs.umich.edu if (IOPort == 0xCF8 && req->getSize() == 4) { 5075357Sgblack@eecs.umich.edu req->setMmapedIpr(true); 5085357Sgblack@eecs.umich.edu req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg)); 5095357Sgblack@eecs.umich.edu } else if ((IOPort & ~mask(2)) == 0xCFC) { 5105357Sgblack@eecs.umich.edu Addr configAddress = 5115357Sgblack@eecs.umich.edu tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS); 5125357Sgblack@eecs.umich.edu if (bits(configAddress, 31, 31)) { 5135357Sgblack@eecs.umich.edu req->setPaddr(PhysAddrPrefixPciConfig | 5145357Sgblack@eecs.umich.edu bits(configAddress, 30, 0)); 5155357Sgblack@eecs.umich.edu } 5165357Sgblack@eecs.umich.edu } else { 5175357Sgblack@eecs.umich.edu req->setPaddr(PhysAddrPrefixIO | IOPort); 5185357Sgblack@eecs.umich.edu } 5195323Sgblack@eecs.umich.edu return NoFault; 5205149Sgblack@eecs.umich.edu } else { 5215149Sgblack@eecs.umich.edu panic("Access to unrecognized internal address space %#x.\n", 5225149Sgblack@eecs.umich.edu prefix); 5235149Sgblack@eecs.umich.edu } 5245149Sgblack@eecs.umich.edu } 5255124Sgblack@eecs.umich.edu 5265140Sgblack@eecs.umich.edu // Get cr0. This will tell us how to do translation. We'll assume it was 5275140Sgblack@eecs.umich.edu // verified to be correct and consistent when set. 5285140Sgblack@eecs.umich.edu CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 5295140Sgblack@eecs.umich.edu 5305140Sgblack@eecs.umich.edu // If protected mode has been enabled... 5315140Sgblack@eecs.umich.edu if (cr0.pe) { 5325237Sgblack@eecs.umich.edu DPRINTF(TLB, "In protected mode.\n"); 5335140Sgblack@eecs.umich.edu Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER); 5345140Sgblack@eecs.umich.edu SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR); 5355140Sgblack@eecs.umich.edu // If we're not in 64-bit mode, do protection/limit checks 5365140Sgblack@eecs.umich.edu if (!efer.lma || !csAttr.longMode) { 5375237Sgblack@eecs.umich.edu DPRINTF(TLB, "Not in long mode. Checking segment protection.\n"); 5385140Sgblack@eecs.umich.edu SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg)); 5395140Sgblack@eecs.umich.edu if (!attr.writable && write) 5405140Sgblack@eecs.umich.edu return new GeneralProtection(0); 5415140Sgblack@eecs.umich.edu if (!attr.readable && !write && !execute) 5425140Sgblack@eecs.umich.edu return new GeneralProtection(0); 5435140Sgblack@eecs.umich.edu Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg)); 5445140Sgblack@eecs.umich.edu Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg)); 5455140Sgblack@eecs.umich.edu if (!attr.expandDown) { 5465237Sgblack@eecs.umich.edu DPRINTF(TLB, "Checking an expand down segment.\n"); 5475140Sgblack@eecs.umich.edu // We don't have to worry about the access going around the 5485140Sgblack@eecs.umich.edu // end of memory because accesses will be broken up into 5495140Sgblack@eecs.umich.edu // pieces at boundaries aligned on sizes smaller than an 5505140Sgblack@eecs.umich.edu // entire address space. We do have to worry about the limit 5515140Sgblack@eecs.umich.edu // being less than the base. 5525140Sgblack@eecs.umich.edu if (limit < base) { 5535140Sgblack@eecs.umich.edu if (limit < vaddr + req->getSize() && vaddr < base) 5545140Sgblack@eecs.umich.edu return new GeneralProtection(0); 5555140Sgblack@eecs.umich.edu } else { 5565140Sgblack@eecs.umich.edu if (limit < vaddr + req->getSize()) 5575140Sgblack@eecs.umich.edu return new GeneralProtection(0); 5585140Sgblack@eecs.umich.edu } 5595140Sgblack@eecs.umich.edu } else { 5605140Sgblack@eecs.umich.edu if (limit < base) { 5615140Sgblack@eecs.umich.edu if (vaddr <= limit || vaddr + req->getSize() >= base) 5625140Sgblack@eecs.umich.edu return new GeneralProtection(0); 5635140Sgblack@eecs.umich.edu } else { 5645140Sgblack@eecs.umich.edu if (vaddr <= limit && vaddr + req->getSize() >= base) 5655140Sgblack@eecs.umich.edu return new GeneralProtection(0); 5665140Sgblack@eecs.umich.edu } 5675140Sgblack@eecs.umich.edu } 5685140Sgblack@eecs.umich.edu } 5695140Sgblack@eecs.umich.edu // If paging is enabled, do the translation. 5705140Sgblack@eecs.umich.edu if (cr0.pg) { 5715237Sgblack@eecs.umich.edu DPRINTF(TLB, "Paging enabled.\n"); 5725140Sgblack@eecs.umich.edu // The vaddr already has the segment base applied. 5735140Sgblack@eecs.umich.edu TlbEntry *entry = lookup(vaddr); 5745140Sgblack@eecs.umich.edu if (!entry) { 5755140Sgblack@eecs.umich.edu return new TlbFault(vaddr); 5765140Sgblack@eecs.umich.edu } else { 5775140Sgblack@eecs.umich.edu // Do paging protection checks. 5785237Sgblack@eecs.umich.edu DPRINTF(TLB, "Entry found with paddr %#x, doing protection checks.\n", entry->paddr); 5795237Sgblack@eecs.umich.edu Addr paddr = entry->paddr | (vaddr & (entry->size-1)); 5805237Sgblack@eecs.umich.edu DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr); 5815140Sgblack@eecs.umich.edu req->setPaddr(paddr); 5825140Sgblack@eecs.umich.edu } 5835140Sgblack@eecs.umich.edu } else { 5845140Sgblack@eecs.umich.edu //Use the address which already has segmentation applied. 5855237Sgblack@eecs.umich.edu DPRINTF(TLB, "Paging disabled.\n"); 5865237Sgblack@eecs.umich.edu DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 5875140Sgblack@eecs.umich.edu req->setPaddr(vaddr); 5885140Sgblack@eecs.umich.edu } 5895124Sgblack@eecs.umich.edu } else { 5905140Sgblack@eecs.umich.edu // Real mode 5915237Sgblack@eecs.umich.edu DPRINTF(TLB, "In real mode.\n"); 5925237Sgblack@eecs.umich.edu DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 5935140Sgblack@eecs.umich.edu req->setPaddr(vaddr); 5945124Sgblack@eecs.umich.edu } 5955360Sgblack@eecs.umich.edu // Check for an access to the local APIC 5965374Sgblack@eecs.umich.edu#if FULL_SYSTEM 5975360Sgblack@eecs.umich.edu LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE); 5985360Sgblack@eecs.umich.edu Addr baseAddr = localApicBase.base << 12; 5995360Sgblack@eecs.umich.edu Addr paddr = req->getPaddr(); 6005360Sgblack@eecs.umich.edu if (baseAddr <= paddr && baseAddr + (1 << 12) > paddr) { 6015360Sgblack@eecs.umich.edu req->setMmapedIpr(true); 6025417Sgblack@eecs.umich.edu // The Intel developer's manuals say the below restrictions apply, 6035417Sgblack@eecs.umich.edu // but the linux kernel, because of a compiler optimization, breaks 6045417Sgblack@eecs.umich.edu // them. 6055417Sgblack@eecs.umich.edu /* 6065360Sgblack@eecs.umich.edu // Check alignment 6075360Sgblack@eecs.umich.edu if (paddr & ((32/8) - 1)) 6085360Sgblack@eecs.umich.edu return new GeneralProtection(0); 6095360Sgblack@eecs.umich.edu // Check access size 6105360Sgblack@eecs.umich.edu if (req->getSize() != (32/8)) 6115360Sgblack@eecs.umich.edu return new GeneralProtection(0); 6125417Sgblack@eecs.umich.edu */ 6135417Sgblack@eecs.umich.edu 6145417Sgblack@eecs.umich.edu //Make sure we're at least only accessing one register. 6155417Sgblack@eecs.umich.edu if ((paddr & ~mask(3)) != ((paddr + req->getSize()) & ~mask(3))) 6165417Sgblack@eecs.umich.edu panic("Accessed more than one register at a time in the APIC!\n"); 6175360Sgblack@eecs.umich.edu MiscReg regNum; 6185417Sgblack@eecs.umich.edu Addr offset = paddr & mask(3); 6195417Sgblack@eecs.umich.edu paddr &= ~mask(3); 6205360Sgblack@eecs.umich.edu switch (paddr - baseAddr) 6215360Sgblack@eecs.umich.edu { 6225360Sgblack@eecs.umich.edu case 0x20: 6235360Sgblack@eecs.umich.edu regNum = MISCREG_APIC_ID; 6245360Sgblack@eecs.umich.edu break; 6255360Sgblack@eecs.umich.edu case 0x30: 6265360Sgblack@eecs.umich.edu regNum = MISCREG_APIC_VERSION; 6275360Sgblack@eecs.umich.edu break; 6285360Sgblack@eecs.umich.edu case 0x80: 6295360Sgblack@eecs.umich.edu regNum = MISCREG_APIC_TASK_PRIORITY; 6305360Sgblack@eecs.umich.edu break; 6315360Sgblack@eecs.umich.edu case 0x90: 6325360Sgblack@eecs.umich.edu regNum = MISCREG_APIC_ARBITRATION_PRIORITY; 6335360Sgblack@eecs.umich.edu break; 6345360Sgblack@eecs.umich.edu case 0xA0: 6355360Sgblack@eecs.umich.edu regNum = MISCREG_APIC_PROCESSOR_PRIORITY; 6365360Sgblack@eecs.umich.edu break; 6375360Sgblack@eecs.umich.edu case 0xB0: 6385360Sgblack@eecs.umich.edu regNum = MISCREG_APIC_EOI; 6395360Sgblack@eecs.umich.edu break; 6405360Sgblack@eecs.umich.edu case 0xD0: 6415360Sgblack@eecs.umich.edu regNum = MISCREG_APIC_LOGICAL_DESTINATION; 6425360Sgblack@eecs.umich.edu break; 6435360Sgblack@eecs.umich.edu case 0xE0: 6445360Sgblack@eecs.umich.edu regNum = MISCREG_APIC_DESTINATION_FORMAT; 6455360Sgblack@eecs.umich.edu break; 6465360Sgblack@eecs.umich.edu case 0xF0: 6475360Sgblack@eecs.umich.edu regNum = MISCREG_APIC_SPURIOUS_INTERRUPT_VECTOR; 6485360Sgblack@eecs.umich.edu break; 6495360Sgblack@eecs.umich.edu case 0x100: 6505360Sgblack@eecs.umich.edu case 0x108: 6515360Sgblack@eecs.umich.edu case 0x110: 6525360Sgblack@eecs.umich.edu case 0x118: 6535360Sgblack@eecs.umich.edu case 0x120: 6545360Sgblack@eecs.umich.edu case 0x128: 6555360Sgblack@eecs.umich.edu case 0x130: 6565360Sgblack@eecs.umich.edu case 0x138: 6575360Sgblack@eecs.umich.edu case 0x140: 6585360Sgblack@eecs.umich.edu case 0x148: 6595360Sgblack@eecs.umich.edu case 0x150: 6605360Sgblack@eecs.umich.edu case 0x158: 6615360Sgblack@eecs.umich.edu case 0x160: 6625360Sgblack@eecs.umich.edu case 0x168: 6635360Sgblack@eecs.umich.edu case 0x170: 6645360Sgblack@eecs.umich.edu case 0x178: 6655360Sgblack@eecs.umich.edu regNum = MISCREG_APIC_IN_SERVICE( 6665360Sgblack@eecs.umich.edu (paddr - baseAddr - 0x100) / 0x8); 6675360Sgblack@eecs.umich.edu break; 6685360Sgblack@eecs.umich.edu case 0x180: 6695360Sgblack@eecs.umich.edu case 0x188: 6705360Sgblack@eecs.umich.edu case 0x190: 6715360Sgblack@eecs.umich.edu case 0x198: 6725360Sgblack@eecs.umich.edu case 0x1A0: 6735360Sgblack@eecs.umich.edu case 0x1A8: 6745360Sgblack@eecs.umich.edu case 0x1B0: 6755360Sgblack@eecs.umich.edu case 0x1B8: 6765360Sgblack@eecs.umich.edu case 0x1C0: 6775360Sgblack@eecs.umich.edu case 0x1C8: 6785360Sgblack@eecs.umich.edu case 0x1D0: 6795360Sgblack@eecs.umich.edu case 0x1D8: 6805360Sgblack@eecs.umich.edu case 0x1E0: 6815360Sgblack@eecs.umich.edu case 0x1E8: 6825360Sgblack@eecs.umich.edu case 0x1F0: 6835360Sgblack@eecs.umich.edu case 0x1F8: 6845360Sgblack@eecs.umich.edu regNum = MISCREG_APIC_TRIGGER_MODE( 6855360Sgblack@eecs.umich.edu (paddr - baseAddr - 0x180) / 0x8); 6865360Sgblack@eecs.umich.edu break; 6875360Sgblack@eecs.umich.edu case 0x200: 6885360Sgblack@eecs.umich.edu case 0x208: 6895360Sgblack@eecs.umich.edu case 0x210: 6905360Sgblack@eecs.umich.edu case 0x218: 6915360Sgblack@eecs.umich.edu case 0x220: 6925360Sgblack@eecs.umich.edu case 0x228: 6935360Sgblack@eecs.umich.edu case 0x230: 6945360Sgblack@eecs.umich.edu case 0x238: 6955360Sgblack@eecs.umich.edu case 0x240: 6965360Sgblack@eecs.umich.edu case 0x248: 6975360Sgblack@eecs.umich.edu case 0x250: 6985360Sgblack@eecs.umich.edu case 0x258: 6995360Sgblack@eecs.umich.edu case 0x260: 7005360Sgblack@eecs.umich.edu case 0x268: 7015360Sgblack@eecs.umich.edu case 0x270: 7025360Sgblack@eecs.umich.edu case 0x278: 7035360Sgblack@eecs.umich.edu regNum = MISCREG_APIC_INTERRUPT_REQUEST( 7045360Sgblack@eecs.umich.edu (paddr - baseAddr - 0x200) / 0x8); 7055360Sgblack@eecs.umich.edu break; 7065360Sgblack@eecs.umich.edu case 0x280: 7075360Sgblack@eecs.umich.edu regNum = MISCREG_APIC_ERROR_STATUS; 7085360Sgblack@eecs.umich.edu break; 7095360Sgblack@eecs.umich.edu case 0x300: 7105360Sgblack@eecs.umich.edu regNum = MISCREG_APIC_INTERRUPT_COMMAND_LOW; 7115360Sgblack@eecs.umich.edu break; 7125360Sgblack@eecs.umich.edu case 0x310: 7135360Sgblack@eecs.umich.edu regNum = MISCREG_APIC_INTERRUPT_COMMAND_HIGH; 7145360Sgblack@eecs.umich.edu break; 7155360Sgblack@eecs.umich.edu case 0x320: 7165360Sgblack@eecs.umich.edu regNum = MISCREG_APIC_LVT_TIMER; 7175360Sgblack@eecs.umich.edu break; 7185360Sgblack@eecs.umich.edu case 0x330: 7195360Sgblack@eecs.umich.edu regNum = MISCREG_APIC_LVT_THERMAL_SENSOR; 7205360Sgblack@eecs.umich.edu break; 7215360Sgblack@eecs.umich.edu case 0x340: 7225360Sgblack@eecs.umich.edu regNum = MISCREG_APIC_LVT_PERFORMANCE_MONITORING_COUNTERS; 7235360Sgblack@eecs.umich.edu break; 7245360Sgblack@eecs.umich.edu case 0x350: 7255360Sgblack@eecs.umich.edu regNum = MISCREG_APIC_LVT_LINT0; 7265360Sgblack@eecs.umich.edu break; 7275360Sgblack@eecs.umich.edu case 0x360: 7285360Sgblack@eecs.umich.edu regNum = MISCREG_APIC_LVT_LINT1; 7295360Sgblack@eecs.umich.edu break; 7305360Sgblack@eecs.umich.edu case 0x370: 7315360Sgblack@eecs.umich.edu regNum = MISCREG_APIC_LVT_ERROR; 7325360Sgblack@eecs.umich.edu break; 7335360Sgblack@eecs.umich.edu case 0x380: 7345360Sgblack@eecs.umich.edu regNum = MISCREG_APIC_INITIAL_COUNT; 7355360Sgblack@eecs.umich.edu break; 7365360Sgblack@eecs.umich.edu case 0x390: 7375360Sgblack@eecs.umich.edu regNum = MISCREG_APIC_CURRENT_COUNT; 7385360Sgblack@eecs.umich.edu break; 7395360Sgblack@eecs.umich.edu case 0x3E0: 7405360Sgblack@eecs.umich.edu regNum = MISCREG_APIC_DIVIDE_COUNT; 7415360Sgblack@eecs.umich.edu break; 7425360Sgblack@eecs.umich.edu default: 7435360Sgblack@eecs.umich.edu // A reserved register field. 7445360Sgblack@eecs.umich.edu return new GeneralProtection(0); 7455360Sgblack@eecs.umich.edu break; 7465360Sgblack@eecs.umich.edu } 7475417Sgblack@eecs.umich.edu req->setPaddr(regNum * sizeof(MiscReg) + offset); 7485360Sgblack@eecs.umich.edu } 7495374Sgblack@eecs.umich.edu#endif 7505086Sgblack@eecs.umich.edu return NoFault; 7515086Sgblack@eecs.umich.edu}; 7525086Sgblack@eecs.umich.edu 7535140Sgblack@eecs.umich.eduFault 7545140Sgblack@eecs.umich.eduDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 7555140Sgblack@eecs.umich.edu{ 7565140Sgblack@eecs.umich.edu return TLB::translate<FakeDTLBFault>(req, tc, write, false); 7575140Sgblack@eecs.umich.edu} 7585140Sgblack@eecs.umich.edu 7595140Sgblack@eecs.umich.eduFault 7605140Sgblack@eecs.umich.eduITB::translate(RequestPtr &req, ThreadContext *tc) 7615140Sgblack@eecs.umich.edu{ 7625140Sgblack@eecs.umich.edu return TLB::translate<FakeITLBFault>(req, tc, false, true); 7635140Sgblack@eecs.umich.edu} 7645140Sgblack@eecs.umich.edu 7655086Sgblack@eecs.umich.edu#if FULL_SYSTEM 7665086Sgblack@eecs.umich.edu 7675086Sgblack@eecs.umich.eduTick 7685086Sgblack@eecs.umich.eduDTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 7695086Sgblack@eecs.umich.edu{ 7705100Ssaidi@eecs.umich.edu return tc->getCpuPtr()->ticks(1); 7715086Sgblack@eecs.umich.edu} 7725086Sgblack@eecs.umich.edu 7735086Sgblack@eecs.umich.eduTick 7745086Sgblack@eecs.umich.eduDTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 7755086Sgblack@eecs.umich.edu{ 7765100Ssaidi@eecs.umich.edu return tc->getCpuPtr()->ticks(1); 7775086Sgblack@eecs.umich.edu} 7785086Sgblack@eecs.umich.edu 7795086Sgblack@eecs.umich.edu#endif 7805086Sgblack@eecs.umich.edu 7815086Sgblack@eecs.umich.eduvoid 7825086Sgblack@eecs.umich.eduTLB::serialize(std::ostream &os) 7835086Sgblack@eecs.umich.edu{ 7845086Sgblack@eecs.umich.edu} 7855086Sgblack@eecs.umich.edu 7865086Sgblack@eecs.umich.eduvoid 7875086Sgblack@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const std::string §ion) 7885086Sgblack@eecs.umich.edu{ 7895086Sgblack@eecs.umich.edu} 7905086Sgblack@eecs.umich.edu 7915086Sgblack@eecs.umich.eduvoid 7925086Sgblack@eecs.umich.eduDTB::serialize(std::ostream &os) 7935086Sgblack@eecs.umich.edu{ 7945086Sgblack@eecs.umich.edu TLB::serialize(os); 7955086Sgblack@eecs.umich.edu} 7965086Sgblack@eecs.umich.edu 7975086Sgblack@eecs.umich.eduvoid 7985086Sgblack@eecs.umich.eduDTB::unserialize(Checkpoint *cp, const std::string §ion) 7995086Sgblack@eecs.umich.edu{ 8005086Sgblack@eecs.umich.edu TLB::unserialize(cp, section); 8015086Sgblack@eecs.umich.edu} 8025086Sgblack@eecs.umich.edu 8035086Sgblack@eecs.umich.edu/* end namespace X86ISA */ } 8045086Sgblack@eecs.umich.edu 8054997Sgblack@eecs.umich.eduX86ISA::ITB * 8064997Sgblack@eecs.umich.eduX86ITBParams::create() 8074997Sgblack@eecs.umich.edu{ 8085038Sgblack@eecs.umich.edu return new X86ISA::ITB(this); 8094997Sgblack@eecs.umich.edu} 8104997Sgblack@eecs.umich.edu 8114997Sgblack@eecs.umich.eduX86ISA::DTB * 8124997Sgblack@eecs.umich.eduX86DTBParams::create() 8134997Sgblack@eecs.umich.edu{ 8145038Sgblack@eecs.umich.edu return new X86ISA::DTB(this); 8154997Sgblack@eecs.umich.edu} 816