tlb.cc revision 5149 
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use.  Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 *     Director of Intellectual Property Licensing
21 *     Office of Strategy and Technology
22 *     Hewlett-Packard Company
23 *     1501 Page Mill Road
24 *     Palo Alto, California  94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer.  Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution.  Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission.  No right of
34 * sublicense is granted herewith.  Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses.  Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include <cstring>
59
60#include "config/full_system.hh"
61
62#include "arch/x86/pagetable.hh"
63#include "arch/x86/tlb.hh"
64#include "arch/x86/x86_traits.hh"
65#include "base/bitfield.hh"
66#include "base/trace.hh"
67#include "cpu/thread_context.hh"
68#include "cpu/base.hh"
69#include "mem/packet_access.hh"
70#include "mem/request.hh"
71#include "sim/system.hh"
72
73namespace X86ISA {
74
75TLB::TLB(const Params *p) : SimObject(p), size(p->size)
76{
77    tlb = new TlbEntry[size];
78    std::memset(tlb, 0, sizeof(TlbEntry) * size);
79
80    for (int x = 0; x < size; x++)
81        freeList.push_back(&tlb[x]);
82}
83
84void
85TLB::insert(Addr vpn, TlbEntry &entry)
86{
87    //TODO Deal with conflicting entries
88
89    TlbEntry *newEntry = NULL;
90    if (!freeList.empty()) {
91        newEntry = freeList.front();
92        freeList.pop_front();
93    } else {
94        newEntry = entryList.back();
95        entryList.pop_back();
96    }
97    *newEntry = entry;
98    newEntry->vaddr = vpn;
99    entryList.push_front(newEntry);
100}
101
102TlbEntry *
103TLB::lookup(Addr va, bool update_lru)
104{
105    //TODO make this smarter at some point
106    EntryList::iterator entry;
107    for (entry = entryList.begin(); entry != entryList.end(); entry++) {
108        if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) {
109            DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x "
110                    "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size);
111            TlbEntry *e = *entry;
112            if (update_lru) {
113                entryList.erase(entry);
114                entryList.push_front(e);
115            }
116            return e;
117        }
118    }
119    return NULL;
120}
121
122void
123TLB::invalidateAll()
124{
125}
126
127void
128TLB::invalidateNonGlobal()
129{
130}
131
132void
133TLB::demapPage(Addr va)
134{
135}
136
137template<class TlbFault>
138Fault
139TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
140{
141    Addr vaddr = req->getVaddr();
142    DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
143    uint32_t flags = req->getFlags();
144    bool storeCheck = flags & StoreCheck;
145
146    int seg = flags & mask(3);
147
148    //XXX Junk code to surpress the warning
149    if (storeCheck);
150
151    // If this is true, we're dealing with a request to read an internal
152    // value.
153    if (seg == NUM_SEGMENTREGS) {
154        Addr prefix = vaddr & IntAddrPrefixMask;
155        if (prefix == IntAddrPrefixCPUID) {
156            panic("CPUID memory space not yet implemented!\n");
157        } else if (prefix == IntAddrPrefixMSR) {
158            req->setMmapedIpr(true);
159            Addr regNum = 0;
160            switch (vaddr & ~IntAddrPrefixMask) {
161              case 0x10:
162                regNum = MISCREG_TSC;
163                break;
164              case 0xFE:
165                regNum = MISCREG_MTRRCAP;
166                break;
167              case 0x174:
168                regNum = MISCREG_SYSENTER_CS;
169                break;
170              case 0x175:
171                regNum = MISCREG_SYSENTER_ESP;
172                break;
173              case 0x176:
174                regNum = MISCREG_SYSENTER_EIP;
175                break;
176              case 0x179:
177                regNum = MISCREG_MCG_CAP;
178                break;
179              case 0x17A:
180                regNum = MISCREG_MCG_STATUS;
181                break;
182              case 0x17B:
183                regNum = MISCREG_MCG_CTL;
184                break;
185              case 0x1D9:
186                regNum = MISCREG_DEBUG_CTL_MSR;
187                break;
188              case 0x1DB:
189                regNum = MISCREG_LAST_BRANCH_FROM_IP;
190                break;
191              case 0x1DC:
192                regNum = MISCREG_LAST_BRANCH_TO_IP;
193                break;
194              case 0x1DD:
195                regNum = MISCREG_LAST_EXCEPTION_FROM_IP;
196                break;
197              case 0x1DE:
198                regNum = MISCREG_LAST_EXCEPTION_TO_IP;
199                break;
200              case 0x200:
201                regNum = MISCREG_MTRR_PHYS_BASE_0;
202                break;
203              case 0x201:
204                regNum = MISCREG_MTRR_PHYS_MASK_0;
205                break;
206              case 0x202:
207                regNum = MISCREG_MTRR_PHYS_BASE_1;
208                break;
209              case 0x203:
210                regNum = MISCREG_MTRR_PHYS_MASK_1;
211                break;
212              case 0x204:
213                regNum = MISCREG_MTRR_PHYS_BASE_2;
214                break;
215              case 0x205:
216                regNum = MISCREG_MTRR_PHYS_MASK_2;
217                break;
218              case 0x206:
219                regNum = MISCREG_MTRR_PHYS_BASE_3;
220                break;
221              case 0x207:
222                regNum = MISCREG_MTRR_PHYS_MASK_3;
223                break;
224              case 0x208:
225                regNum = MISCREG_MTRR_PHYS_BASE_4;
226                break;
227              case 0x209:
228                regNum = MISCREG_MTRR_PHYS_MASK_4;
229                break;
230              case 0x20A:
231                regNum = MISCREG_MTRR_PHYS_BASE_5;
232                break;
233              case 0x20B:
234                regNum = MISCREG_MTRR_PHYS_MASK_5;
235                break;
236              case 0x20C:
237                regNum = MISCREG_MTRR_PHYS_BASE_6;
238                break;
239              case 0x20D:
240                regNum = MISCREG_MTRR_PHYS_MASK_6;
241                break;
242              case 0x20E:
243                regNum = MISCREG_MTRR_PHYS_BASE_7;
244                break;
245              case 0x20F:
246                regNum = MISCREG_MTRR_PHYS_MASK_7;
247                break;
248              case 0x250:
249                regNum = MISCREG_MTRR_FIX_64K_00000;
250                break;
251              case 0x258:
252                regNum = MISCREG_MTRR_FIX_16K_80000;
253                break;
254              case 0x259:
255                regNum = MISCREG_MTRR_FIX_16K_A0000;
256                break;
257              case 0x268:
258                regNum = MISCREG_MTRR_FIX_4K_C0000;
259                break;
260              case 0x269:
261                regNum = MISCREG_MTRR_FIX_4K_C8000;
262                break;
263              case 0x26A:
264                regNum = MISCREG_MTRR_FIX_4K_D0000;
265                break;
266              case 0x26B:
267                regNum = MISCREG_MTRR_FIX_4K_D8000;
268                break;
269              case 0x26C:
270                regNum = MISCREG_MTRR_FIX_4K_E0000;
271                break;
272              case 0x26D:
273                regNum = MISCREG_MTRR_FIX_4K_E8000;
274                break;
275              case 0x26E:
276                regNum = MISCREG_MTRR_FIX_4K_F0000;
277                break;
278              case 0x26F:
279                regNum = MISCREG_MTRR_FIX_4K_F8000;
280                break;
281              case 0x277:
282                regNum = MISCREG_PAT;
283                break;
284              case 0x2FF:
285                regNum = MISCREG_DEF_TYPE;
286                break;
287              case 0x400:
288                regNum = MISCREG_MC0_CTL;
289                break;
290              case 0x404:
291                regNum = MISCREG_MC1_CTL;
292                break;
293              case 0x408:
294                regNum = MISCREG_MC2_CTL;
295                break;
296              case 0x40C:
297                regNum = MISCREG_MC3_CTL;
298                break;
299              case 0x410:
300                regNum = MISCREG_MC4_CTL;
301                break;
302              case 0x401:
303                regNum = MISCREG_MC0_STATUS;
304                break;
305              case 0x405:
306                regNum = MISCREG_MC1_STATUS;
307                break;
308              case 0x409:
309                regNum = MISCREG_MC2_STATUS;
310                break;
311              case 0x40D:
312                regNum = MISCREG_MC3_STATUS;
313                break;
314              case 0x411:
315                regNum = MISCREG_MC4_STATUS;
316                break;
317              case 0x402:
318                regNum = MISCREG_MC0_ADDR;
319                break;
320              case 0x406:
321                regNum = MISCREG_MC1_ADDR;
322                break;
323              case 0x40A:
324                regNum = MISCREG_MC2_ADDR;
325                break;
326              case 0x40E:
327                regNum = MISCREG_MC3_ADDR;
328                break;
329              case 0x412:
330                regNum = MISCREG_MC4_ADDR;
331                break;
332              case 0x403:
333                regNum = MISCREG_MC0_MISC;
334                break;
335              case 0x407:
336                regNum = MISCREG_MC1_MISC;
337                break;
338              case 0x40B:
339                regNum = MISCREG_MC2_MISC;
340                break;
341              case 0x40F:
342                regNum = MISCREG_MC3_MISC;
343                break;
344              case 0x413:
345                regNum = MISCREG_MC4_MISC;
346                break;
347              case 0xC0000080:
348                regNum = MISCREG_EFER;
349                break;
350              case 0xC0000081:
351                regNum = MISCREG_STAR;
352                break;
353              case 0xC0000082:
354                regNum = MISCREG_LSTAR;
355                break;
356              case 0xC0000083:
357                regNum = MISCREG_CSTAR;
358                break;
359              case 0xC0000084:
360                regNum = MISCREG_SF_MASK;
361                break;
362              case 0xC0000100:
363                regNum = MISCREG_FS_BASE;
364                break;
365              case 0xC0000101:
366                regNum = MISCREG_GS_BASE;
367                break;
368              case 0xC0000102:
369                regNum = MISCREG_KERNEL_GS_BASE;
370                break;
371              case 0xC0000103:
372                regNum = MISCREG_TSC_AUX;
373                break;
374              case 0xC0010000:
375                regNum = MISCREG_PERF_EVT_SEL0;
376                break;
377              case 0xC0010001:
378                regNum = MISCREG_PERF_EVT_SEL1;
379                break;
380              case 0xC0010002:
381                regNum = MISCREG_PERF_EVT_SEL2;
382                break;
383              case 0xC0010003:
384                regNum = MISCREG_PERF_EVT_SEL3;
385                break;
386              case 0xC0010004:
387                regNum = MISCREG_PERF_EVT_CTR0;
388                break;
389              case 0xC0010005:
390                regNum = MISCREG_PERF_EVT_CTR1;
391                break;
392              case 0xC0010006:
393                regNum = MISCREG_PERF_EVT_CTR2;
394                break;
395              case 0xC0010007:
396                regNum = MISCREG_PERF_EVT_CTR3;
397                break;
398              case 0xC0010010:
399                regNum = MISCREG_SYSCFG;
400                break;
401              case 0xC0010016:
402                regNum = MISCREG_IORR_BASE0;
403                break;
404              case 0xC0010017:
405                regNum = MISCREG_IORR_BASE1;
406                break;
407              case 0xC0010018:
408                regNum = MISCREG_IORR_MASK0;
409                break;
410              case 0xC0010019:
411                regNum = MISCREG_IORR_MASK1;
412                break;
413              case 0xC001001A:
414                regNum = MISCREG_TOP_MEM;
415                break;
416              case 0xC001001D:
417                regNum = MISCREG_TOP_MEM2;
418                break;
419              case 0xC0010114:
420                regNum = MISCREG_VM_CR;
421                break;
422              case 0xC0010115:
423                regNum = MISCREG_IGNNE;
424                break;
425              case 0xC0010116:
426                regNum = MISCREG_SMM_CTL;
427                break;
428              case 0xC0010117:
429                regNum = MISCREG_VM_HSAVE_PA;
430                break;
431              default:
432                return new GeneralProtection(0);
433            }
434            //The index is multiplied by the size of a MiscReg so that
435            //any memory dependence calculations will not see these as
436            //overlapping.
437            req->setPaddr(regNum * sizeof(MiscReg));
438            return NoFault;
439        } else {
440            panic("Access to unrecognized internal address space %#x.\n",
441                    prefix);
442        }
443    }
444
445    // Get cr0. This will tell us how to do translation. We'll assume it was
446    // verified to be correct and consistent when set.
447    CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
448
449    // If protected mode has been enabled...
450    if (cr0.pe) {
451        Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
452        SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
453        // If we're not in 64-bit mode, do protection/limit checks
454        if (!efer.lma || !csAttr.longMode) {
455            SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
456            if (!attr.writable && write)
457                return new GeneralProtection(0);
458            if (!attr.readable && !write && !execute)
459                return new GeneralProtection(0);
460            Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
461            Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
462            if (!attr.expandDown) {
463                // We don't have to worry about the access going around the
464                // end of memory because accesses will be broken up into
465                // pieces at boundaries aligned on sizes smaller than an
466                // entire address space. We do have to worry about the limit
467                // being less than the base.
468                if (limit < base) {
469                    if (limit < vaddr + req->getSize() && vaddr < base)
470                        return new GeneralProtection(0);
471                } else {
472                    if (limit < vaddr + req->getSize())
473                        return new GeneralProtection(0);
474                }
475            } else {
476                if (limit < base) {
477                    if (vaddr <= limit || vaddr + req->getSize() >= base)
478                        return new GeneralProtection(0);
479                } else {
480                    if (vaddr <= limit && vaddr + req->getSize() >= base)
481                        return new GeneralProtection(0);
482                }
483            }
484        }
485        // If paging is enabled, do the translation.
486        if (cr0.pg) {
487            // The vaddr already has the segment base applied.
488            TlbEntry *entry = lookup(vaddr);
489            if (!entry) {
490#if FULL_SYSTEM
491                return new TlbFault();
492#else
493                return new TlbFault(vaddr);
494#endif
495            } else {
496                // Do paging protection checks.
497                Addr paddr = entry->pageStart | (vaddr & mask(12));
498                req->setPaddr(paddr);
499            }
500        } else {
501            //Use the address which already has segmentation applied.
502            req->setPaddr(vaddr);
503        }
504    } else {
505        // Real mode
506        req->setPaddr(vaddr);
507    }
508    return NoFault;
509};
510
511Fault
512DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
513{
514    return TLB::translate<FakeDTLBFault>(req, tc, write, false);
515}
516
517Fault
518ITB::translate(RequestPtr &req, ThreadContext *tc)
519{
520    return TLB::translate<FakeITLBFault>(req, tc, false, true);
521}
522
523#if FULL_SYSTEM
524
525Tick
526DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
527{
528    return tc->getCpuPtr()->ticks(1);
529}
530
531Tick
532DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
533{
534    return tc->getCpuPtr()->ticks(1);
535}
536
537#endif
538
539void
540TLB::serialize(std::ostream &os)
541{
542}
543
544void
545TLB::unserialize(Checkpoint *cp, const std::string &section)
546{
547}
548
549void
550DTB::serialize(std::ostream &os)
551{
552    TLB::serialize(os);
553}
554
555void
556DTB::unserialize(Checkpoint *cp, const std::string &section)
557{
558    TLB::unserialize(cp, section);
559}
560
561/* end namespace X86ISA */ }
562
563X86ISA::ITB *
564X86ITBParams::create()
565{
566    return new X86ISA::ITB(this);
567}
568
569X86ISA::DTB *
570X86DTBParams::create()
571{
572    return new X86ISA::DTB(this);
573}
574