tlb.cc revision 11793
14997Sgblack@eecs.umich.edu/* 25417Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 34997Sgblack@eecs.umich.edu * All rights reserved. 44997Sgblack@eecs.umich.edu * 57087Snate@binkert.org * The license below extends only to copyright in the software and shall 67087Snate@binkert.org * not be construed as granting a license to any other intellectual 77087Snate@binkert.org * property including but not limited to intellectual property relating 87087Snate@binkert.org * to a hardware implementation of the functionality of the software 97087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 107087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 117087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 127087Snate@binkert.org * modified or unmodified, in source code or in binary form. 134997Sgblack@eecs.umich.edu * 147087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 157087Snate@binkert.org * modification, are permitted provided that the following conditions are 167087Snate@binkert.org * met: redistributions of source code must retain the above copyright 177087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 187087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 197087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 207087Snate@binkert.org * documentation and/or other materials provided with the distribution; 217087Snate@binkert.org * neither the name of the copyright holders nor the names of its 224997Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 237087Snate@binkert.org * this software without specific prior written permission. 244997Sgblack@eecs.umich.edu * 254997Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 264997Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 274997Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 284997Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 294997Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 304997Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 314997Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 324997Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 334997Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 344997Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 354997Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 364997Sgblack@eecs.umich.edu * 374997Sgblack@eecs.umich.edu * Authors: Gabe Black 384997Sgblack@eecs.umich.edu */ 394997Sgblack@eecs.umich.edu 4011793Sbrandon.potter@amd.com#include "arch/x86/tlb.hh" 4111793Sbrandon.potter@amd.com 424997Sgblack@eecs.umich.edu#include <cstring> 4310474Sandreas.hansson@arm.com#include <memory> 444997Sgblack@eecs.umich.edu 459898Sandreas@sandberg.pp.se#include "arch/generic/mmapped_ipr.hh" 4611793Sbrandon.potter@amd.com#include "arch/x86/faults.hh" 478229Snate@binkert.org#include "arch/x86/insts/microldstop.hh" 4811793Sbrandon.potter@amd.com#include "arch/x86/pagetable.hh" 4911793Sbrandon.potter@amd.com#include "arch/x86/pagetable_walker.hh" 508229Snate@binkert.org#include "arch/x86/regs/misc.hh" 518582Sgblack@eecs.umich.edu#include "arch/x86/regs/msr.hh" 525149Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh" 535086Sgblack@eecs.umich.edu#include "base/bitfield.hh" 545086Sgblack@eecs.umich.edu#include "base/trace.hh" 558229Snate@binkert.org#include "cpu/base.hh" 565086Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 578232Snate@binkert.org#include "debug/TLB.hh" 585086Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 598767Sgblack@eecs.umich.edu#include "mem/page_table.hh" 605086Sgblack@eecs.umich.edu#include "mem/request.hh" 618767Sgblack@eecs.umich.edu#include "sim/full_system.hh" 625895Sgblack@eecs.umich.edu#include "sim/process.hh" 635086Sgblack@eecs.umich.edu 645086Sgblack@eecs.umich.edunamespace X86ISA { 655086Sgblack@eecs.umich.edu 6610905Sandreas.sandberg@arm.comTLB::TLB(const Params *p) 6710905Sandreas.sandberg@arm.com : BaseTLB(p), configAddress(0), size(p->size), 6810905Sandreas.sandberg@arm.com tlb(size), lruSeq(0) 695124Sgblack@eecs.umich.edu{ 708953Sgblack@eecs.umich.edu if (!size) 718953Sgblack@eecs.umich.edu fatal("TLBs must have a non-zero size.\n"); 725124Sgblack@eecs.umich.edu 738953Sgblack@eecs.umich.edu for (int x = 0; x < size; x++) { 748953Sgblack@eecs.umich.edu tlb[x].trieHandle = NULL; 755124Sgblack@eecs.umich.edu freeList.push_back(&tlb[x]); 768953Sgblack@eecs.umich.edu } 775124Sgblack@eecs.umich.edu 785245Sgblack@eecs.umich.edu walker = p->walker; 795245Sgblack@eecs.umich.edu walker->setTLB(this); 805236Sgblack@eecs.umich.edu} 815236Sgblack@eecs.umich.edu 828953Sgblack@eecs.umich.eduvoid 838953Sgblack@eecs.umich.eduTLB::evictLRU() 848953Sgblack@eecs.umich.edu{ 858953Sgblack@eecs.umich.edu // Find the entry with the lowest (and hence least recently updated) 868953Sgblack@eecs.umich.edu // sequence number. 878953Sgblack@eecs.umich.edu 888953Sgblack@eecs.umich.edu unsigned lru = 0; 898953Sgblack@eecs.umich.edu for (unsigned i = 1; i < size; i++) { 908953Sgblack@eecs.umich.edu if (tlb[i].lruSeq < tlb[lru].lruSeq) 918953Sgblack@eecs.umich.edu lru = i; 928953Sgblack@eecs.umich.edu } 938953Sgblack@eecs.umich.edu 948953Sgblack@eecs.umich.edu assert(tlb[lru].trieHandle); 958953Sgblack@eecs.umich.edu trie.remove(tlb[lru].trieHandle); 968953Sgblack@eecs.umich.edu tlb[lru].trieHandle = NULL; 978953Sgblack@eecs.umich.edu freeList.push_back(&tlb[lru]); 988953Sgblack@eecs.umich.edu} 998953Sgblack@eecs.umich.edu 1005895Sgblack@eecs.umich.eduTlbEntry * 1015124Sgblack@eecs.umich.eduTLB::insert(Addr vpn, TlbEntry &entry) 1025124Sgblack@eecs.umich.edu{ 1038962Sgblack@eecs.umich.edu // If somebody beat us to it, just use that existing entry. 1048962Sgblack@eecs.umich.edu TlbEntry *newEntry = trie.lookup(vpn); 1058962Sgblack@eecs.umich.edu if (newEntry) { 1069064Snilay@cs.wisc.edu assert(newEntry->vaddr == vpn); 1078962Sgblack@eecs.umich.edu return newEntry; 1088962Sgblack@eecs.umich.edu } 1095124Sgblack@eecs.umich.edu 1108953Sgblack@eecs.umich.edu if (freeList.empty()) 1118953Sgblack@eecs.umich.edu evictLRU(); 1128962Sgblack@eecs.umich.edu 1138953Sgblack@eecs.umich.edu newEntry = freeList.front(); 1148953Sgblack@eecs.umich.edu freeList.pop_front(); 1158953Sgblack@eecs.umich.edu 1165124Sgblack@eecs.umich.edu *newEntry = entry; 1178953Sgblack@eecs.umich.edu newEntry->lruSeq = nextSeq(); 1185124Sgblack@eecs.umich.edu newEntry->vaddr = vpn; 1198953Sgblack@eecs.umich.edu newEntry->trieHandle = 1208962Sgblack@eecs.umich.edu trie.insert(vpn, TlbEntryTrie::MaxBits - entry.logBytes, newEntry); 1215895Sgblack@eecs.umich.edu return newEntry; 1225124Sgblack@eecs.umich.edu} 1235124Sgblack@eecs.umich.edu 1245360Sgblack@eecs.umich.eduTlbEntry * 1255360Sgblack@eecs.umich.eduTLB::lookup(Addr va, bool update_lru) 1265360Sgblack@eecs.umich.edu{ 1278953Sgblack@eecs.umich.edu TlbEntry *entry = trie.lookup(va); 1288953Sgblack@eecs.umich.edu if (entry && update_lru) 1298953Sgblack@eecs.umich.edu entry->lruSeq = nextSeq(); 1308953Sgblack@eecs.umich.edu return entry; 1315124Sgblack@eecs.umich.edu} 1325124Sgblack@eecs.umich.edu 1335124Sgblack@eecs.umich.eduvoid 1349423SAndreas.Sandberg@arm.comTLB::flushAll() 1355124Sgblack@eecs.umich.edu{ 1365242Sgblack@eecs.umich.edu DPRINTF(TLB, "Invalidating all entries.\n"); 1378953Sgblack@eecs.umich.edu for (unsigned i = 0; i < size; i++) { 1388953Sgblack@eecs.umich.edu if (tlb[i].trieHandle) { 1398953Sgblack@eecs.umich.edu trie.remove(tlb[i].trieHandle); 1408953Sgblack@eecs.umich.edu tlb[i].trieHandle = NULL; 1418953Sgblack@eecs.umich.edu freeList.push_back(&tlb[i]); 1428953Sgblack@eecs.umich.edu } 1435242Sgblack@eecs.umich.edu } 1445124Sgblack@eecs.umich.edu} 1455124Sgblack@eecs.umich.edu 1465124Sgblack@eecs.umich.eduvoid 1475357Sgblack@eecs.umich.eduTLB::setConfigAddress(uint32_t addr) 1485357Sgblack@eecs.umich.edu{ 1495357Sgblack@eecs.umich.edu configAddress = addr; 1505357Sgblack@eecs.umich.edu} 1515357Sgblack@eecs.umich.edu 1525357Sgblack@eecs.umich.eduvoid 1539423SAndreas.Sandberg@arm.comTLB::flushNonGlobal() 1545124Sgblack@eecs.umich.edu{ 1555242Sgblack@eecs.umich.edu DPRINTF(TLB, "Invalidating all non global entries.\n"); 1568953Sgblack@eecs.umich.edu for (unsigned i = 0; i < size; i++) { 1578953Sgblack@eecs.umich.edu if (tlb[i].trieHandle && !tlb[i].global) { 1588953Sgblack@eecs.umich.edu trie.remove(tlb[i].trieHandle); 1598953Sgblack@eecs.umich.edu tlb[i].trieHandle = NULL; 1608953Sgblack@eecs.umich.edu freeList.push_back(&tlb[i]); 1615242Sgblack@eecs.umich.edu } 1625242Sgblack@eecs.umich.edu } 1635124Sgblack@eecs.umich.edu} 1645124Sgblack@eecs.umich.edu 1655124Sgblack@eecs.umich.eduvoid 1665358Sgblack@eecs.umich.eduTLB::demapPage(Addr va, uint64_t asn) 1675086Sgblack@eecs.umich.edu{ 1688953Sgblack@eecs.umich.edu TlbEntry *entry = trie.lookup(va); 1698953Sgblack@eecs.umich.edu if (entry) { 1708953Sgblack@eecs.umich.edu trie.remove(entry->trieHandle); 1718953Sgblack@eecs.umich.edu entry->trieHandle = NULL; 1728953Sgblack@eecs.umich.edu freeList.push_back(entry); 1735359Sgblack@eecs.umich.edu } 1745086Sgblack@eecs.umich.edu} 1755086Sgblack@eecs.umich.edu 1765086Sgblack@eecs.umich.eduFault 1776141Sgblack@eecs.umich.eduTLB::translateInt(RequestPtr req, ThreadContext *tc) 1786141Sgblack@eecs.umich.edu{ 1796141Sgblack@eecs.umich.edu DPRINTF(TLB, "Addresses references internal memory.\n"); 1806141Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr(); 1816141Sgblack@eecs.umich.edu Addr prefix = (vaddr >> 3) & IntAddrPrefixMask; 1826141Sgblack@eecs.umich.edu if (prefix == IntAddrPrefixCPUID) { 1836141Sgblack@eecs.umich.edu panic("CPUID memory space not yet implemented!\n"); 1846141Sgblack@eecs.umich.edu } else if (prefix == IntAddrPrefixMSR) { 1858582Sgblack@eecs.umich.edu vaddr = (vaddr >> 3) & ~IntAddrPrefixMask; 1868105Sgblack@eecs.umich.edu req->setFlags(Request::MMAPPED_IPR); 1878582Sgblack@eecs.umich.edu 1888582Sgblack@eecs.umich.edu MiscRegIndex regNum; 1898582Sgblack@eecs.umich.edu if (!msrAddrToIndex(regNum, vaddr)) 19010474Sandreas.hansson@arm.com return std::make_shared<GeneralProtection>(0); 1918582Sgblack@eecs.umich.edu 1926141Sgblack@eecs.umich.edu //The index is multiplied by the size of a MiscReg so that 1936141Sgblack@eecs.umich.edu //any memory dependence calculations will not see these as 1946141Sgblack@eecs.umich.edu //overlapping. 1958582Sgblack@eecs.umich.edu req->setPaddr((Addr)regNum * sizeof(MiscReg)); 1966141Sgblack@eecs.umich.edu return NoFault; 1976141Sgblack@eecs.umich.edu } else if (prefix == IntAddrPrefixIO) { 1986141Sgblack@eecs.umich.edu // TODO If CPL > IOPL or in virtual mode, check the I/O permission 1996141Sgblack@eecs.umich.edu // bitmap in the TSS. 2006141Sgblack@eecs.umich.edu 2016141Sgblack@eecs.umich.edu Addr IOPort = vaddr & ~IntAddrPrefixMask; 2026141Sgblack@eecs.umich.edu // Make sure the address fits in the expected 16 bit IO address 2036141Sgblack@eecs.umich.edu // space. 2046141Sgblack@eecs.umich.edu assert(!(IOPort & ~0xFFFF)); 2056141Sgblack@eecs.umich.edu if (IOPort == 0xCF8 && req->getSize() == 4) { 2068105Sgblack@eecs.umich.edu req->setFlags(Request::MMAPPED_IPR); 2076141Sgblack@eecs.umich.edu req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg)); 2086141Sgblack@eecs.umich.edu } else if ((IOPort & ~mask(2)) == 0xCFC) { 20910824SAndreas.Sandberg@ARM.com req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 2106141Sgblack@eecs.umich.edu Addr configAddress = 2116141Sgblack@eecs.umich.edu tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS); 2126141Sgblack@eecs.umich.edu if (bits(configAddress, 31, 31)) { 2136141Sgblack@eecs.umich.edu req->setPaddr(PhysAddrPrefixPciConfig | 2146141Sgblack@eecs.umich.edu mbits(configAddress, 30, 2) | 2156141Sgblack@eecs.umich.edu (IOPort & mask(2))); 2168098Sgblack@eecs.umich.edu } else { 2178098Sgblack@eecs.umich.edu req->setPaddr(PhysAddrPrefixIO | IOPort); 2186141Sgblack@eecs.umich.edu } 2196141Sgblack@eecs.umich.edu } else { 22010824SAndreas.Sandberg@ARM.com req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 2216141Sgblack@eecs.umich.edu req->setPaddr(PhysAddrPrefixIO | IOPort); 2226141Sgblack@eecs.umich.edu } 2236141Sgblack@eecs.umich.edu return NoFault; 2246141Sgblack@eecs.umich.edu } else { 2256141Sgblack@eecs.umich.edu panic("Access to unrecognized internal address space %#x.\n", 2266141Sgblack@eecs.umich.edu prefix); 2276141Sgblack@eecs.umich.edu } 2286141Sgblack@eecs.umich.edu} 2296141Sgblack@eecs.umich.edu 2306141Sgblack@eecs.umich.eduFault 2319738Sandreas@sandberg.pp.seTLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const 2329738Sandreas@sandberg.pp.se{ 2339738Sandreas@sandberg.pp.se Addr paddr = req->getPaddr(); 2349738Sandreas@sandberg.pp.se 23510553Salexandru.dutu@amd.com AddrRange m5opRange(0xFFFF0000, 0xFFFFFFFF); 23610553Salexandru.dutu@amd.com 23710553Salexandru.dutu@amd.com if (m5opRange.contains(paddr)) { 23810553Salexandru.dutu@amd.com if (m5opRange.contains(paddr)) { 23911628Smichael.lebeane@amd.com req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR | 24011628Smichael.lebeane@amd.com Request::STRICT_ORDER); 24110553Salexandru.dutu@amd.com req->setPaddr(GenericISA::iprAddressPseudoInst( 24210553Salexandru.dutu@amd.com (paddr >> 8) & 0xFF, 24310553Salexandru.dutu@amd.com paddr & 0xFF)); 24410553Salexandru.dutu@amd.com } 24510553Salexandru.dutu@amd.com } else if (FullSystem) { 24610553Salexandru.dutu@amd.com // Check for an access to the local APIC 2479738Sandreas@sandberg.pp.se LocalApicBase localApicBase = 2489738Sandreas@sandberg.pp.se tc->readMiscRegNoEffect(MISCREG_APIC_BASE); 2499738Sandreas@sandberg.pp.se AddrRange apicRange(localApicBase.base * PageBytes, 2509738Sandreas@sandberg.pp.se (localApicBase.base + 1) * PageBytes - 1); 2519738Sandreas@sandberg.pp.se 2529738Sandreas@sandberg.pp.se if (apicRange.contains(paddr)) { 2539738Sandreas@sandberg.pp.se // The Intel developer's manuals say the below restrictions apply, 2549738Sandreas@sandberg.pp.se // but the linux kernel, because of a compiler optimization, breaks 2559738Sandreas@sandberg.pp.se // them. 2569738Sandreas@sandberg.pp.se /* 2579738Sandreas@sandberg.pp.se // Check alignment 2589738Sandreas@sandberg.pp.se if (paddr & ((32/8) - 1)) 2599738Sandreas@sandberg.pp.se return new GeneralProtection(0); 2609738Sandreas@sandberg.pp.se // Check access size 2619738Sandreas@sandberg.pp.se if (req->getSize() != (32/8)) 2629738Sandreas@sandberg.pp.se return new GeneralProtection(0); 2639738Sandreas@sandberg.pp.se */ 2649738Sandreas@sandberg.pp.se // Force the access to be uncacheable. 26510824SAndreas.Sandberg@ARM.com req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 2669738Sandreas@sandberg.pp.se req->setPaddr(x86LocalAPICAddress(tc->contextId(), 2679738Sandreas@sandberg.pp.se paddr - apicRange.start())); 2689738Sandreas@sandberg.pp.se } 2699738Sandreas@sandberg.pp.se } 2709738Sandreas@sandberg.pp.se 2719738Sandreas@sandberg.pp.se return NoFault; 2729738Sandreas@sandberg.pp.se} 2739738Sandreas@sandberg.pp.se 2749738Sandreas@sandberg.pp.seFault 2756023Snate@binkert.orgTLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation, 2766023Snate@binkert.org Mode mode, bool &delayedResponse, bool timing) 2775086Sgblack@eecs.umich.edu{ 27811608Snikos.nikoleris@arm.com Request::Flags flags = req->getFlags(); 2796141Sgblack@eecs.umich.edu int seg = flags & SegmentFlagMask; 2806141Sgblack@eecs.umich.edu bool storeCheck = flags & (StoreCheck << FlagShift); 2816141Sgblack@eecs.umich.edu 2828535Sgblack@eecs.umich.edu delayedResponse = false; 2838535Sgblack@eecs.umich.edu 2846141Sgblack@eecs.umich.edu // If this is true, we're dealing with a request to a non-memory address 2856141Sgblack@eecs.umich.edu // space. 2866141Sgblack@eecs.umich.edu if (seg == SEGMENT_REG_MS) { 2876141Sgblack@eecs.umich.edu return translateInt(req, tc); 2886141Sgblack@eecs.umich.edu } 2896141Sgblack@eecs.umich.edu 2905124Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr(); 2915140Sgblack@eecs.umich.edu DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr); 2925140Sgblack@eecs.umich.edu 2936141Sgblack@eecs.umich.edu HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); 2945140Sgblack@eecs.umich.edu 2955140Sgblack@eecs.umich.edu // If protected mode has been enabled... 2966141Sgblack@eecs.umich.edu if (m5Reg.prot) { 2975237Sgblack@eecs.umich.edu DPRINTF(TLB, "In protected mode.\n"); 2985140Sgblack@eecs.umich.edu // If we're not in 64-bit mode, do protection/limit checks 2996141Sgblack@eecs.umich.edu if (m5Reg.mode != LongMode) { 3005237Sgblack@eecs.umich.edu DPRINTF(TLB, "Not in long mode. Checking segment protection.\n"); 3015431Sgblack@eecs.umich.edu // Check for a NULL segment selector. 3026059Sgblack@eecs.umich.edu if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR || 3036141Sgblack@eecs.umich.edu seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS) 3046059Sgblack@eecs.umich.edu && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg))) 30510474Sandreas.hansson@arm.com return std::make_shared<GeneralProtection>(0); 3065433Sgblack@eecs.umich.edu bool expandDown = false; 3075965Sgblack@eecs.umich.edu SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg)); 3085433Sgblack@eecs.umich.edu if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) { 3096099Sgblack@eecs.umich.edu if (!attr.writable && (mode == Write || storeCheck)) 31010474Sandreas.hansson@arm.com return std::make_shared<GeneralProtection>(0); 3116023Snate@binkert.org if (!attr.readable && mode == Read) 31210474Sandreas.hansson@arm.com return std::make_shared<GeneralProtection>(0); 3135433Sgblack@eecs.umich.edu expandDown = attr.expandDown; 3145965Sgblack@eecs.umich.edu 3155433Sgblack@eecs.umich.edu } 3165140Sgblack@eecs.umich.edu Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg)); 3175140Sgblack@eecs.umich.edu Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg)); 3185965Sgblack@eecs.umich.edu bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift)); 3199062Sjayneel@cs.wisc.edu unsigned logSize = sizeOverride ? (unsigned)m5Reg.altAddr 3209062Sjayneel@cs.wisc.edu : (unsigned)m5Reg.defAddr; 3219028Sgblack@eecs.umich.edu int size = (1 << logSize) * 8; 3229028Sgblack@eecs.umich.edu Addr offset = bits(vaddr - base, size - 1, 0); 3235965Sgblack@eecs.umich.edu Addr endOffset = offset + req->getSize() - 1; 3245433Sgblack@eecs.umich.edu if (expandDown) { 3255237Sgblack@eecs.umich.edu DPRINTF(TLB, "Checking an expand down segment.\n"); 3265965Sgblack@eecs.umich.edu warn_once("Expand down segments are untested.\n"); 3275965Sgblack@eecs.umich.edu if (offset <= limit || endOffset <= limit) 32810474Sandreas.hansson@arm.com return std::make_shared<GeneralProtection>(0); 3295140Sgblack@eecs.umich.edu } else { 3305965Sgblack@eecs.umich.edu if (offset > limit || endOffset > limit) 33110474Sandreas.hansson@arm.com return std::make_shared<GeneralProtection>(0); 3325140Sgblack@eecs.umich.edu } 3335140Sgblack@eecs.umich.edu } 3349025Sgblack@eecs.umich.edu if (m5Reg.submode != SixtyFourBitMode || 3358925Sgblack@eecs.umich.edu (flags & (AddrSizeFlagBit << FlagShift))) 3368925Sgblack@eecs.umich.edu vaddr &= mask(32); 3375140Sgblack@eecs.umich.edu // If paging is enabled, do the translation. 3386141Sgblack@eecs.umich.edu if (m5Reg.paging) { 3395237Sgblack@eecs.umich.edu DPRINTF(TLB, "Paging enabled.\n"); 3405140Sgblack@eecs.umich.edu // The vaddr already has the segment base applied. 3415140Sgblack@eecs.umich.edu TlbEntry *entry = lookup(vaddr); 3425140Sgblack@eecs.umich.edu if (!entry) { 3438752Sgblack@eecs.umich.edu if (FullSystem) { 3448752Sgblack@eecs.umich.edu Fault fault = walker->start(tc, translation, req, mode); 3458752Sgblack@eecs.umich.edu if (timing || fault != NoFault) { 3468752Sgblack@eecs.umich.edu // This gets ignored in atomic mode. 3478752Sgblack@eecs.umich.edu delayedResponse = true; 3488752Sgblack@eecs.umich.edu return fault; 3498752Sgblack@eecs.umich.edu } 3508752Sgblack@eecs.umich.edu entry = lookup(vaddr); 3518752Sgblack@eecs.umich.edu assert(entry); 3528752Sgblack@eecs.umich.edu } else { 3538752Sgblack@eecs.umich.edu DPRINTF(TLB, "Handling a TLB miss for " 3548752Sgblack@eecs.umich.edu "address %#x at pc %#x.\n", 3558752Sgblack@eecs.umich.edu vaddr, tc->instAddr()); 3568752Sgblack@eecs.umich.edu 3578752Sgblack@eecs.umich.edu Process *p = tc->getProcessPtr(); 3588752Sgblack@eecs.umich.edu TlbEntry newEntry; 3598752Sgblack@eecs.umich.edu bool success = p->pTable->lookup(vaddr, newEntry); 3608752Sgblack@eecs.umich.edu if (!success && mode != Execute) { 3618752Sgblack@eecs.umich.edu // Check if we just need to grow the stack. 3628752Sgblack@eecs.umich.edu if (p->fixupStackFault(vaddr)) { 3638752Sgblack@eecs.umich.edu // If we did, lookup the entry for the new page. 3648752Sgblack@eecs.umich.edu success = p->pTable->lookup(vaddr, newEntry); 3658752Sgblack@eecs.umich.edu } 3668752Sgblack@eecs.umich.edu } 3678752Sgblack@eecs.umich.edu if (!success) { 36810474Sandreas.hansson@arm.com return std::make_shared<PageFault>(vaddr, true, mode, 36910474Sandreas.hansson@arm.com true, false); 3708752Sgblack@eecs.umich.edu } else { 3718752Sgblack@eecs.umich.edu Addr alignedVaddr = p->pTable->pageAlign(vaddr); 3728752Sgblack@eecs.umich.edu DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, 3738752Sgblack@eecs.umich.edu newEntry.pageStart()); 3748752Sgblack@eecs.umich.edu entry = insert(alignedVaddr, newEntry); 3758752Sgblack@eecs.umich.edu } 3768752Sgblack@eecs.umich.edu DPRINTF(TLB, "Miss was serviced.\n"); 3775895Sgblack@eecs.umich.edu } 3785140Sgblack@eecs.umich.edu } 3798646Snilay@cs.wisc.edu 3808646Snilay@cs.wisc.edu DPRINTF(TLB, "Entry found with paddr %#x, " 3818646Snilay@cs.wisc.edu "doing protection checks.\n", entry->paddr); 3825895Sgblack@eecs.umich.edu // Do paging protection checks. 3836141Sgblack@eecs.umich.edu bool inUser = (m5Reg.cpl == 3 && 3845917Sgblack@eecs.umich.edu !(flags & (CPL0FlagBit << FlagShift))); 3857933Stharris@microsoft.com CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 3867933Stharris@microsoft.com bool badWrite = (!entry->writable && (inUser || cr0.wp)); 3877933Stharris@microsoft.com if ((inUser && !entry->user) || (mode == Write && badWrite)) { 3885917Sgblack@eecs.umich.edu // The page must have been present to get into the TLB in 3895917Sgblack@eecs.umich.edu // the first place. We'll assume the reserved bits are 3905917Sgblack@eecs.umich.edu // fine even though we're not checking them. 39110474Sandreas.hansson@arm.com return std::make_shared<PageFault>(vaddr, true, mode, inUser, 39210474Sandreas.hansson@arm.com false); 3935917Sgblack@eecs.umich.edu } 3947933Stharris@microsoft.com if (storeCheck && badWrite) { 3956099Sgblack@eecs.umich.edu // This would fault if this were a write, so return a page 3966099Sgblack@eecs.umich.edu // fault that reflects that happening. 39710474Sandreas.hansson@arm.com return std::make_shared<PageFault>(vaddr, true, Write, inUser, 39810474Sandreas.hansson@arm.com false); 3996099Sgblack@eecs.umich.edu } 4005917Sgblack@eecs.umich.edu 4018953Sgblack@eecs.umich.edu Addr paddr = entry->paddr | (vaddr & mask(entry->logBytes)); 4025895Sgblack@eecs.umich.edu DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr); 4035895Sgblack@eecs.umich.edu req->setPaddr(paddr); 4047775Sgblack@eecs.umich.edu if (entry->uncacheable) 40510824SAndreas.Sandberg@ARM.com req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 4065140Sgblack@eecs.umich.edu } else { 4075140Sgblack@eecs.umich.edu //Use the address which already has segmentation applied. 4085237Sgblack@eecs.umich.edu DPRINTF(TLB, "Paging disabled.\n"); 4095237Sgblack@eecs.umich.edu DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 4105140Sgblack@eecs.umich.edu req->setPaddr(vaddr); 4115140Sgblack@eecs.umich.edu } 4125124Sgblack@eecs.umich.edu } else { 4135140Sgblack@eecs.umich.edu // Real mode 4145237Sgblack@eecs.umich.edu DPRINTF(TLB, "In real mode.\n"); 4155237Sgblack@eecs.umich.edu DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 4165140Sgblack@eecs.umich.edu req->setPaddr(vaddr); 4175124Sgblack@eecs.umich.edu } 4189738Sandreas@sandberg.pp.se 4199738Sandreas@sandberg.pp.se return finalizePhysical(req, tc, mode); 4208902Sandreas.hansson@arm.com} 4215086Sgblack@eecs.umich.edu 4225140Sgblack@eecs.umich.eduFault 4236023Snate@binkert.orgTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 4245140Sgblack@eecs.umich.edu{ 4255895Sgblack@eecs.umich.edu bool delayedResponse; 4266023Snate@binkert.org return TLB::translate(req, tc, NULL, mode, delayedResponse, false); 4275140Sgblack@eecs.umich.edu} 4285140Sgblack@eecs.umich.edu 4295894Sgblack@eecs.umich.eduvoid 4306022Sgblack@eecs.umich.eduTLB::translateTiming(RequestPtr req, ThreadContext *tc, 4316023Snate@binkert.org Translation *translation, Mode mode) 4325894Sgblack@eecs.umich.edu{ 4335895Sgblack@eecs.umich.edu bool delayedResponse; 4345894Sgblack@eecs.umich.edu assert(translation); 4356023Snate@binkert.org Fault fault = 4366023Snate@binkert.org TLB::translate(req, tc, translation, mode, delayedResponse, true); 4375895Sgblack@eecs.umich.edu if (!delayedResponse) 4386023Snate@binkert.org translation->finish(fault, req, tc, mode); 4395894Sgblack@eecs.umich.edu} 4405894Sgblack@eecs.umich.edu 4418888Sgeoffrey.blake@arm.comFault 4428888Sgeoffrey.blake@arm.comTLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) 4438888Sgeoffrey.blake@arm.com{ 4448888Sgeoffrey.blake@arm.com panic("Not implemented\n"); 4458888Sgeoffrey.blake@arm.com return NoFault; 4468888Sgeoffrey.blake@arm.com} 4478888Sgeoffrey.blake@arm.com 4487912Shestness@cs.utexas.eduWalker * 4497912Shestness@cs.utexas.eduTLB::getWalker() 4507912Shestness@cs.utexas.edu{ 4517912Shestness@cs.utexas.edu return walker; 4527912Shestness@cs.utexas.edu} 4537912Shestness@cs.utexas.edu 4545086Sgblack@eecs.umich.eduvoid 45510905Sandreas.sandberg@arm.comTLB::serialize(CheckpointOut &cp) const 4565086Sgblack@eecs.umich.edu{ 4579818Snilay@cs.wisc.edu // Only store the entries in use. 4589818Snilay@cs.wisc.edu uint32_t _size = size - freeList.size(); 4599818Snilay@cs.wisc.edu SERIALIZE_SCALAR(_size); 4609818Snilay@cs.wisc.edu SERIALIZE_SCALAR(lruSeq); 4619818Snilay@cs.wisc.edu 4629818Snilay@cs.wisc.edu uint32_t _count = 0; 4639818Snilay@cs.wisc.edu for (uint32_t x = 0; x < size; x++) { 46410905Sandreas.sandberg@arm.com if (tlb[x].trieHandle != NULL) 46510905Sandreas.sandberg@arm.com tlb[x].serializeSection(cp, csprintf("Entry%d", _count++)); 4669818Snilay@cs.wisc.edu } 4675086Sgblack@eecs.umich.edu} 4685086Sgblack@eecs.umich.edu 4695086Sgblack@eecs.umich.eduvoid 47010905Sandreas.sandberg@arm.comTLB::unserialize(CheckpointIn &cp) 4715086Sgblack@eecs.umich.edu{ 4729818Snilay@cs.wisc.edu // Do not allow to restore with a smaller tlb. 4739818Snilay@cs.wisc.edu uint32_t _size; 4749818Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(_size); 4759818Snilay@cs.wisc.edu if (_size > size) { 4769818Snilay@cs.wisc.edu fatal("TLB size less than the one in checkpoint!"); 4779818Snilay@cs.wisc.edu } 4789818Snilay@cs.wisc.edu 4799818Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(lruSeq); 4809818Snilay@cs.wisc.edu 4819818Snilay@cs.wisc.edu for (uint32_t x = 0; x < _size; x++) { 4829818Snilay@cs.wisc.edu TlbEntry *newEntry = freeList.front(); 4839818Snilay@cs.wisc.edu freeList.pop_front(); 4849818Snilay@cs.wisc.edu 48510905Sandreas.sandberg@arm.com newEntry->unserializeSection(cp, csprintf("Entry%d", x)); 4869818Snilay@cs.wisc.edu newEntry->trieHandle = trie.insert(newEntry->vaddr, 4879818Snilay@cs.wisc.edu TlbEntryTrie::MaxBits - newEntry->logBytes, newEntry); 4889818Snilay@cs.wisc.edu } 4895086Sgblack@eecs.umich.edu} 4905086Sgblack@eecs.umich.edu 4919294Sandreas.hansson@arm.comBaseMasterPort * 4928922Swilliam.wang@arm.comTLB::getMasterPort() 4938864Snilay@cs.wisc.edu{ 4948922Swilliam.wang@arm.com return &walker->getMasterPort("port"); 4958864Snilay@cs.wisc.edu} 4968864Snilay@cs.wisc.edu 4977811Ssteve.reinhardt@amd.com} // namespace X86ISA 4985086Sgblack@eecs.umich.edu 4996022Sgblack@eecs.umich.eduX86ISA::TLB * 5006022Sgblack@eecs.umich.eduX86TLBParams::create() 5014997Sgblack@eecs.umich.edu{ 5026022Sgblack@eecs.umich.edu return new X86ISA::TLB(this); 5034997Sgblack@eecs.umich.edu} 504