system.cc revision 5627
1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * 9 * The software must be used only for Non-Commercial Use which means any 10 * use which is NOT directed to receiving any direct monetary 11 * compensation for, or commercial advantage from such use. Illustrative 12 * examples of non-commercial use are academic research, personal study, 13 * teaching, education and corporate research & development. 14 * Illustrative examples of commercial use are distributing products for 15 * commercial advantage and providing services using the software for 16 * commercial advantage. 17 * 18 * If you wish to use this software or functionality therein that may be 19 * covered by patents for commercial use, please contact: 20 * Director of Intellectual Property Licensing 21 * Office of Strategy and Technology 22 * Hewlett-Packard Company 23 * 1501 Page Mill Road 24 * Palo Alto, California 94304 25 * 26 * Redistributions of source code must retain the above copyright notice, 27 * this list of conditions and the following disclaimer. Redistributions 28 * in binary form must reproduce the above copyright notice, this list of 29 * conditions and the following disclaimer in the documentation and/or 30 * other materials provided with the distribution. Neither the name of 31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 32 * contributors may be used to endorse or promote products derived from 33 * this software without specific prior written permission. No right of 34 * sublicense is granted herewith. Derivatives of the software and 35 * output created using the software may be prepared, but only for 36 * Non-Commercial Uses. Derivatives of the software may be shared with 37 * others provided: (i) the others agree to abide by the list of 38 * conditions herein which includes the Non-Commercial Use restrictions; 39 * and (ii) such Derivatives of the software include the above copyright 40 * notice to acknowledge the contribution from this software where 41 * applicable, this list of conditions and the disclaimer below. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * 55 * Authors: Gabe Black 56 */ 57 58#include "arch/x86/bios/smbios.hh" 59#include "arch/x86/bios/intelmp.hh" 60#include "arch/x86/miscregs.hh" 61#include "arch/x86/system.hh" 62#include "arch/vtophys.hh" 63#include "base/intmath.hh" 64#include "base/loader/object_file.hh" 65#include "base/loader/symtab.hh" 66#include "base/remote_gdb.hh" 67#include "base/trace.hh" 68#include "cpu/thread_context.hh" 69#include "mem/physical.hh" 70#include "params/X86System.hh" 71#include "sim/byteswap.hh" 72 73 74using namespace LittleEndianGuest; 75using namespace X86ISA; 76 77X86System::X86System(Params *p) : 78 System(p), smbiosTable(p->smbios_table), 79 mpFloatingPointer(p->intel_mp_pointer), 80 mpConfigTable(p->intel_mp_table), 81 rsdp(p->acpi_description_table_pointer) 82{} 83 84void 85X86System::startup() 86{ 87 System::startup(); 88 // This is the boot strap processor (BSP). Initialize it to look like 89 // the boot loader has just turned control over to the 64 bit OS. We 90 // won't actually set up real mode or legacy protected mode descriptor 91 // tables because we aren't executing any code that would require 92 // them. We do, however toggle the control bits in the correct order 93 // while allowing consistency checks and the underlying mechansims 94 // just to be safe. 95 96 const int NumPDTs = 4; 97 98 const Addr PageMapLevel4 = 0x70000; 99 const Addr PageDirPtrTable = 0x71000; 100 const Addr PageDirTable[NumPDTs] = 101 {0x72000, 0x73000, 0x74000, 0x75000}; 102 const Addr GDTBase = 0x76000; 103 104 const int PML4Bits = 9; 105 const int PDPTBits = 9; 106 const int PDTBits = 9; 107 108 // Get a port to write the page tables and descriptor tables. 109 FunctionalPort * physPort = threadContexts[0]->getPhysPort(); 110 111 /* 112 * Set up the gdt. 113 */ 114 // Place holder at selector 0 115 uint64_t nullDescriptor = 0; 116 physPort->writeBlob(GDTBase, (uint8_t *)(&nullDescriptor), 8); 117 118 //64 bit code segment 119 SegDescriptor csDesc = 0; 120 csDesc.type.c = 0; // Not conforming 121 csDesc.dpl = 0; // Privelege level 0 122 csDesc.p = 1; // Present 123 csDesc.l = 1; // 64 bit 124 csDesc.d = 0; // default operand size 125 //Because we're dealing with a pointer and I don't think it's 126 //guaranteed that there isn't anything in a nonvirtual class between 127 //it's beginning in memory and it's actual data, we'll use an 128 //intermediary. 129 uint64_t csDescVal = csDesc; 130 physPort->writeBlob(GDTBase, (uint8_t *)(&csDescVal), 8); 131 132 threadContexts[0]->setMiscReg(MISCREG_TSG_BASE, GDTBase); 133 threadContexts[0]->setMiscReg(MISCREG_TSG_LIMIT, 0xF); 134 135 /* 136 * Identity map the first 4GB of memory. In order to map this region 137 * of memory in long mode, there needs to be one actual page map level 138 * 4 entry which points to one page directory pointer table which 139 * points to 4 different page directory tables which are full of two 140 * megabyte pages. All of the other entries in valid tables are set 141 * to indicate that they don't pertain to anything valid and will 142 * cause a fault if used. 143 */ 144 145 // Put valid values in all of the various table entries which indicate 146 // that those entries don't point to further tables or pages. Then 147 // set the values of those entries which are needed. 148 149 // Page Map Level 4 150 151 // read/write, user, not present 152 uint64_t pml4e = X86ISA::htog(0x6); 153 for (int offset = 0; offset < (1 << PML4Bits) * 8; offset += 8) { 154 physPort->writeBlob(PageMapLevel4 + offset, (uint8_t *)(&pml4e), 8); 155 } 156 // Point to the only PDPT 157 pml4e = X86ISA::htog(0x7 | PageDirPtrTable); 158 physPort->writeBlob(PageMapLevel4, (uint8_t *)(&pml4e), 8); 159 160 // Page Directory Pointer Table 161 162 // read/write, user, not present 163 uint64_t pdpe = X86ISA::htog(0x6); 164 for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8) { 165 physPort->writeBlob(PageDirPtrTable + offset, 166 (uint8_t *)(&pdpe), 8); 167 } 168 // Point to the PDTs 169 for (int table = 0; table < NumPDTs; table++) { 170 pdpe = X86ISA::htog(0x7 | PageDirTable[table]); 171 physPort->writeBlob(PageDirPtrTable + table * 8, 172 (uint8_t *)(&pdpe), 8); 173 } 174 175 // Page Directory Tables 176 177 Addr base = 0; 178 const Addr pageSize = 2 << 20; 179 for (int table = 0; table < NumPDTs; table++) { 180 for (int offset = 0; offset < (1 << PDTBits) * 8; offset += 8) { 181 // read/write, user, present, 4MB 182 uint64_t pdte = X86ISA::htog(0x87 | base); 183 physPort->writeBlob(PageDirTable[table] + offset, 184 (uint8_t *)(&pdte), 8); 185 base += pageSize; 186 } 187 } 188 189 /* 190 * Transition from real mode all the way up to Long mode 191 */ 192 CR0 cr0 = threadContexts[0]->readMiscRegNoEffect(MISCREG_CR0); 193 //Turn off paging. 194 cr0.pg = 0; 195 threadContexts[0]->setMiscReg(MISCREG_CR0, cr0); 196 //Turn on protected mode. 197 cr0.pe = 1; 198 threadContexts[0]->setMiscReg(MISCREG_CR0, cr0); 199 200 CR4 cr4 = threadContexts[0]->readMiscRegNoEffect(MISCREG_CR4); 201 //Turn on pae. 202 cr4.pae = 1; 203 threadContexts[0]->setMiscReg(MISCREG_CR4, cr4); 204 205 //Point to the page tables. 206 threadContexts[0]->setMiscReg(MISCREG_CR3, PageMapLevel4); 207 208 Efer efer = threadContexts[0]->readMiscRegNoEffect(MISCREG_EFER); 209 //Enable long mode. 210 efer.lme = 1; 211 threadContexts[0]->setMiscReg(MISCREG_EFER, efer); 212 213 //Activate long mode. 214 cr0.pg = 1; 215 threadContexts[0]->setMiscReg(MISCREG_CR0, cr0); 216 217 /* 218 * Far jump into 64 bit mode. 219 */ 220 // Set the selector 221 threadContexts[0]->setMiscReg(MISCREG_CS, 1); 222 // Manually set up the segment attributes. In the future when there's 223 // other existing functionality to do this, that could be used 224 // instead. 225 SegAttr csAttr = 0; 226 csAttr.writable = 0; 227 csAttr.readable = 1; 228 csAttr.expandDown = 0; 229 csAttr.dpl = 0; 230 csAttr.defaultSize = 0; 231 csAttr.longMode = 1; 232 threadContexts[0]->setMiscReg(MISCREG_CS_ATTR, csAttr); 233 234 threadContexts[0]->setPC(threadContexts[0]->getSystemPtr()->kernelEntry); 235 threadContexts[0]->setNextPC(threadContexts[0]->readPC()); 236 237 // We should now be in long mode. Yay! 238 239 Addr ebdaPos = 0xF0000; 240 Addr fixed, table; 241 242 //Write out the SMBios/DMI table 243 writeOutSMBiosTable(ebdaPos, fixed, table); 244 ebdaPos += (fixed + table); 245 ebdaPos = roundUp(ebdaPos, 16); 246 247 //Write out the Intel MP Specification configuration table 248 writeOutMPTable(ebdaPos, fixed, table); 249 ebdaPos += (fixed + table); 250} 251 252void 253X86System::writeOutSMBiosTable(Addr header, 254 Addr &headerSize, Addr &structSize, Addr table) 255{ 256 // Get a port to write the table and header to memory. 257 FunctionalPort * physPort = threadContexts[0]->getPhysPort(); 258 259 // If the table location isn't specified, just put it after the header. 260 // The header size as of the 2.5 SMBios specification is 0x1F bytes 261 if (!table) 262 table = header + 0x1F; 263 smbiosTable->setTableAddr(table); 264 265 smbiosTable->writeOut(physPort, header, headerSize, structSize); 266 267 // Do some bounds checking to make sure we at least didn't step on 268 // ourselves. 269 assert(header > table || header + headerSize <= table); 270 assert(table > header || table + structSize <= header); 271} 272 273void 274X86System::writeOutMPTable(Addr fp, 275 Addr &fpSize, Addr &tableSize, Addr table) 276{ 277 // Get a port to write the table and header to memory. 278 FunctionalPort * physPort = threadContexts[0]->getPhysPort(); 279 280 // If the table location isn't specified and it exists, just put 281 // it after the floating pointer. The fp size as of the 1.4 Intel MP 282 // specification is 0x10 bytes. 283 if (mpConfigTable) { 284 if (!table) 285 table = fp + 0x10; 286 mpFloatingPointer->setTableAddr(table); 287 } 288 289 fpSize = mpFloatingPointer->writeOut(physPort, fp); 290 if (mpConfigTable) 291 tableSize = mpConfigTable->writeOut(physPort, table); 292 else 293 tableSize = 0; 294 295 // Do some bounds checking to make sure we at least didn't step on 296 // ourselves and the fp structure was the size we thought it was. 297 assert(fp > table || fp + fpSize <= table); 298 assert(table > fp || table + tableSize <= fp); 299 assert(fpSize == 0x10); 300} 301 302 303X86System::~X86System() 304{ 305 delete smbiosTable; 306} 307 308void 309X86System::serialize(std::ostream &os) 310{ 311 System::serialize(os); 312} 313 314 315void 316X86System::unserialize(Checkpoint *cp, const std::string §ion) 317{ 318 System::unserialize(cp,section); 319} 320 321X86System * 322X86SystemParams::create() 323{ 324 return new X86System(this); 325} 326